JP2007214254A - Manufacturing method for semiconductor device and plasma treatment equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide plasma treatment equipment capable of detecting the change of a plasma generating state with a high sensibility, and a manufacturing method for a semiconductor device using the plasma treatment equipment. <P>SOLUTION: The plasma treatment equipment generates a plasma in a chamber 11 through an impedance matching by a matching box 14 from an output from a high-frequency power supply 13. A semiconductor wafer W is plasma-treated while sampling the position voltages of variable capacitors C1 and C2 in the matching box 14 automatically adjusted with the impedance matching by using the plasma treatment equipment. The differential value of the position voltages among continuous sampling points is evaluated by a Δ monitor 18b while using the position voltage collected in a section actually conducting a device process in the position voltages collected at each sampling point as an object, and the standard deviation is evaluated in the position voltages collected by σ monitor section 18c. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a plasma processing apparatus, and more particularly to a semiconductor device manufacturing method including monitoring of a plasma processing apparatus and a technique effective when applied to a plasma processing apparatus used therefor.

  Japanese Patent Laying-Open No. 2005-259941 (Patent Document 1) describes a sputter etching apparatus that detects abnormal discharge using an electrical physical quantity in a matching mechanism. Specifically, for each semiconductor wafer process, the maximum and minimum values of the high-frequency load voltage, RF tune voltage, and electrode voltage included in the matching mechanism are recorded. The minimum value is averaged as needed, and a value obtained by adding a predetermined voltage to each average value is set as a voltage threshold value that is a criterion for abnormal discharge determination. When the semiconductor wafer is processed after the voltage threshold is set, the case where the maximum and minimum values of the electrical physical quantity of the matching mechanism described above exceed the set voltage threshold is regarded as abnormal.

  Japanese Patent Laid-Open No. 2003-234332 (Patent Document 2) monitors a bias voltage of an upper electrode and a lower electrode of a plasma processing apparatus, and detects a plasma abnormality based on a change amount of the bias voltage. Is described. Japanese Patent Application Laid-Open No. 2004-363405 (Patent Document 3) calculates an average value of electrical signals output from a high-frequency power source for each semiconductor wafer, and represents a reference expression representing a change in the average value, and each semiconductor wafer. An abnormality detection method for a plasma processing apparatus that detects an abnormality by calculating a correction formula that reflects the time interval between the processes is described.

Japanese Patent Application Laid-Open No. 10-74734 (Patent Document 4) describes a plasma processing apparatus and a semiconductor device manufacturing method for monitoring abnormal discharge by detecting a change in plasma impedance. In Japanese Patent Laid-Open No. 2001-319922 (Patent Document 5), light emission due to abnormal discharge of plasma is measured by a camera or the like from a window on a chamber wall, and a two-dimensional image by the camera or the like is processed by a processing means. An abnormal discharge detection device that specifies the occurrence of a discharge and the generation position thereof is described. In JP-A-7-326489 (Patent Document 6), a floating electrode is provided in a plasma generation space of a chamber of a sputtering apparatus, and the potential generated in the floating electrode is measured with a voltmeter or the like to detect an abnormality in the plasma. A discharge detector is described.
JP 2005-259941 A JP 2003-234332 A JP 2004-363405 A JP-A-10-74734 JP 2001-319922 A Japanese Patent Laid-Open No. 7-326489

  In recent years, miniaturization of semiconductor devices has progressed, and highly accurate device processes are required. In the device process, processes such as film formation, etching, and ashing are repeatedly performed, and various plasma processing apparatuses are used in these processes. In plasma processing apparatuses, it is known that deposits are generated in the chamber as the usage period elapses, and the plasma generation state changes due to consumption and deterioration of various components. Therefore, in order to realize a highly accurate device process, it is required to detect the change in the plasma generation state with high sensitivity.

  Moreover, what is called abnormal discharge may occur with changes in the plasma generation state. When the abnormal discharge occurs, for example, a phenomenon such as foreign matters mixed on the semiconductor wafer occurs, and thereby a defective product is built. Abnormal discharges often occur once after they occur, and if this discovery is delayed, a large number of defective products are produced, resulting in considerable damage. In order to prevent the creation of such defective products, it is required to detect changes in the plasma generation state with high sensitivity and to detect abnormal discharges or their signs at an early stage.

  In order to detect such a change in the plasma generation state, for example, it is conceivable to use the techniques described in Patent Documents 1 to 6 described above. However, in the technique of Patent Document 2, there is a concern that the detection sensitivity is lowered due to, for example, the influence of the electrostatic chuck provided in the lower electrode. In the technique of Patent Document 3, there is a possibility that abnormal discharge or the like cannot be detected from an electrical signal of a high-frequency power source. Further, in the technique of Patent Document 4, a change in plasma impedance (in practice, a reflected wave from the chamber) is detected, but in practice, this reflected wave is instantly detected by a matching box if the magnitude is below a certain level. Therefore, a relatively small change is not detected and the detection sensitivity may be reduced.

  On the other hand, in the technique of Patent Document 1, it is considered that highly sensitive detection is possible because the electrical physical quantity of the matching box is used. In this technique, a maximum value and a minimum value such as a high-frequency load voltage are detected for each processing of each semiconductor wafer, and pass / fail for each processing of each semiconductor wafer is determined based on these two values. However, it is expected that the maximum and minimum values will be obtained values in a time zone during which no substantial device process is performed within the processing of each semiconductor wafer, and it is not always necessary to generate plasma corresponding to the substantial device process. It does not always represent the state. In addition, when the processing of each semiconductor wafer is evaluated by two values, the maximum value and the minimum value, it is highly possible that an obvious abnormal discharge can be detected, but the degree of influence that affects the small abnormal discharge or the accuracy of the device process. The change in the plasma generation state may be difficult to detect.

  Accordingly, one object of the present invention is to provide a plasma processing apparatus capable of detecting a change in plasma generation state with high sensitivity and a method for manufacturing a semiconductor device using the plasma processing apparatus. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor device manufacturing method according to the present invention performs processing of a semiconductor device using a plasma processing apparatus including a wafer processing container, a high-frequency power source, and a matching box for impedance matching. When processing this semiconductor device, electrical parameters that are automatically adjusted when the matching box performs impedance matching are acquired in time series, and further, an evaluation start point and an evaluation end point are determined. The plasma generation state is evaluated using the time-series electrical parameters acquired during the end point as evaluation targets.

  In this way, it is possible to detect the change in the plasma generation state with high sensitivity by performing the evaluation using the electrical parameters of the matching box. Furthermore, by determining the evaluation start time and evaluation end time, for example, it is possible to evaluate the plasma generation state only for the part where the device process is actually performed, thus realizing highly accurate or highly reliable evaluation. It becomes possible.

  Here, when evaluating the plasma generation state, for example, with respect to the values of each electrical parameter acquired in time series based on the sampling period, these standard deviations or between successive sampling points are used. It is preferable to calculate fluctuation values (difference values) of electrical parameters and to compare and determine these calculated values and preset standard values. As a result, not only large-scale abnormal discharge in the device process but also various abnormalities such as small-scale abnormal discharge can be detected with high sensitivity.

  In addition, many plasma processing apparatuses are equipped with an electrostatic chuck mechanism. However, even with apparatuses equipped with such a mechanism, the plasma generation state can be changed by using the method described above. Can be detected with high sensitivity.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The electrical parameter value of the matching box in the plasma processing apparatus is acquired in time series, and the acquired value between the evaluation start time and the evaluation end time among the acquired values is set as the evaluation target. By calculating and evaluating a standard deviation and a time-series difference value, it is possible to detect a change in plasma generation state with high sensitivity.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a schematic diagram showing an example of the configuration of a plasma processing apparatus according to Embodiment 1 of the present invention. The plasma processing apparatus shown in FIG. 1 includes a plasma processing unit 10 that performs plasma processing on a semiconductor wafer, and an abnormality monitoring unit 18 that monitors the state of the plasma processing unit 10 and performs desired processing according to the monitoring result. Composed. The plasma processing unit 10 observes electrical parameters of a chamber 11 serving as a wafer processing container, a high-frequency power source 13 (for example, 13.56 MHz) for generating plasma in the chamber 11, a matching box 14, and the matching box 14. A C1 position monitor unit 15a and a C2 position monitor unit 15b are included. Further, the plasma processing unit 10 includes a reflected power (Pr) detection unit 16 for observing a reflected wave toward the high frequency power supply 13 and an error for performing various processes when an abnormality in the observation result occurs in the Pr detection unit 16. A processing unit 17 and the like are provided.

  The chamber 11 includes an exhaust port 11b connected to a vacuum pump (not shown) and a gas inlet 11a into which a processing gas is introduced. In the chamber 11, an upper electrode 12a and a lower electrode 12b are provided. Here, a configuration in which the lower electrode 12b is connected to the ground potential GND and the upper electrode 12a is connected to the high frequency power source 13 via the matching box 14 is taken as an example. In such a configuration, plasma is generated between the upper electrode 12a and the lower electrode 12b, and a desired process is performed on the semiconductor wafer W mounted on the lower electrode 12b. Such a plasma generation mechanism is generally called a capacitive coupling type or a parallel plate type.

  In addition to the parallel plate type, there are various types of plasma generation mechanisms. Typical examples include a dielectric coupling type (ICP type) using a dielectric coil and a microwave of 2.45 GHz. Examples include ECR (Electron Cyclotron Resonance) type. Further, the parallel plate type is not limited to the high frequency power supply 13 connected to the upper electrode 12a, but may be connected to the lower electrode 12b. The plasma processing apparatus of the first embodiment only needs to include the matching box 14 in its configuration, and can be similarly applied to devices having different electrode configurations and plasma generation mechanisms as described above.

  The matching box 14 includes, for example, a variable capacitor C2 and an inductor L1 connected in series between the output of the high frequency power supply 13 and the upper electrode 12a, and a variable capacitor C1 connected between the output of the high frequency power supply 13 and the ground potential GND. Is provided. In general, one of the variable capacitors C1 and C2 is for coarse adjustment, and the other is for fine adjustment. Although a variable capacitor is used here, for example, a parallel inductor can be replaced with a series inductor, so a variable inductor can also be used.

  The sizes of the variable capacitors C1 and C2 (here, the C1 value is a matching value and the C2 value is a tune value) are determined when the plasma is generated between the upper electrode 12a and the lower electrode 12b by the high frequency power source 13. The reflected wave from is detected by the Pr detector 16 and automatically adjusted to a value that eliminates the reflected wave. That is, in order to efficiently supply power to the plasma portion, the value is automatically adjusted to a value that allows impedance matching with the plasma portion. At this time, if the reflected wave detected by the Pr detection unit 16 is large and the reflected wave cannot be suppressed in the adjustment range of the variable capacitors C1 and C2, error processing is performed by the error processing unit 17. Examples of the error processing include alarm transmission and interlock (device stop processing).

  The C1 position monitor unit 15a and the C2 position monitor unit 15b monitor the positions of the variable capacitors C1 and C2 in the matching box 14 as voltage signals, respectively. The monitored voltage signal is output to the abnormality monitoring unit 18. The abnormality monitoring unit 18 includes, for example, a sequence control unit 18a, a Δ monitoring unit 18b, a σ monitoring unit 18c, and the like. The processing contents of the abnormality monitoring unit 18 will be described with reference to FIG.

  FIG. 2 is a schematic diagram for explaining an example of processing contents of the abnormality monitoring unit in the plasma processing apparatus of FIG. In FIG. 2, the horizontal axis is the time axis, and the reflected power Pr and the position voltages of the variable capacitors C1 and C2 are changed in each time zone in one wafer process. When the high-frequency power supply 13 is turned on, as shown in FIG. 2, normally, the large reflected power Pr is detected by the Pr detector 16, and the variable capacitors C1 and C2 in the matching box 14 are received from the non-operating section to the changing section. Migrate to Within the fluctuation section, the values of the variable capacitors C1 and C2 automatically change so that the reflected power Pr is reduced, and when the impedance matching is achieved, the operation stable section is reached. Normally, in the stable operation period, the C1 and C2 values do not change so much unless an abnormality occurs in the plasma state.

  In such processing, the sequence control unit 18a in the abnormality monitoring unit 18 sets a time interval (that is, a sampling cycle) for acquiring C1 and C2 in time series, and sets a time zone for evaluating the acquired value. Settings and control of the Δ monitoring unit 18b and the σ monitoring unit 18c are performed. Specifically, the sequence control unit 18a sets a time zone (that is, an operation stable interval) ST after the plasma discharge is stabilized after plasma generation as a time zone for evaluating the values of C1 and C2. Then, the value of the first sampling point in this time zone ST is set to V0, and thereafter, values are acquired in time series such as V1, V2,..., Vn−1, Vn for each sampling period. The sampling period can be set arbitrarily, but a shorter one can realize highly accurate plasma evaluation. Actually, for example, a value of about 0.01 ms can be set.

  The Δ monitoring unit 18b in the abnormality monitoring unit 18 calculates a difference value Δ of acquired values for each sampling period. That is, Δ [1] = | V1-V0 |, Δ [2] = | V2-V1 |,..., Δ [n] = | Vn− (Vn−1) | Then, under the control of the sequence control unit 18a, it is verified whether or not each difference value Δ exceeds a preset standard value. The σ monitoring unit 18c in the abnormality monitoring unit 18 calculates the standard deviation σ of the acquired value for each sampling period. That is, the standard deviation of V0, V1,..., Vn is calculated. Then, under the control of the sequence control unit 18a, it is verified whether or not the standard deviation σ exceeds a preset standard value. If each verification result exceeds the standard value, the error processing unit 17 shown in FIG. 1 is notified, and processing such as alarm transmission and device stop is performed.

  FIG. 3 is a graph showing an example of the monitoring result of the σ monitoring unit in the plasma processing apparatus of FIG. 1, wherein (a) shows an example during normal operation, and (b) shows an example during abnormal operation. is there. In FIG. 3A, there is a portion where the value of the standard deviation σ varies between wafer processes (for each wafer in the case of a single wafer type), but the standard value is not exceeded. On the other hand, in FIG. 3B, there are locations where the standard deviation σ varies greatly between the wafer processes, and there are locations where the standard value is exceeded. The semiconductor wafer corresponding to this location is determined to be abnormal by the abnormality monitoring unit 18. In this case, the semiconductor wafer is examined for, for example, a foreign matter due to the occurrence of abnormal discharge or a decrease in device accuracy. In some cases, it is also necessary to investigate the inside of the chamber 11.

  As described above, for example, the following effects can be obtained by using the plasma processing apparatus of the first embodiment.

  (1) By using the electrical parameters of the matching box (for example, the values of C1 and C2) for the evaluation of the plasma generation state, it is possible to detect a change in the plasma generation state with high sensitivity and realize a highly accurate evaluation. At this time, a stricter evaluation can be realized by setting a section where the device process is substantially performed (operation stable section ST in FIG. 2) and evaluating the values of C1 and C2. That is, the accuracy and reliability of the evaluation can be improved by excluding values in an unstable time zone at the beginning of plasma generation.

  (2) A highly accurate evaluation can be realized by evaluating the time-series acquired values of C1 and C2 in the process of each semiconductor wafer based on the difference value Δ and the standard deviation σ. That is, for example, when the C1 and C2 values vary only for a relatively short period, the abnormality can be detected with high sensitivity by the difference value Δ, and even if the variation between the sampling points is relatively small, When it occurs over a long period of time, the abnormality can be detected with high sensitivity by the standard deviation σ. As a result, in the process of each semiconductor wafer, not only large-scale abnormal discharge but also small-scale abnormal discharge occurred, and abnormalities that affect device processing accuracy due to instability of the plasma state occurred. Even in cases, it can be detected with high sensitivity.

  (3) By the above (1) and (2), it is possible to realize cost reduction by preventing the creation of defective products, improvement of device processing accuracy, and improvement of manufacturing efficiency by optimally grasping device maintenance time. Become.

(Embodiment 2)
FIG. 4 is a schematic diagram showing an example of the configuration of the plasma processing apparatus according to the second embodiment of the present invention. The plasma processing apparatus shown in FIG. 4 includes a plasma processing unit 40 that performs plasma processing on a semiconductor wafer, and an abnormality monitoring unit 48 that monitors the state of the plasma processing unit 40 and performs desired processing according to the monitoring result. Composed. The plasma processing apparatus shown in FIG. 4 is slightly different from the plasma processing apparatus shown in FIG. The abnormality monitoring unit 48 has the same configuration and operation as the abnormality monitoring unit 18 shown in FIG. 1, and includes a sequence control unit 48a, a Δ monitoring unit 48b, and a σ monitoring unit 48c.

  As in the configuration of FIG. 1, the plasma processing unit 40 includes a chamber 41, a high frequency power supply 43 and a matching box 44, a C1 position monitor unit 45a and a C2 position monitor unit 45b, a reflected power (Pr) detection unit 46, An error processing unit 47 is provided. The chamber 41 also includes an exhaust port 41b and a gas inflow port 41a, as in the configuration of FIG. 1, and an upper electrode 42a and a lower electrode 42b are provided in the chamber 41.

  Here, the difference from the configuration example of FIG. 1 is that an electrostatic chuck 42c is provided on the lower electrode 42b, and a voltage can be applied to the electrostatic chuck 42c by the DC voltage source 49. It is. Further, the upper electrode 42a side is connected to the ground potential GND, and a high frequency signal is applied to the lower electrode 42b side from the high frequency power supply 43 via the matching box 44. As a typical example, for example, in a plasma CVD apparatus for forming a film, a high-frequency signal is normally applied to the upper electrode as shown in FIG. 1, and in a RIE (Reactive Ion Etching) apparatus for performing etching, as shown in FIG. Thus, a high frequency signal is applied to the lower electrode.

  The electrostatic chuck 42c is made of, for example, a dielectric material or an insulating material, and has a configuration in which a conductor pattern is embedded therein. In such a configuration, the semiconductor wafer W is mounted on the electrostatic chuck mechanism 42c, and a voltage is applied from the DC voltage source 49 to the conductor pattern inside the electrostatic chuck 42c, thereby using the clone force. The semiconductor wafer W is adsorbed. In addition, the semiconductor wafer W can be adsorbed by using a Johnson labeling force that generates an electric adsorption force by a minute current flowing through the insulating material. Note that the plasma processing apparatus of the second embodiment is only required to include the electrostatic chuck 42c and the matching box 44. As in the case of the first embodiment, the plasma processing apparatus has a different electrode configuration and plasma generation mechanism. Is equally applicable.

  In the plasma processing apparatus provided with such an electrostatic chuck 42c, since the insulating component of the electrostatic chuck portion influences, in the method of measuring the bias voltage Vdc of the lower electrode 42b as shown in Patent Document 2 described above, Measurement accuracy or sensitivity may be reduced. Further, in addition to the insulating component of the electrostatic chuck portion, the insulating component may change due to the deposits generated in the device process, so that stable measurement is expected to be difficult. On the other hand, such a problem does not occur in the method of measuring the electrical parameters of the matching box 44 as shown in FIG.

  Therefore, by using the plasma processing apparatus of the second embodiment, in addition to the effects (1) to (3) described in the first embodiment, a widely used electrostatic chuck is provided. Also for the plasma processing apparatus, it is possible to detect the change in the plasma generation state with high sensitivity.

(Embodiment 3)
In the third embodiment, assuming that the plasma processing apparatus as described in the first and second embodiments is, for example, a plasma CVD apparatus, processing contents when a film forming process is performed using this apparatus will be described.

  FIG. 5 is a flowchart showing an example of processing contents in the method of manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 6 is an explanatory diagram showing an example of the state of the matching box of the plasma processing apparatus, corresponding to the flowchart of FIG. Each of FIGS. 7 to 9 is a device cross-sectional view showing a configuration example of a part of a semiconductor device formed with the flowchart of FIG. Hereinafter, the description will be made based on the plasma processing apparatus of FIG. 1, but the same applies to the case of FIG.

In the processing flow of FIG. 5, in the plasma processing unit 10 of FIG. 1, first, the semiconductor wafer W is loaded into the chamber 11 and mounted and adsorbed on the lower electrode 12b (S501). Here, it is assumed that a part of the configuration of the semiconductor wafer W in this initial state is, for example, as shown in FIG. In the semiconductor wafer (semiconductor device) W shown in FIG. 7, for example, an insulating layer 70 such as SiO ₂ is formed on an upper layer portion of a semiconductor substrate (not shown), a barrier layer 71 such as TiN / Ti is formed on the insulating layer 70, Al— A metal layer 72 such as Cu and an antireflection layer 73 such as TiN are sequentially formed. This is, for example, a device state in a multilayer wiring process.

Next, TEOS / O ₂ gas is introduced from the gas inlet 11a in a state where the chamber 11 is sufficiently evacuated (S502). Thereafter, the output of the high-frequency power supply 13 is turned on while the gas inflow is stable. Then, plasma is generated between the upper electrode 12a and the lower electrode 12b, and impedance matching is automatically performed by the matching box 14 (S504). That is, the values (position voltages) of the variable capacitors C1 and C2 in the matching box 14 change and are automatically adjusted to an optimal position where impedance matching can be achieved (S505). When impedance matching is performed, the plasma becomes a stable discharge region, and TEOS and O ₂ react with each other on the main surface portion of the semiconductor wafer W as shown in FIG. An interlayer insulating layer 74 such as TEOS SiO ₂ is formed. When the interlayer insulating layer 74 is formed to have a desired film thickness, the output of the high frequency power supply 13 is turned off (S507).

  In such a series of processes, the position voltage V of the variable capacitors C1 and C2 in the matching box 14 varies as shown in FIG. 6, for example. In FIG. 6, the horizontal axis represents time, and the vertical axis represents the position voltage V of the variable capacitors C1 and C2. When the output of the high frequency power supply 13 is turned on, the position voltages of the variable capacitors C1 and C2 start to fluctuate from an unspecified position voltage in accordance with the processing of S504 and S505 in FIG. When the impedance matching is achieved, the position voltage fluctuation stops. This section from the start to the stop will be referred to as a fluctuation section. After the fluctuation section, the stable discharge region described in S506 of FIG. In this stable discharge region, the plasma generation state is stable, and normally the position voltages of the variable capacitors C1 and C2 hardly change as shown in FIG.

  On the other hand, in parallel with the processing of the plasma processing unit 10 as described above, the abnormality monitoring unit 18 performs processing as shown on the right side of FIG. First, in response to the output of the high frequency power supply 13 being turned on in S503, a start signal is notified to the sequence control unit 18a (S511). When the start signal is notified, the sequence control unit 18a sets the evaluation start point for the position voltages of the variable capacitors C1 and C2 (S517). Here, the evaluation start time point is a time point at which the evaluation of the plasma generation state is started within a section where the device process is substantially performed. Specifically, the processing in S517 is performed as in S512 to S516 below, for example.

  In S512, in response to the start signal in S511, sampling collection of the position voltages of the variable capacitors C1 and C2 is started. In S513, for each sampling point, the difference between the acquired position voltage value and the position voltage value acquired at the previous sampling point is calculated using the Δ monitoring unit 18b. Then, it is determined whether the calculated difference value is 0 (or can be arbitrarily set to a value close to 0) (S514). If this determination result is 0, the time is set as the evaluation start time of the position voltages of the variable capacitors C1 and C2, and the position voltage of the variable capacitors C1 and C2 at the start of evaluation is determined as the initial value V0. (S515). On the other hand, if the determination result is not 0, an unnecessary acquired value (that is, a position voltage value acquired at the previous sampling point) is deleted (S516), and the process proceeds to S512. Gets the position voltage value at the next sampling point.

  The processing here corresponds to the processing in the fluctuation section in FIG. That is, the position voltages V of the variable capacitors C1 and C2 are acquired at a predetermined sampling period, and the processes of S512 to S514 and S516 are repeated until the difference between the acquired values becomes 0 in each sampling period. When the difference between the acquired values becomes 0 (that is, when the slope of the position voltage V is 0 in FIG. 6), that time is set as the evaluation start time, and the initial value V0 (C1) of the position voltage of the variable capacitor C1 and the variable capacitor An initial value V0 (C2) of the position voltage of C2 is determined.

  In S517, the method of detecting the start point of the stable discharge region, which is the section in which the device process is substantially performed, from the difference between the position voltages of the variable capacitors C1 and C2, is shown. Since the time until the time is approximately constant, the determination process at the evaluation start time in S517 can be realized by a timer or the like.

  When the initial values of the position voltages of the variable capacitors C1 and C2 are determined in S515, the position voltage values are continuously collected based on the sampling period (S518). The acquired value of the position voltage at each sampling point is stored as V1, V2,..., Vn (n is a sampling point No.) including the initial value V0. Here, the time point when the evaluation of the position voltage of the variable capacitors C1 and C2 ends is the time point when the output of the high frequency power supply 13 is turned off. In this case, in response to the output of the high-frequency power source 13 being turned off in S507 described above, the sequence control unit 18a stops collecting the position voltage (S519). Note that the position voltage evaluation end time can also be set using a timer or the like, similar to the above-described evaluation start time.

  The acquired value of the position voltage collected in this way is stored in a collected data buffer serving as a storage device (S520). In S521, the Δ monitoring unit 18b reads the data from the collected data buffer, and calculates the difference value Δ = | Vn− (Vn−1) | Then, the Δ monitoring unit 18b determines whether this Δ exceeds the preset standard value J (S522). Here, if not exceeding, it is determined as normal, and the difference value Δ obtained by the calculation is stored in the storage device in a state where it can be identified as normal data (S523).

  On the other hand, if it has exceeded, it is determined as abnormal and stored in the storage device in a state where it can be identified as abnormal data (S524). Note that the number of integrations may be set in the normal / abnormal determination at S522, for example. That is, for example, when the number of times of integration is set to 2, continuous Δ [n−1] (= | (Vn−1) − (Vn−2) |) and Δ [n] (= | Vn− (Vn -1) If both | exceed the standard value J, it is determined as abnormal. If it is determined in S522 that the difference value Δ is abnormal, the data is stored in S524 and notified to the error processing unit 17 in FIG. Then, the error processing unit 17 performs a desired process such as sending an alarm or stopping the apparatus (S529), and the stored value of Δ corresponding to the normal / abnormal time in S523 and S524 is the same as that. By accumulating, it is used to appropriately determine the standard value J.

  If the difference value Δ is determined to be normal in S522, the data storage process is performed in S523, while the position voltage value (V0,..., V0,..., Acquired by the σ monitoring unit 18c in FIG. The standard deviation σ is calculated for Vn). And the (sigma) monitoring part 18c determines whether this standard deviation (sigma) exceeds the preset standard value K (S526). Here, if it does not exceed, it is determined as normal, and the standard deviation σ obtained by the calculation is stored in the storage device in a state where it can be identified as normal data (S527). Then, usually, the process returns to S501 and the next semiconductor wafer is processed.

  On the other hand, if it has exceeded, it is determined as abnormal and stored in the storage device in a state where it can be identified as abnormal data (S528). It should be noted that, in the normal / abnormal determination in S526, the number of integrations may be set in the same manner as the difference value Δ. However, in the case of the standard deviation σ, one calculation result is obtained for one device process (one semiconductor wafer process in the case of a single wafer type). In the case where the standard value K is exceeded in two consecutive device processes, it is determined that there is an abnormality. If it is determined that there is an abnormality in S526, desired error processing is performed in S529 described above. Further, the storage value of σ corresponding to normal / abnormal in S527 and S528 is used to appropriately determine the standard value K by accumulating the stored value.

  FIG. 10 is an explanatory diagram showing an example of the state of the matching box of the plasma processing apparatus when an abnormality occurs, corresponding to the flowchart of FIG. As shown in FIG. 10, in the stable discharge region, when an abnormality occurs in the plasma generation state, the impedance matching state is disturbed, and the matching operation is automatically performed according to this, so that the variable capacitors C1 and C2 The position voltage V varies. Although this fluctuation waveform can take various shapes depending on the abnormal situation, it is obvious that a large-scale abnormal discharge can be obtained by evaluating the difference value Δ and the standard deviation σ as in the processing flow of FIG. It is considered that most abnormalities can be detected, including abnormal discharges on a scale and abnormalities that affect device processing accuracy. When a large-scale abnormal discharge occurs, for example, a device state as shown in FIG. 11 is obtained.

  FIG. 11 is a device cross-sectional view showing a configuration example of a part of the semiconductor device when a large-scale abnormal discharge occurs in the processing flow of FIG. As shown in FIG. 11, when a large-scale abnormal discharge occurs, a large number of foreign matters 75 adhere to the semiconductor wafer W due to peeling off of the deposits in the chamber 11 or the interlayer insulating layer 74. There are various problems that lead to product defects such as peeling off, and failure to form the interlayer insulating layer 74 normally. If the processing flow of FIG. 5 is used, the semiconductor wafer W in which such a problem has occurred can be reliably detected, and the subsequent inspection of the apparatus and the like can reliably prevent the formation of defective products thereafter.

  As described above, by using the method for manufacturing a semiconductor device according to the third embodiment, it is possible to realize a film forming process with various effects as described in the first and second embodiments. Further, by strictly managing the standard values of the difference value Δ and the standard deviation σ, it is possible to sufficiently manage the process accuracy even for a film forming process that requires high accuracy, for example. In the processing flow of FIG. 5, the difference value Δ and the standard deviation σ are determined at the end of the processing of the semiconductor wafer. However, the determination is performed sequentially during the processing of the semiconductor wafer, and immediately when an abnormality occurs. It is also possible to perform error processing.

(Embodiment 4)
In the fourth embodiment, assuming that the plasma processing apparatus as described in the first and second embodiments is, for example, an RIE apparatus, processing contents when an etching process is performed using this apparatus will be described.

  FIG. 12 is a flowchart showing an example of processing contents in the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention. FIG. 13 is an explanatory view showing a state example of the matching box of the plasma processing apparatus corresponding to the flowchart of FIG. Each of FIG. 14 to FIG. 16 is a device sectional view showing a configuration example of a part of a semiconductor device formed in accordance with the flowchart of FIG. In the following, description will be made based on the plasma processing apparatus of FIG. 4, but the same applies to the case of FIG.

In the processing flow of FIG. 12, in the plasma processing unit 40 of FIG. 4, first, the semiconductor wafer W is loaded into the chamber 41 and mounted on the electrostatic chuck 42c. Then, the semiconductor wafer W is attracted onto the electrostatic chuck 42c by applying a voltage from the DC voltage source 49 (S1201). Here, it is assumed that a part of the configuration of the semiconductor wafer W in this initial state is as shown in FIG. 14, for example. In the semiconductor wafer (semiconductor device) W shown in FIG. 14, for example, an insulating layer 140 such as SiO ₂ is formed on an upper layer portion of a semiconductor substrate (not shown), a barrier layer 141 such as TiN / Ti is formed on the insulating layer 140, Al− A metal layer 142 such as Cu and an antireflection layer 143 such as TiN are sequentially formed. A resist 144 for patterning is applied on the antireflection layer 143. This is, for example, a device state in a multilayer wiring process.

Next, BCl ₃ / Cl ₂ gas is introduced from the gas inlet 41a while the chamber 41 is sufficiently evacuated (S1202). Thereafter, the output of the high frequency power supply 43 is turned on in a state where the gas inflow is stable. Then, plasma is generated between the upper electrode 42a and the lower electrode 42b, and impedance matching is automatically performed by the matching box 44 (S1204). In other words, the values (position voltages) of the variable capacitors C1 and C2 in the matching box 44 change and are automatically adjusted to an optimum position where impedance matching can be achieved (S1205).

When impedance matching is performed, the plasma becomes a stable discharge region, and Cl ions and Cl radicals are activated on the main surface portion of the semiconductor wafer W as shown in FIG. 15, and reaction products Al _X Cl _Y and Resist decomposition products C _X Cl _Y are discharged. By performing the etching in this manner, a wiring pattern having a desired shape including the barrier layer 141, the metal layer 142, and the antireflection layer 143 is formed as shown in FIG. When the etching is performed to the extent that it reaches the insulating layer 140, the output of the high frequency power supply 43 is turned off (S1207).

  In such a series of processes, the position voltage V of the variable capacitors C1 and C2 in the matching box 44 varies as shown in FIG. 13, for example. In FIG. 6, the horizontal axis represents time, and the vertical axis represents the position voltage V of the variable capacitors C1 and C2. When the output of the high frequency power supply 43 is turned on, the position voltages of the variable capacitors C1 and C2 start to fluctuate from an unspecified position voltage in accordance with the processing of S1204 and S1205 in FIG. When the impedance matching is achieved, the position voltage fluctuation stops. Thereafter, a stable discharge section is reached, and the antireflection film 143, the metal layer 142, the barrier layer 141, and the insulating layer 140 are etched in this order. However, in reality, the plasma generation state (plasma impedance) may be slightly different depending on the layer to be etched. In this case, the position voltage of the variable capacitors C1 and C2 shifts at the switching portion of this layer. Will do.

  On the other hand, in parallel with the processing of the plasma processing unit 40 as described above, the abnormality monitoring unit 48 performs processing as shown on the right side of FIG. The processing of the abnormality monitoring unit 48 in FIG. 12 is substantially the same as the processing of the abnormality monitoring unit described in FIG. 5, but with the shift of the position voltage due to switching of each layer described in FIG. It is necessary to consider how to determine the end point. Therefore, here, the determination process of the evaluation start time in S1217 of FIG. 12 is performed using a timer as in S1212 to S1215.

  That is, when the start signal is notified to the sequence control unit 48a of the abnormality monitoring unit 48 in response to the output of the high-frequency power source 43 being turned on in S1203 (S1211), the position voltage is updated at a preset sampling cycle in S1212. Start sampling collection. In step S1213, the apparatus waits for a preset time starting from the notification of the start signal in step S1211, and sets the time when the set time has elapsed as the evaluation start time. In S1215, the position voltages of the variable capacitors C1 and C2 acquired at the sampling position closest to the evaluation start time are determined as initial values V0 (C1) and V0 (C2), respectively. Thereby, for example, as shown in FIG. 13, the evaluation can be focused on the etching process of the metal layer 142.

  Subsequently, in S1218, the position voltage is continuously collected at each sampling point as in S518 of FIG. 5, and then the collection of the position voltage is stopped in S1219. This stop time (that is, evaluation end time) is determined using a timer in the same manner as the evaluation start time. The subsequent processing of S1220 to S1229 is performed in the same manner as the processing of S520 to S529 of FIG. 5 described above, and various processing is performed based on the determination result of the difference value Δ and the standard deviation σ with respect to the standard value.

  Here, the determination process of the evaluation start time and the evaluation end time in S1217 and S1219 is performed using a timer, but this determination process is realized by applying processes such as S512 to S516 in FIG. It is also possible to do. That is, by using the processing such as S512 to S516 described above, the switching portion of the layer to be etched in FIG. 13 can be detected. For example, when it is desired to evaluate the etching of the metal layer 142, the second switching occurs. After that, data collection is started and data up to the time before the third switching occurs may be handled as valid data.

  FIG. 17 is an explanatory diagram showing an example of the state of the matching box of the plasma processing apparatus when an abnormality has occurred, corresponding to the flowchart of FIG. As shown in FIG. 17, for example, in the etching process of the metal layer 142, when an abnormality occurs in the plasma generation state, the position voltage V of the variable capacitors C1 and C2 varies. Although this fluctuation waveform can take various shapes depending on the abnormal situation, it is needless to say that a large-scale abnormal discharge can be obtained by evaluating the difference value Δ and the standard deviation σ as in the processing flow of FIG. It is considered that most abnormalities can be detected, including abnormal discharges on a scale and abnormalities that affect device processing accuracy. If a large-scale abnormal discharge occurs, for example, a device state as shown in FIG. 18 is obtained.

  FIG. 18 is a device cross-sectional view showing a configuration example of a part of the semiconductor device when a large-scale abnormal discharge occurs in the processing flow of FIG. When a large-scale abnormal discharge occurs, for example, as shown in FIG. 18, the resist 144 or the like is removed to cause over-etching of the metal layer 142 portion, or conversely, an etching residue occurs or foreign matter is generated. As a result of frequent occurrences, various problems that lead to product defects such as disconnection or short-circuiting of wiring occur. When the processing flow of FIG. 12 is used, the semiconductor wafer W in which such a problem has occurred can be reliably detected, and subsequent inspection of the apparatus or the like can surely prevent the formation of defective products thereafter.

  As described above, by using the method for manufacturing a semiconductor device according to the fourth embodiment, an etching process with various effects as described in the first and second embodiments can be realized. In addition, by strictly managing the standard values of the difference value Δ and the standard deviation σ, it is possible to sufficiently manage the process accuracy, for example, for an etching process that requires high-precision wiring processing. Become. In the processing flow of FIG. 12, the difference value Δ and the standard deviation σ are determined at the end of the processing of the semiconductor wafer. However, the determination is performed sequentially during the processing of the semiconductor wafer, and an abnormality occurs. It is also possible to perform error processing immediately.

(Embodiment 5)
In the fifth embodiment, assuming that the plasma processing apparatus as described in the first and second embodiments is, for example, a sputter etching apparatus, processing contents when a sputter etching process is performed using this apparatus will be described.

  FIG. 19 is a flowchart showing an example of the processing contents in the method of manufacturing a semiconductor device according to the fifth embodiment of the present invention. FIG. 20 is an explanatory view showing a state example of the matching box of the plasma processing apparatus corresponding to the flowchart of FIG. Each of FIGS. 21 and 22 is a device cross-sectional view illustrating a configuration example of a part of a semiconductor device formed with the flowchart of FIG. 19. Hereinafter, the description will be made based on the plasma processing apparatus of FIG. 4, but the same applies to the case of FIG. 1.

In the processing flow of FIG. 19, in the plasma processing unit 40 of FIG. 4, first, the semiconductor wafer W is loaded into the chamber 41 and mounted on the electrostatic chuck 42c. Then, the semiconductor wafer W is attracted onto the electrostatic chuck 42c by applying a voltage from the DC voltage source 49 (S1901). Here, it is assumed that a part of the configuration of the semiconductor wafer W in this initial state is as shown in FIG. In the semiconductor wafer (semiconductor device) W shown in FIG. 21, for example, an insulating layer 210 such as SiO ₂ is formed on an upper layer portion of a semiconductor substrate (not shown).

Next, Ar gas is introduced from the gas inlet 41a in a state where the inside of the chamber 41 is sufficiently evacuated (S1902). Thereafter, the output of the high frequency power supply 43 is turned on in a state where the gas inflow is stable. Then, plasma is generated between the upper electrode 42a and the lower electrode 42b, and impedance matching is automatically performed by the matching box 44 (S1904). That is, the values (position voltages) of the variable capacitors C1 and C2 in the matching box 44 change and are automatically adjusted to an optimum position where impedance matching can be achieved (S1905). When the impedance matching is performed, the plasma becomes a stable discharge region, and Ar ⁺ ions collide with the surface of the insulating layer 210 as shown in FIG. 22, whereby the surface treatment of the insulating layer 210 is performed. When the surface treatment is performed for a certain time, the output of the high frequency power supply 43 is turned off (S1907).

  In such a series of processes, the position voltage V of the variable capacitors C1 and C2 in the matching box 14 varies as shown in FIG. 20, for example. In FIG. 20, the horizontal axis indicates time, and the vertical axis indicates the position voltage V of the variable capacitors C1 and C2. When the output of the high frequency power supply 43 is turned on, the position voltages of the variable capacitors C1 and C2 start to fluctuate from an unspecified position voltage in accordance with the processing of S1904 and S1905 in FIG. When the impedance matching is achieved, the position voltage fluctuation stops. After passing through such a fluctuation section, it becomes a stable discharge region, and in this region, the plasma generation state is stable, and the position voltages of the variable capacitors C1 and C2 hardly change as shown in FIG.

  On the other hand, in parallel with the processing of the plasma processing unit 40 as described above, the abnormality monitoring unit 48 performs processing as shown on the right side of FIG. Since the processing of S1911 to S1929 here is the same as the processing of S511 to S529 of FIG. 5, a detailed description thereof will be omitted, and a brief description will be given. First, in S1911 to S1915, when the output of the high frequency power supply 43 is turned on, sampling of the position voltages of the variable capacitors C1 and C2 is started, the position voltage accompanying the initial matching is stabilized, and the stable discharge region is entered. By the way, initial values V0 (C1) and V0 (C2) of the position voltage are determined.

  Next, in S1918 and S1919, the sampling collection of the position voltage is continued, and this collection is stopped in response to the output of the high frequency power supply 43 being turned off. Thereafter, in S1920 to S1929, the standard deviation σ with respect to the collected position voltage and the difference value Δ of the position voltage between the sampling points are calculated, and these are compared with a preset standard value to determine normality / abnormality. I do. If it is normal, the next semiconductor wafer is carried in, and if it is abnormal, error processing such as sending an alarm or stopping the apparatus is performed.

  FIG. 23 is an explanatory diagram showing an example of the state of the matching box of the plasma processing apparatus when an abnormality has occurred, corresponding to the flowchart of FIG. As shown in FIG. 23, when an abnormality occurs in the plasma generation state in the stable discharge region, the impedance matching state is disturbed, and the position voltage V of the variable capacitors C1 and C2 varies. Although this fluctuation waveform can take various shapes depending on the abnormal situation, it is obvious that a large-scale abnormal discharge can be obtained by evaluating the difference value Δ and the standard deviation σ as in the processing flow of FIG. It is considered that most abnormalities can be detected, including abnormal discharges on a scale and abnormalities that affect device processing accuracy.

  If a large-scale abnormal discharge occurs, for example, a foreign substance adheres to the surface of the insulating layer 210, so that the subsequent steps (for example, formation of a wiring layer on the insulating film) are normally performed. Even so, there is a high possibility that the semiconductor wafer will eventually become a defective product. Further, in the sputter etching process for the next semiconductor wafer, there is a possibility that a defect is similarly formed. If the processing flow of FIG. 19 is used, the semiconductor wafer W in which such a problem has occurred can be reliably detected, and the subsequent inspection of the apparatus and the like can reliably prevent the formation of defective products thereafter.

  As described above, by using the method of manufacturing a semiconductor device according to the fifth embodiment, the sputter etching process with various effects as described in the first and second embodiments can be realized. In the processing flow of FIG. 19, the difference value Δ and the standard deviation σ are determined at the end of the processing of the semiconductor wafer. However, the determination is performed sequentially during the processing of the semiconductor wafer, and immediately when an abnormality occurs. It is also possible to perform error processing.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  A semiconductor device manufacturing method and a plasma processing apparatus according to the present invention are applicable to various plasma processing apparatuses represented by plasma CVD apparatuses, RIE apparatuses, sputter etching apparatuses, and the like, and semiconductor device manufacturing processes involving monitoring of such apparatuses. And widely applicable.

It is the schematic which shows an example of the structure in the plasma processing apparatus by Embodiment 1 of this invention. FIG. 2 is a schematic diagram illustrating an example of processing contents of an abnormality monitoring unit in the plasma processing apparatus of FIG. 1. In the plasma processing apparatus of FIG. 1, it is a graph which shows an example of the monitoring result of the (sigma) monitoring part, (a) shows an example at the time of normal operation, (b) shows an example at the time of abnormal operation. It is the schematic which shows an example of the structure in the plasma processing apparatus by Embodiment 2 of this invention. In the manufacturing method of the semiconductor device by Embodiment 3 of this invention, it is a flowchart which shows an example of the processing content. FIG. 6 is an explanatory diagram illustrating a state example of a matching box of the plasma processing apparatus corresponding to the flowchart of FIG. 5. FIG. 6 is a device cross-sectional view illustrating a configuration example of a part of a semiconductor device formed with the flowchart of FIG. 5. FIG. 6 is a device cross-sectional view illustrating a configuration example of a part of a semiconductor device formed with the flowchart of FIG. 5. FIG. 6 is a device cross-sectional view illustrating a configuration example of a part of a semiconductor device formed with the flowchart of FIG. 5. FIG. 6 is an explanatory diagram showing an example of the state of the matching box of the plasma processing apparatus when an abnormality has occurred, corresponding to the flowchart of FIG. 5. FIG. 6 is a device cross-sectional view illustrating a configuration example of a part of a semiconductor device when a large-scale abnormal discharge occurs in the processing flow of FIG. 5. In the manufacturing method of the semiconductor device by Embodiment 4 of this invention, it is a flowchart which shows an example of the processing content. It is explanatory drawing which shows the state example of the matching box of a plasma processing apparatus corresponding to the flowchart of FIG. FIG. 13 is a device cross-sectional view illustrating a partial configuration example of a semiconductor device formed with the flowchart of FIG. 12. FIG. 13 is a device cross-sectional view illustrating a partial configuration example of a semiconductor device formed with the flowchart of FIG. 12. FIG. 13 is a device cross-sectional view illustrating a partial configuration example of a semiconductor device formed with the flowchart of FIG. 12. FIG. 13 is an explanatory diagram illustrating an example of a state of a matching box of the plasma processing apparatus when an abnormality occurs, corresponding to the flowchart of FIG. 12. FIG. 13 is a device cross-sectional view illustrating a partial configuration example of a semiconductor device when a large-scale abnormal discharge occurs in the processing flow of FIG. 12. In the manufacturing method of the semiconductor device by Embodiment 5 of this invention, it is a flowchart which shows an example of the processing content. It is explanatory drawing which shows the state example of the matching box of a plasma processing apparatus corresponding to the flowchart of FIG. FIG. 20 is a device cross-sectional view illustrating a partial configuration example of a semiconductor device formed with the flowchart of FIG. 19. FIG. 20 is a device cross-sectional view illustrating a partial configuration example of a semiconductor device formed with the flowchart of FIG. 19. FIG. 20 is an explanatory diagram illustrating a state example of a matching box of the plasma processing apparatus when an abnormality occurs, corresponding to the flowchart of FIG. 19.

Explanation of symbols

10, 40 Plasma processing unit 11, 41 Chamber 11a, 41a Gas inlet 11b, 41b Exhaust port 12a, 42a Upper electrode 12b, 42b Lower electrode 13, 43 High frequency power supply 14, 44 Matching box 15a, 45a C1 position monitor unit 15b, 45b C2 position monitoring unit 16, 46 Pr detection unit 17, 47 Error processing unit 18, 48 Abnormality monitoring unit 18a, 48a Sequence control unit 18b, 48b Δ monitoring unit 18c, 48c σ monitoring unit 42c Electrostatic chuck 49 DC voltage source 70 , 140, 210 Insulating layer 71, 141 Barrier layer 72, 142 Metal layer 73, 143 Antireflection layer 74 Interlayer insulating layer 75 Foreign material 144 Resist C1, C2 Variable capacitance L1 Inductor W Semiconductor wafer

Claims (16)

A semiconductor device manufacturing method including the following steps:
(A) a wafer processing container, a high-frequency power source, and a matching box capable of variably adjusting electrical parameters for impedance matching between the output of the high-frequency power source and plasma generated in the wafer processing container. Preparing a plasma processing apparatus,
(B) carrying a semiconductor device into the wafer processing container;
(C) generating plasma using the output of the high-frequency power source in the wafer processing container;
(D) detecting the state of the generated plasma, and the matching box automatically adjusting the electrical parameters according to the detection result;
(E) a step of processing the semiconductor device using the generated plasma;
(F) obtaining the value of the electrical parameter adjusted by the matching box in time series;
(G) evaluating the state of the generated plasma using the value of the electrical parameter acquired in time series,
Here, in the step (g), an evaluation start point for starting the evaluation of the generated plasma state and an evaluation end point for ending the evaluation of the generated plasma state are determined, and the step (f) The state of the generated plasma is evaluated by using the value of the electrical parameter acquired between the evaluation start time and the evaluation end time from among the values of the electrical parameter acquired in time series by the evaluation target. To do. In the manufacturing method of the semiconductor device according to claim 1,
The plasma processing apparatus includes an electrostatic chuck for fixing the semiconductor device in the wafer processing container. In the manufacturing method of the semiconductor device according to claim 1,
The step (g) includes the following steps:
(G1) calculating a time-series difference value for the value of the electrical parameter to be evaluated, and comparing and determining a preset standard value and the calculated difference value;
(G2) A step of calculating a standard deviation of the value of the electrical parameter to be evaluated, and comparing and judging a preset standard value and the calculated standard deviation. In the manufacturing method of the semiconductor device according to claim 1,
The evaluation start time is after the plasma generation is started in the step (c), and after the initial automatic adjustment of the electrical parameters accompanying the start of the plasma generation is completed in the step (d). Determined in the time zone. In the manufacturing method of the semiconductor device according to claim 4,
Whether or not the initial automatic adjustment of the electrical parameters accompanying the start of the generation of the plasma is completed is a time-series difference with respect to the electrical parameters acquired in time-series by the step (f). This is determined by calculating the value. In the manufacturing method of the semiconductor device according to claim 4,
The evaluation start time is predicted in advance as a time point after the initial automatic adjustment of the electrical parameters accompanying the start of the generation of the plasma, and the predicted time point is set in a timer in advance. Determined by A semiconductor device manufacturing method including the following steps:
(A) a wafer processing container, a high-frequency power source, and a matching box capable of variably adjusting electrical parameters for impedance matching between the output of the high-frequency power source and plasma generated in the wafer processing container. Preparing a plasma processing apparatus,
(B) carrying a semiconductor device into the wafer processing container;
(C) generating plasma using the output of the high-frequency power source in the wafer processing container;
(D) detecting the state of the generated plasma, and the matching box automatically adjusting the electrical parameters according to the detection result;
(E) a step of processing the semiconductor device using the generated plasma;
(F) obtaining the value of the electrical parameter adjusted by the matching box in time series;
(G) evaluating the state of the generated plasma using the value of the electrical parameter acquired in time series,
Here, the step (g) includes the following steps:
(G1) a step of determining an evaluation start point at which the evaluation of the generated plasma state is started and an evaluation end point at which the evaluation of the generated plasma state is ended;
(G2) The value of the electrical parameter acquired by the step (f) between the evaluation start time and the evaluation end time as an evaluation target, and the time series of the value of the electrical parameter to be evaluated Calculating a difference value, and comparing and determining a preset standard value and the calculated difference value;
(G3) A step of calculating a standard deviation of the value of the electrical parameter to be evaluated, and comparing and judging a preset standard value and the calculated standard deviation. The method of manufacturing a semiconductor device according to claim 7.
The value of the electrical parameter includes a value indicating the adjustment position of the variable capacitor for coarse adjustment and a value indicating the adjustment position of the variable capacitor for fine adjustment. The method of manufacturing a semiconductor device according to claim 7.
In the step (f), the electrical parameter for each sampling point is acquired based on a preset sampling period,
The time-series difference value calculated in the step (g2) is a difference value between the values of the electrical parameters acquired at two consecutive sampling points. The method of manufacturing a semiconductor device according to claim 7.
In any one of the steps (g2) and (g3), the state of the generated plasma is determined to be abnormal when the respective standard values are not satisfied. The method of manufacturing a semiconductor device according to claim 7.
The step (e) is a film forming step. The method of manufacturing a semiconductor device according to claim 7.
The step (e) is an etching step. A high frequency power supply,
A wafer processing container that fixes a semiconductor wafer inside, generates plasma inside using the output of the high-frequency power source, and processes the semiconductor wafer by the plasma;
An output of the high-frequency power source is provided between the wafer processing container and the high-frequency power source and includes an electrically adjustable parameter and automatically adjusts the electrical parameter according to the plasma generation state. A matching box for impedance matching between the plasmas;
A function of acquiring the value of the electrical parameter adjusted in the matching box in a time series based on a sampling period;
A function of setting an evaluation start time and an evaluation end time, and evaluating the generation state of the plasma using the value of the electrical parameter acquired in a time zone between the evaluation start time and the evaluation end time as an evaluation target Plasma processing equipment. The plasma processing apparatus according to claim 13, wherein
The wafer processing container fixes the semiconductor wafer using an electrostatic chuck. The plasma processing apparatus according to claim 13, wherein
The function of evaluating the plasma generation state is as follows:
The difference value between the electrical parameter values acquired at two consecutive sampling points is calculated for the electrical parameter value to be evaluated, and the difference between the standard value set in advance and the difference value are compared. Function to
A function of calculating a standard deviation of the value of the electrical parameter to be evaluated, and comparing the standard deviation with a preset standard value;
A function of determining normality / abnormality of the plasma generation state according to a comparison result between the difference value and the standard deviation. The plasma processing apparatus according to claim 15, wherein
The value of the electrical parameter includes a value indicating the adjustment position of the variable capacitor for coarse adjustment and a value indicating the adjustment position of the variable capacitor for fine adjustment.

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