JP2007212700A - Analog electronic circuit for active noise canceling system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the system size and cost of an active noise canceling system of a linear duct by making an adaptive filter section fast and simple. <P>SOLUTION: A circuit is an adaptive filter comprising an analog electronic circuit, has constitution of a neural network, and feeds an error signal back to hierarchical neural network constitution to achieve adaptive filter processing. The circuit uses a wide-range Gilbert multiplier for multiplication in the neural network and substitutes nonlinearity of the wide-range Gilbert multiplier for nonlinear operation of a neuron part. Further, an integrator composed of an operational amplifier is used for a load variation part to vary a load. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

    The present invention relates to an analog electronic circuit for an active noise canceling system which is one of noise elimination methods.

  Conventionally, as disclosed in Patent Documents 1 and 2 or Non-Patent Document 1, an active noise canceling system for one-dimensional duct noise constitutes an adaptive filter by digital processing using a digital electronic circuit and outputs an antiphase sound. I was in control. A schematic diagram of the prior art is shown in FIG. In FIG. 14, noise flows from the left to the right inside the one-dimensional duct 15.

  In FIG. 14, in order to perform active noise canceling, a noise signal is captured by the microphone 16, the noise input is digitally processed, and a sound having an opposite phase is output by the speaker 18.

  Here, when the noise that cannot be completely canceled is left, the remaining noise signal (error signal) is captured by the microphone 17 and fed back to change the circuit operation so that the noise canceling is improved. What operates in this way is called an adaptive filter.

    However, in order to perform the operation of the adaptive filter by digital processing as shown in FIG. 14, the noise input taken in by the microphone 16 is A / D converted by an analog / digital (A / D) converter 19 and then a digital signal processing circuit. It is necessary to input to the (DSP) 22 and control the output to be converted to D / A by the digital / analog (D / A) converter 20 and output to the speaker 18.

In addition, since the DSP 22 required for digital processing is required to have high-speed computing capability, it is necessary to use a high-performance circuit.
Japanese Patent Laid-Open No. 2002-60146 “Active Noise Controller” JP 2001-355429 A “Active Silencer” “Active Silence System” 1996 TOA ANC Technical Document-05, TOA Corporation Silence Division 1996

    In the conventional circuit described above, noise travels in the one-dimensional duct 15 for the time required for A / D conversion and D / A conversion, and therefore, a certain distance is required between the microphone 16 and the speaker 18 in FIG. There was a problem that the system became large.

    Further, as shown in FIG. 14, an A / D converter 19, an A / D converter 21, a D / A converter 20, and a DSP 22 having a calculation capability according to the conversion speed are necessary, so that the cost is reduced. There was also the problem of becoming higher.

  The present invention has been made in view of the above-described conventional situation, and avoids the delay of a signal processing circuit that leads to an increase in system size and the complexity of a circuit configuration that leads to an increase in cost in an active noise canceling system. It is to provide a circuit to perform.

  In the present invention, in order to solve the problems of the prior art, an A / D converter, a D / A converter, and an analog electronic circuit which does not require a DSP, which have caused the problem, have an active noise canceling function. A filter was produced. Hereinafter, this adaptive filter is referred to as an analog electronic circuit adaptive filter.

  The analog electronic circuit adaptive filter constitutes a neural network circuit.

  The neural network circuit in the analog electric circuit adaptive filter has a hierarchical neural network structure, and is characterized by changing a load in the neural network by feeding back an error signal.

  The analog electronic circuit adaptive filter is characterized in that a wide range Gilbert multiplier is used in a portion for performing a multiplication operation required in the neural network circuit.

  The analog electronic circuit adaptive filter does not use a sigmoid function circuit or the like in the operation of the neuron part in the neural network circuit, but substitutes the operation of the neuron part by the non-linearity by the wide range Gilbert multiplier used for weight multiplication. Features.

  The analog electronic circuit adaptive filter is characterized in that the load change amount is cumulatively added by an integrator using an operational amplifier in order to change the load.

  A schematic diagram of an active noise canceling system using a circuit according to the present invention is shown in FIG.

  An analog electronic circuit adaptive filter 5 in FIG. 1 is a circuit according to the present invention.

  The analog electronic circuit adaptive filter 5 according to the present invention filters the noise input flowing through the one-dimensional duct 1 taken in by the microphone 2 to transmit the noise input to the speaker 4 in the opposite phase.

  Here, the analog electronic circuit adaptive filter 5 has a structure of a hierarchical neural network.

  The speaker 4 outputs a signal having a phase opposite to that of the noise output from the analog electronic circuit adaptive filter 5 and removes noise in the duct. However, it is difficult to completely remove noise, and residual sound flows in the one-dimensional duct 1.

  The residual sound is captured by the microphone 3 and the signal is fed back to the analog electronic circuit adaptive filter 5 as an error signal. The analog electronic circuit adaptive filter 5 changes the characteristic of the filter by changing the value (load) used for the calculation in the neural network based on the error signal. At this time, the load is changed so that the error signal becomes small.

  In this way, the analog electronic circuit adaptive filter 5 outputs a sound having a phase opposite to that of the noise by constantly changing the characteristics of the filter, thereby achieving noise removal.

  The simulation results of the noise removal effect according to the present invention are shown in FIGS. Here, a wave obtained by synthesizing a sine wave of 100 kHz and a sine wave of 250 kHz was input to the analog electronic circuit adaptive filter as virtual noise. Noise is shown in the figure as an input waveform. An antiphase signal output from the analog electronic circuit adaptive filter is shown as an output waveform. The added waveform of the input waveform and the output waveform is shown as the waveform after mute, and it can be seen that the amplitude is smaller than that of the input waveform.

    As a result, it was confirmed that the circuit according to the present invention functions as a circuit for an active noise canceling system.

    Embodiments 1 and 2 embodying the invention will be described below with reference to the drawings.

  FIG. 2 shows a conceptual diagram of a three-layer hierarchical neural network in the analog electronic circuit adaptive filter according to the present invention in the first embodiment.

  A neural network is composed of elements called neurons. In the neural network according to the present invention, neurons are arranged in a three-layer structure including an input layer, an intermediate layer, and an output layer.

  As shown in FIG. 2, the neural network in the first embodiment has one input layer neuron (input layer neuron 6), two intermediate layer neurons (intermediate layer neurons 7, 8), and one output layer neuron (output layer neuron). 9) The hierarchical neural network.

  The noise input passes through the input layer neurons 6 and the signals are divided by the number of intermediate layer neurons. In the case of Example 1, it is divided into two.

  One of the divided signals is multiplied by the load Wm1 before reaching the intermediate layer neuron 7. The other signal is multiplied by the load Wm2 before reaching the intermediate layer neuron 8.

  The signal reaching the intermediate layer neuron 7 passes through the intermediate layer neuron 7 and is then multiplied by the load Wo1. The signal reaching the intermediate layer neuron 8 is multiplied by the load Wo2 after passing through the intermediate layer neuron 8.

  The signal multiplied by the load Wo1 and the signal multiplied by the load Wo2 are added and then passed through the output layer neuron 9 to become an output. The output is then amplified and transmitted to the speaker 4.

  The loads Wm1, Wm2, Wo1, Wo2 are appropriately changed to values calculated from the error signal. An adaptive process is performed by changing the load, and the three-layer hierarchical neural network functions as an adaptive filter.

  Hereinafter, the operation will be described using a specific circuit diagram.

  FIG. 3 shows a wide range Gilbert multiplier used in the present invention. In the hierarchical neural network of the present invention, multiplication is frequently used, and this wide range Gilbert multiplier is used for all the multiplications.

Wide Range Gilbert multiplier of Figure 3 is the voltage input to the voltage and V ₂ are inputted to the difference (V 3 _{-V 4),} and V ₁ of the voltage input to the voltage and V ₄ which are input to the V ₃ Is multiplied by the difference (V ₁ −V ₂ ). That is, (V ₃ −V ₄ ) × (V ₁ −V ₂ ) is output to V _out .

FIG. 4 shows the characteristics of V _out with respect to the input voltages (V ₁ −V ₂ ) and (V ₃ −V ₄ ) of the wide range Gilbert multiplier. In (V ₃ −V ₄ ), a DC voltage of 1.65 V is applied so as to take a reference at the center of the power supply voltage of 3.3 V. It can be seen that multiplication is achieved when (V ₃ −V ₄ ) is | 0.2 V | or less.

In FIG. 4, when (V ₃ −V ₄ ) is equal to or greater than | 0.2V |, nonlinear characteristics appear instead of linear multiplication. In the present invention, this non-linearity achieves a non-linear operation necessary for the operation of the neural network.

  The wide range Gilbert multiplier in this specification will be represented by symbols as shown in FIG.

  FIG. 6 is a block diagram of a three-layer hierarchical neural network circuit according to the first embodiment. WRM in the figure represents a wide range Gilbert multiplier.

  WRM1 and WRM2 execute weight multiplication in signal transmission from the input layer neuron 6 to the intermediate layer neuron 7 and the intermediate layer neuron 8, and non-linear operations in the intermediate layer neuron 7 and the intermediate layer neuron 8. Here, the reference input that is input together with the noise input is obtained by extracting a DC component added to the noise input signal. By using the reference input and the noise input, it is possible to input only the AC component, which is a noise signal, to the multiplier.

  Wm1 and Wm2 indicate the above-described loads, and Wm-gnd indicates a reference voltage with respect to the loads Wm1 and Wm2. This Wm-gnd is also a DC component of the load, and by using Wm1, Wm2, and Wm-gnd, only the AC component that is the load changing portion can be input to the multiplier.

  Signals H1 and H2 multiplied and output by WRM1 and WRM2 are input to WRM4 and WRM5, respectively.

WRM3 is for creating a reference voltage H-gnd for signals H1 and H2 output from WRM1 and WRM2. Noise input and Wm-gnd are input to WRM3. Compensates WRM1, WRM2 is the error of the If not accurately calculated and _{(V 3 -V 4) × (} V 1 -V 2) In this WRM3 The H-gnd.

  WRM 4 and WRM 5 execute weight multiplication in signal transmission from the intermediate layer neuron 7, intermediate layer neuron 8 to output layer neuron 9, and non-linear operation in the output layer neuron 9.

    The output from WRM1 and the output from WRM3 are input to WRM4. Further, the load Wo1 and the reference voltage Wo-gnd with respect to the load Wo1 are input, and multiplication is performed.

  The output from WRM2 and the output from WRM3 are input to WRM5. Further, the load Wo2 and the reference voltage Wo-gnd with respect to the load Wo2 are input, and multiplication is performed.

  The outputs of WRM4 and WRM5 are added and become the final output.

  The loads Wm1, Wm2, Wo1, and Wo2 are generated by an arithmetic circuit that uses an error signal as an input.

  In the first embodiment, the loads Wm1 and Wm2 are fixed, and only the loads Wo1 and Wo2 are changed. FIG. 7 shows a block diagram of a circuit for changing the loads Wo1 and Wo2.

  Note that Integrator 1 shown in FIG. 7 indicates an integrator using the operational amplifier 10 shown in FIG. The resistor 11 in FIG. 8 is a resistor of about 100 kΩ, and the capacitor 12 is a capacitor of about 10 pF. This integrator creates a load W by accumulating the load change amount ΔW.

  In FIG. 7, first, an output, a reference input, and two reference voltages are input to the WRM 6. Here, the two reference voltages are DC voltages, and there is a certain potential difference between the reference voltages. As a result, the output is multiplied by a constant multiple.

  The output of WRM6 is input to WRM7. The reference voltage is a DC voltage having a DC component of the output of the WRM 6. By inputting this, only the AC component of the output of the WRM 6 can be calculated. In addition, the outputs H1 and H2 from the intermediate layer neuron 7 and the intermediate layer neuron 8 in FIG. The output from these intermediate layer neurons is represented as Hj, where j is a numerical value obtained by sequentially numbering the intermediate layer neurons. A reference voltage H-gnd corresponding to the DC component of Hj is also input, and only the AC component of Hj is calculated.

  The output of WRM7 is input to WRM8. Further, a reference voltage that is a DC component of the output of WRM 7 is also input, and an AC component of the output of WRM 7 is calculated. The error signal is also input together with the reference voltage and multiplied by the AC component.

  The output of the WRM 8 is the change amount ΔWoj of the load Woj and is input to the integrator 1. Integrator 1 cumulatively adds them to create Woj and inputs it to the circuit of FIG.

  The circuit shown in FIG. 7 is produced by the number of Wo. That is, in this case, two circuits are required corresponding to Wo1 and Wo2 necessary for the circuit configuration of FIG.

  The adaptive filter processing can be realized by combining the calculation from the noise input to the output by the circuit of FIG. 6 and the calculation from the error signal to the load Woj by the circuit of FIG. FIG. 9 shows the simulation result of the analog electronic circuit adaptive filter by the three-layer hierarchical neural network manufactured using these circuits.

  FIG. 10 is a conceptual diagram of a two-layer hierarchical neural network in the analog electronic circuit adaptive filter according to the present invention in the second embodiment.

  The neural network according to the second embodiment has a configuration in which there is one input layer neuron 13 and one output layer neuron 14.

  The noise input transmitted from the microphone 3 first passes through the input layer neuron 13 and is multiplied by the load Wok. Here, k of the load Wok is a numerical value corresponding to the input layer neuron, and is only 1 in this case. Thereafter, the signal is output through the output layer neuron 14. The output is then amplified and transmitted to the speaker 4 to be silenced.

  Here, the load Wok is appropriately changed based on the error signal that cannot be completely silenced, and is adjusted so that the output always has an appropriate silenced waveform. This works as a two-layer hierarchical neural network adaptive filter.

  Hereinafter, description will be made with reference to a circuit diagram.

  FIG. 11 is a block diagram of a two-layer hierarchical neural network circuit according to the second embodiment.

  In this two-layer hierarchical neural network, the wide-range Gilbert multiplier shown in FIG. 3 is used for all multiplications, and the nonlinear calculation of the neural network is achieved by using the nonlinearity of the characteristics.

  The noise input is input to the WRM 9 and multiplied by a load Wo1, which is a load between the input layer neuron 13 and the output layer neuron 14. At this time, the reference voltage 24 is also input to the WRM 9, and only the AC components of both are multiplied. At this time, the non-linear operation is achieved by the non-linearity of the wide-range Gilbert multiplier. The multiplied result is transmitted to the speaker 4 as an output.

  FIG. 12 is a block diagram of a circuit for changing the load Wok. This circuit includes a WRM 10 and an integrator Integrator2. Integrator 2 is the same as that shown in FIG.

  The WRM 10 receives a noise input and an error signal and multiplies them. At this time, the reference voltage is also input to the WRM 10, and only the AC components of both are multiplied. The multiplied result is the load change amount ΔWok and is input to Integrator 2.

  Integrator 2 cumulatively adds the load change amount ΔWok and outputs the load Wok. The load Wok thus generated is input to the circuit of FIG.

  The adaptive filter processing can be realized by combining the calculation from the noise input to the output by the circuit of FIG. 11 and the calculation from the error signal to the load Wok by the circuit of FIG. FIG. 13 shows the simulation result of the analog electronic circuit adaptive filter by the two-layer hierarchical neural network manufactured using these circuits.

Schematic diagram of an active noise canceling system using a circuit according to the present invention. Conceptual diagram of a three-layer hierarchical neural network in the analog electronic circuit adaptive filter of the first embodiment Wide-range Gilbert multiplier used in the present invention Input / output characteristics of wide-range Gilbert multiplier Wide range Gilbert multiplier symbol in this specification 1 is a block diagram of a three-layer hierarchical neural network circuit according to the first embodiment. Block diagram of a circuit for changing the loads Wo1 and Wo2 of the first embodiment An integrator using an operational amplifier used in the present invention. Simulation results of an analog electronic circuit adaptive filter by the three-layer hierarchical neural network of the first embodiment Conceptual diagram of a two-layer hierarchical neural network in the analog electronic circuit adaptive filter of the second embodiment Block diagram of a two-layer hierarchical neural network circuit according to the second embodiment Block diagram of a circuit for changing the load Wok of the second embodiment Simulation results of an analog electronic circuit adaptive filter by the two-layer hierarchical neural network of the second embodiment Schematic diagram of a conventional active noise canceling system

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 15 ... One-dimensional duct 2, 3, 16, 17 ... Microphone 4, 18 ... Speaker 5 ... Analog electronic circuit adaptive filter 6, 13 ... Input layer neuron 7, 8 ... Intermediate layer neuron 9, 14 ... Output layer neuron 10 ... Operational amplifier 11 ... Resistance 12 ... Capacitance 19, 21 ... A / D converter 20 ... D / A converter 22 ... Digital signal processing circuit (DSP)
M ₁ , M ₂ , M ₃ , M ₄ , M ₅ , M ₆ , M ₇ , M ₈ , M ₉ , M ₁₀ ... pMOS transistors M ₁₁ , M ₁₂ , M ₁₃ , M ₁₄ , M ₁₅ , M ₁₆ , M ₁₇ ... nMOS transistor

Claims (6)

    An electronic circuit designed for active noise cancellation that eliminates noise by generating anti-phase sound of noise, and an adaptive filter is realized by analog electronic circuits.   The circuit of claim 1, wherein a circuit configuration of a neural network structure is used to realize the adaptive filter.   2. The circuit according to claim 1, which has a hierarchical neural network structure, and performs adaptive processing by changing a load in the neural network by feeding back an error signal.   2. The circuit according to claim 1, wherein a wide-range Gilbert multiplier is used in the multiplication operation in the neural network.   2. The circuit according to claim 1, wherein in the calculation of the neuron portion in the neural network, the operation of the neuron portion is substituted by non-linearity by the wide range Gilbert multiplier used for weight multiplication without using a circuit such as a sigmoid function circuit.   2. The circuit according to claim 1, wherein the load change amount is cumulatively added by an integrator using an operational amplifier in order to change the load.

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