JP2007201853A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To optimize body bias control to a data holding flip-flop using an SOI type MOS transistor according to its operating state. <P>SOLUTION: Each of a plurality of circuits consisting of the SOI type MOS transistor has a flip-flop consisting of a master latch part (MLAT) made into selective power shutdown by a power switch (10) and a slave latch part (SLATdr) made into non-object for the selective power shutdown. The slave latch part is body bias controlled so that threshold voltage of the MOS transistor may become small in a power non-shutdown state and body bias controlled so that the threshold voltage of the MOS transistor may become large in a power shutdown state. Thus, speeding up of the flip-flop is assured in the power non-shutdown state and subthreshold leak current at the slave latch part is reduced in an operation power source shutdown state of the master latch part. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit using an SOI (Silicon On Insulator) type field effect transistor (also simply referred to as a MOS transistor in this specification), and more particularly, a body bias of a flip-flop capable of shutting off an operation power supply. It relates to control technology.

  Patent Document 1 discloses a flip-flop in which an operation power supply of a master latch unit is cut off in a low power consumption mode, and only a slave latch unit increases the voltage level of the operation power supply to hold an information signal while reducing a leakage current. There is a description. Patent Document 2 describes a non-volatile master-slave flip-flop that includes a master-slave latch unit that can be powered off and a save latch that retains stored information of the slave latch unit and is not powered off when the power is turned off.

  A semiconductor integrated circuit including a flip-flop and a latch can be configured by either a bulk type MOS integrated circuit or an SOI type MOS integrated circuit. In a bulk type MOS integrated circuit, an active region is formed on a substrate or a well region to form a MOS transistor. However, an SOI type MOS integrated circuit does not use a well region, and a large number of active regions are formed on an insulating thin film on a substrate. A MOS transistor is formed in each active region. Therefore, the SOI type MOS integrated circuit is fundamentally different from the bulk type MOS integrated circuit in terms of element isolation, and junction capacitance and junction leakage with the substrate are small. In this respect, the SOI type MOS integrated circuit is superior to the bulk type MOS integrated circuit in terms of low voltage operation, low power consumption, and high speed operation. From the viewpoint of low power consumption and high-speed operation, Patent Document 3 discloses that the body of a MOS transistor that constitutes a logic circuit is floated to set a low threshold voltage, and the MOS transistor that constitutes the logic circuit is connected to a power supply and a ground. A configuration in which the power supply switch to be body biased to increase the threshold voltage is exemplified. A low threshold voltage MOS transistor can operate the logic circuit at high speed, and a high threshold voltage power switch can reduce power consumption during standby.

JP 2000-244287 A JP 2005-167184 A JP-A-8-228145

  The present inventor uses a SOI-type MOS transistor to form a flip-flop (data retention type flip-flop) that maintains stored information by maintaining power supply to only some circuits when the operating power is shut off. I examined that. As described above, when an SOI type MOS integrated circuit is used, unlike a bulk type MOS integrated circuit, isolation is naturally performed for each element without performing well isolation according to differences in transistor conductivity type and power supply voltage. This is excellent in reducing the chip occupation area. Further, if attention is paid to the element isolation of the SOI type MOS transistor, it is possible to subdivide the data holding type flip-flop and perform different body bias control. In that case, paying attention to the difference in function between the power shut-off unit and the non-shut-off unit that constitutes the data retention type flip-flop, low leakage at the time of power shut-off, faster operation at the time of power non-shutoff, The present inventor has found the usefulness of performing body bias control in consideration of an operation margin and the like in data saving and data restoration with respect to the blocking unit.

  An object of the present invention is to optimize body bias control for a circuit part that can be turned off and a circuit part that cannot be turned off, constituting a data holding type flip-flop using an SOI type MOS transistor, according to its operating state. An object of the present invention is to provide a semiconductor integrated circuit capable of achieving the above.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

[1] << Data retention type FF in which the slave latch part is not powered off >>
A semiconductor integrated circuit according to the present invention includes a source (SOC), a drain (DRN), a body (BDY), a gate insulating film (GOX) on the body, and a gate on the gate insulating film on an insulating thin film of a substrate. (GAT) and a plurality of circuits comprising MOS transistors (MNtn, MPtn, MNtk, MPtk), and a control circuit (5) and a controlled circuit (6, 6) as part of the plurality of circuits. 8). The controlled circuit includes a flip-flop (12) including a power shut-off unit that is subject to selective power shut-off by a power switch (10) and a power non-shut-off unit that is not subject to selective power shut-off. . The power shut-off unit is a master latch unit (MLAT) that can be powered off by a power switch, and the power non-shut-off unit is a slave latch unit in which a storage node can be selectively connected to a storage node of the master latch unit ( SLATdr). The electric slave latch unit holds data held by the master latch unit when the master latch unit is powered off. That is, the input gate or the input transfer gate unit (STRG) of the slave latch unit is closed in the power cutoff state. The control unit controls a body voltage of the MOS transistor constituting the slave latch unit, and the threshold voltage of the MOS transistor by the body voltage control is when the power source is not shut off than the power source shut off state of the master latch unit. A semiconductor integrated circuit that is smaller.

  From the above, a flip-flop composed of a so-called SOI-type MOS transistor can perform power shut-off and body bias by dividing the master latch portion and the slave latch portion by its own element isolation structure in the SOI-type MOS transistor. In terms of element isolation, the chip occupation area is reduced as compared with the case where a bulk MOS transistor is used. For the slave latch part whose power is not cut off, the body voltage is controlled in accordance with the state of the master latch part where the power can be cut off. According to the control mode, the slave latch unit is body-bias-controlled so that the threshold voltage of the MOS transistor becomes small in the power-off state, and body-bias-controlled so that the threshold voltage of the MOS transistor becomes large in the power-off state. . As a result, an increase in operating speed is ensured in the operating state of the flip-flop supplied with power. Furthermore, when the operation power supply of the master latch unit is shut off due to the standby mode or the like, the body bias of the slave latch unit that holds the stored information is controlled in the direction of increasing the threshold voltage of the MOS transistor, so that the subthreshold leakage current is reduced. Reduced.

  As one specific form of the present invention, some of body voltage control forms by the control unit will be described. First, if the threshold voltage when the body of the MOS transistor constituting the slave latch unit is biased with its own source potential is relatively large, the control unit is configured to operate the slave latch in the non-power-off state of the master latch unit. What is necessary is just to apply the forward bias voltage which makes a threshold voltage small to the body of the said MOS transistor which comprises a part. Second, when the threshold voltage when the body of the MOS transistor constituting the slave latch unit is biased with its own source potential is relatively small, the control unit sets the slave latch unit in the power-off state of the master latch unit. Control may be performed to apply a reverse bias voltage for increasing the threshold voltage to the body of the MOS transistor to be configured. Third, when the threshold voltage when the body of the MOS transistor constituting the slave latch unit is biased with its own source potential is intermediate between the above two modes, the control unit is configured to supply power to the master latch unit. Control is performed to apply a forward bias voltage to reduce the threshold voltage to the body of the MOS transistor that constitutes the slave latch unit in the cutoff state, and the MOS transistor that constitutes the slave latch unit in the power cutoff state of the master latch unit Control to apply a reverse bias voltage for increasing the threshold voltage to the body may be performed.

  As a more specific form of the present invention, considering the low leakage of the master latch part in the power-off state, the body of the MOS transistor constituting the master latch part is a power source on the opposite side to the power-off side power source in the power-off state. It should be biased. For example, when the power switch (10 (n)) is arranged on the ground voltage (VSS) side, when the power switch is turned off, the sources and drains of the various MOS transistors constituting the master latch circuit are connected to the power supply voltage ( VDD). In this state, the body of the n-channel MOS transistor (MNtn) is also set to the power supply voltage, so that no parasitic diode is turned on between the source / drain and the body, and no junction leakage occurs. When the power switch (10 (p) is arranged on the power supply voltage (VDD) side and the power switch is turned off, the sources and drains of the various MOS transistors constituting the master latch circuit are connected to the ground voltage (VSS). In this state, the body of the p-channel MOS transistor (MPtn) is also set to the ground voltage, so that no parasitic diode is turned on and no junction leakage occurs.

  In order to bias the body with a power supply on the side opposite to the power supply cut-off power supply in the power supply cut-off state, for example, the body of the MOS transistor constituting the master latch section may be coupled to its own source.

  Instead of biasing the body with the power supply on the side opposite to the power supply cutoff side power supply in the power supply cutoff state, the body of the MOS transistor constituting the master latch unit may be floated (open) in the power supply cutoff state. There is no leakage path between the source / drain and the body.

  When the floating control is performed, the body of the MOS transistor constituting the master latch unit is preferably biased with its own source voltage in the power supply non-cutoff state. This is because, in the SOI structure, high radiation resistance is realized by fixing or controlling the body potential. Therefore, it is considered advantageous to obtain high soft error resistance in terms of the properties as a memory circuit.

  If the power switch for shutting off the power supply to the master latch part is arranged on both the power supply voltage side and the ground voltage side, there is no problem even if the body bias control is not performed on the master latch part that is turned off. .

[2] << Data retention type FF having save latch section >>
A semiconductor integrated circuit according to another aspect of the present invention includes a MOS transistor having a source, a drain, a body, a gate insulating film on the body, and a gate on the gate insulating film on an insulating thin film of a substrate. A plurality of circuits are included, and a control circuit and a controlled circuit are included as part of the plurality of circuits. The controlled circuit includes a latch unit that can be powered off by a power switch, for example, a master latch unit (MLAT) and a slave latch unit (SLAT), and a retraction latch unit (BLATdr) that cannot be powered off by a power switch. And a flip-flop (13, 14) comprising a transfer gate part (BTRG) for selectively connecting the storage node of the slave latch part and the storage node of the save latch part. The control unit (5) performs save control for saving data held by the slave latch unit to the save latch unit when the power source of the master latch unit and the slave latch unit is shut off, and supplies power to the master latch unit and the slave latch unit When the interruption is released, a return control is performed to restore the data held by the save latch unit to the slave latch unit. The control unit applies a forward bias voltage for reducing a threshold voltage to the body of the MOS transistor constituting the save latch unit during the return control.

  As described above, the flip-flop composed of a so-called SOI type MOS transistor is divided into a master latch unit, a slave latch unit, and a save latch unit due to its own element isolation structure in the SOI type MOS transistor. Even when biasing is performed, the chip occupation area is reduced in terms of element isolation as compared with the case where a bulk MOS transistor is used. When writing data from the slave latch unit to the save latch unit when the power is cut off, and reading data from the save latch unit to the slave latch unit when the power cut is released, body voltage control is performed in consideration of the operation margin of the write and read operations. Is called. According to the control mode, a forward bias voltage for reducing the threshold voltage is applied to the body of the MOS transistor constituting the save latch unit in the return control for reading data from the save latch unit to the slave latch unit. As a result, the drive capability of the save latch unit on the data output side is changed in a larger direction, and the output of the save latch unit tends to be more dominant with respect to the collision with the latch data of the slave latch unit. The operation margin for the read operation to the slave latch unit is increased.

  In order to further increase the operation margin of the read operation to the slave latch unit, the control unit further applies a reverse bias voltage for increasing the threshold voltage to the body of the MOS transistor constituting the slave latch unit during the return control. It is good to do.

  In order to further increase the operation margin of the read operation to the slave latch unit, the control unit further applies a forward bias voltage that reduces the threshold voltage to the body of the MOS transistor constituting the transfer gate unit during the return control. It is good to apply.

  In consideration of the operation margin when writing to the save latch unit, the control unit may apply a forward bias voltage for reducing the threshold voltage to the body of the MOS transistor constituting the slave latch unit in the save control. . In order to further increase the write operation margin, the control unit may apply a reverse bias voltage that increases the threshold voltage to the body of the MOS transistor constituting the save latch unit during the save control.

  As a more specific form of the present invention, considering the low leakage of the master latch unit and the slave latch unit in the power cutoff state, the body of the MOS transistor constituting the master latch unit and the slave latch unit is the power cutoff side in the power cutoff state. Biased with a power supply opposite to the power supply. As a result, the parasitic diode of the MOS transistor is not turned on, and junction leakage does not occur. In order to bias the body with a power supply on the side opposite to the power supply cut-off power supply in the power supply cut-off state, for example, the body of the MOS transistor constituting the master latch section may be coupled to its own source.

  Instead of biasing the body with the power supply on the side opposite to the power supply cut-off power supply in the power supply cut-off state, the body of the MOS transistor constituting the master latch unit may be floated in the power supply cut-off state. There is no leakage path between the source / drain and the body. When the floating control is performed, the body of the MOS transistor constituting the master latch unit is preferably biased with its own source voltage in the power supply non-cutoff state. This is because it is considered that it is a good idea to obtain high soft error resistance because of the nature of the memory circuit.

  According to still another aspect of the present invention, the control unit increases the threshold voltage in the body of the MOS transistor constituting the slave latch unit instead of applying a forward bias voltage to the save latch unit during the return control. A reverse bias voltage may be applied.

  According to still another aspect of the present invention, the control unit does not have to apply a forward bias voltage to all the MOS transistors constituting the save latch unit during the return control. A forward bias voltage for reducing the threshold voltage may be applied to the body of the MOS transistor capable of driving at least the storage node of the slave latch unit.

[3] << Expansion of return operation margin of data holding type FF having save latch section >>
A semiconductor integrated circuit according to still another aspect of the present invention comprises a MOS transistor having a source, a drain, a body, a gate insulating film on the body, and a gate on the gate insulating film on an insulating thin film of a substrate. A plurality of circuits are included, and a control circuit and a controlled circuit are included as part of the plurality of circuits. The controlled circuit includes a master latch unit (MLAT) and a slave latch unit (SLAT) that can be powered off by a power switch, a save latch unit (BLATdr) that cannot be powered off by the power switch, and the slave A save gate unit (SGT) for selectively allowing the storage node of the latch unit to communicate with the storage node of the save latch unit, and a switch to the storage node of the slave latch unit using the storage node of the save latch unit as a switch control input It has a flip-flop (15, 16, 17) composed of a return gate section (RGT (t), RGT (b)) for providing an output. The control unit (5) performs save control to save the data held by the slave latch unit in the save latch unit when the power of the master latch unit and the slave latch unit is shut off, and the master latch unit and the slave latch unit When canceling the power shutdown, the slave latch unit performs a return control to restore the data held by the save latch unit. The control unit applies a forward bias voltage for reducing a threshold voltage to the body of the MOS transistor constituting the save latch unit during the return control.

  The main purpose of the save latch unit is to back up the stored information of the slave latch unit when the power is cut off, and it is not necessary to consider high-speed operation like the normal operation of the flip-flop, and the transistor size can be reduced, Low power consumption may be prioritized using a large threshold voltage. In this case, a case where a necessary operation margin cannot be ensured only by the forward bias control for the save latch unit when the save data is restored is considered. According to this, when the saved data is returned to the slave latch unit, the switch output of the return gate having the return source data as the switch control data is given to the return destination. Even if the driving capability is considerably smaller than the driving capability, the reading operation from the save latch unit to the slave latch unit can be normally performed even if the driving capability is insufficient.

  In order to further increase the operation margin of the read operation to the slave latch unit, a forward bias voltage for reducing the threshold voltage may be applied to the body of the MOS transistor constituting the save latch unit during the return control. Further, the control unit may apply a reverse bias voltage for increasing a threshold voltage to the body of the MOS transistor constituting the slave latch unit in the return control. The control unit may apply a forward bias voltage for reducing the threshold voltage to the body of the MOS transistor constituting the return gate unit during the return control.

  In the case of this flip-flop, the driving capability of the slave latch unit is larger than the driving capability of the save latch unit, but considering the operation margin when writing to the save latch unit, the control unit performs the save control. A forward bias voltage for reducing the threshold voltage may be applied to the body of the MOS transistor constituting the slave latch unit. The controller may apply a reverse bias voltage for increasing a threshold voltage to a body of the MOS transistor constituting the save latch unit during the save control.

  As a more specific form of the present invention, considering the low leakage of the master latch unit and the slave latch unit in the power cutoff state, the body of the MOS transistor constituting the master latch unit and the slave latch unit is the power cutoff side in the power cutoff state. Biased with a power supply opposite to the power supply. As a result, the parasitic diode of the MOS transistor is not turned on, and junction leakage does not occur. In order to bias the body with a power supply on the side opposite to the power supply cut-off power supply in the power supply cut-off state, for example, the body of the MOS transistor constituting the master latch section may be coupled to its own source.

  Instead of biasing the body with the power supply on the side opposite to the power supply cut-off power supply in the power supply cut-off state, the body of the MOS transistor constituting the master latch unit may be floated in the power supply cut-off state. There is no leakage path between the source / drain and the body. When the floating control is performed, the body of the MOS transistor constituting the master latch unit is preferably biased with its own source voltage in the power supply non-cutoff state. This is because it is considered that it is a good idea to obtain high soft error resistance because of the nature of the memory circuit.

  According to still another aspect of the present invention, the control unit increases the threshold voltage in the body of the MOS transistor constituting the slave latch unit instead of applying a forward bias voltage to the save latch unit during the return control. A reverse bias voltage may be applied.

  According to still another aspect of the present invention, the control unit does not have to apply a forward bias voltage to all the MOS transistors constituting the save latch unit during the return control. A forward bias voltage for reducing the threshold voltage may be applied to the body of the MOS transistor capable of driving at least the storage node of the slave latch unit.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to optimize the body bias control for the circuit part that can be turned off and the circuit part that cannot be turned off, constituting the data holding type flip-flop using the SOI type MOS transistor, according to the operation state.

<< Semiconductor integrated circuit using SOI type MOS transistor >>
FIG. 2 illustrates a planar configuration of the semiconductor integrated circuit 1 according to the present invention. Here, a MOS integrated circuit having a digital / analog mixed SOI structure is taken as an example. A peripheral portion of the semiconductor integrated circuit 1 is a formation region of an input / output circuit 2 as an external interface circuit, and a digital circuit region 3 and an analog circuit region 4 are formed as core circuit regions therein. The digital circuit area 3 includes a power supply control and body bias control circuit 5, a power supply cutoff circuit 6 that can selectively cut off the supply of operating power by the power supply control and body bias control circuit 5, and a supplied operating power supply. Is provided with a power non-cutoff circuit 7 that is always supplied. The analog circuit area 4 includes a power cutoff circuit 8 that can selectively cut off the supply of operation power by the power supply control and body bias control circuit 5, and a power supply non-cutoff circuit 9 that is constantly supplied with operating power. Have. A power switch 10 is disposed in the power cutoff circuit 6, 8. The arrangement of the power switch 10 in the power cutoff circuit 6, 8 may be random. Needless to say, the power cutoff circuit 6 and the non-power cutoff circuit 7 can be further subdivided as required. Although not shown, the power switch 10 may be arranged along the center of each of the power cutoff circuits 6 and 8 or along the bottom of each of the cutoff circuits 6 and 8 because of the regularity of the layout. is there. Although details will be described later, the layout of the power switch 10 is basically not limited by the device structure. In this specification, the term “power cutoff” simply means power cutoff due to the OFF state of the power switch 10, and the term “power cutoff” means power supply due to the ON state of the power switch 10. This is a different concept from power-on in which an external power supply is turned on for the entire semiconductor integrated circuit and power-off in which the external power supply is shut off for the entire semiconductor integrated circuit.

  FIG. 3 illustrates a vertical cross-sectional structure of an SOI type MOS transistor constituting the semiconductor integrated circuit 1. The MOS transistor is formed in the active region through a buried oxide film EOX which is an insulating thin film of 20 to 200 nanometers on the silicon substrate BPL. The active regions are a source SOC, a drain DRN, and a body BDY. The body BDY becomes a channel formation region. A gate GAT is formed on the body BDY via a gate insulating film GOX. The source SOC, the drain DRN, and the body BDY are electrically isolated from the surroundings by a complete isolation region FTI (or partial isolation region OTI) in which a trench formed by, for example, STI (Shallow Trench Isolation) is covered with silicon oxide, The silicon substrate is electrically separated by a buried oxide film EOX.

Here, the MOS transistor includes an n-channel MOS transistor MNtn and a p-channel first MOS transistor MPtn as a first MOS transistor (thin film MOS transistor) having a relatively thin gate oxide film, and a second MOS having a relatively thick gate oxide film. The transistors are classified into n-channel type MOS transistors MNtk and p-channel type MOS transistors MPtk as transistors (thick film MOS transistors). In the n-channel MOS transistor, the source SOC and the drain DRN are N ⁺ type diffusion layers, and the body BDY is a P ⁻ type diffusion layer. In p-channel type MOS transistor, the source SOC and drain DRN is ^{P +} -type diffusion layer, the body BDY is N ^- consists -type diffusion layer.

  The thin film MOS transistors MNtn and MPtn have, for example, a channel length of 45 to 180 nanometers (nm), a gate oxide film thickness of 1.5 to 3.9 nm, and a gate input voltage amplitude corresponding to the gate oxide film thickness of 0.8 V to 1. 5V. The thick film MOS transistors MNtk and MPtk have, for example, a channel length of 300 to 1000 nm, a gate oxide film thickness of 3.0 to 15.0 nm, and a gate input voltage amplitude corresponding to the gate oxide film thickness of 1.2 V to 5.0 V. The The thin film MOS transistors MNtn and MPtn are mainly used to configure a digital logic circuit and an analog circuit in the core logic region. The thickness-preserving film MOS transistors MNtk and MPtk are used to constitute a part of the input / output circuit and the analog circuit because of their high breakdown voltage, and are also used to constitute the power cutoff switch 10 because of their high threshold voltage.

4 is a bird's eye view of an n-channel MOS transistor having an SOI structure, FIG. 5 is a longitudinal sectional view of FIG. 4, and FIG. 6 is a plan view of FIG. 4 to 6, in the SOI structure, the source SOC, the drain DRN, and the body BDY are electrically isolated from the surroundings by the complete isolation region FTI or the partial isolation region PTI, and are electrically isolated from the silicon substrate by the buried oxide film EOX. It is clear that In particular, the body BDY may be floating, or body bias may be performed to prevent fluctuations in the body potential or control the threshold voltage. When the body bias is performed, the body BDY is connected to a contact region CNT made of, for example, a P-type diffusion region (P ⁺ ) using the partial isolation region PTI. Here, an example is shown in which the contact region CNT is connected to a metal ground wiring VSS to which the source SOC is connected.

  Thus, in the SOI structure, individual MOS transistors are electrically isolated, so that it is not necessary to perform isolation by a well region according to the difference in the conductivity type of the MOS transistor, the power supply voltage, and the like. Furthermore, there is almost no junction capacitance with the substrate and no current leakage with the substrate, which is excellent in low voltage operation and high speed operation.

  FIG. 7 illustrates a basic circuit configuration of the power cutoff circuit 6 and the non-power cutoff circuit 7 in consideration of the characteristics of the SOI structure. The power cutoff circuit 6 arranged between the power supply wiring VDD and the ground wiring VSS has thick film MOS transistors MNtk and MPtk as the power switch 10, and the power non-cutoff circuit 7 is a thick film MOS transistor MNtk as the power switch. , MPtk. In the power cutoff circuit 6, a circuit represented by a CMOS inverter composed of a plurality of thin film MOS transistors MNtn and MPtn is connected in series to the thick film MOS transistors MNtk and MPtk as the power switch 10. The power non-cutoff circuit 8 also has a circuit represented by a CMOS inverter in which a plurality of thin film MOS transistors MNtn and MPtn are connected in series. For example, when the ground voltage VSS is 0 V and the power supply voltage VDD is 1.5 V, the gate input voltage amplitude of the thin film MOS transistors MNtn and MPtn is 1.5 V. At this time, the thick film MOS transistors MNtk and MPtk constituting the power switch 10 are set. The gate input voltage amplitude is 3.3V. Although not specifically shown, the thick film MOS transistor uses only one of the MNtk and MPtk as the power switch 10 in the power cut-off possible circuit 6, or both thick film MOS transistors MNtk and MPtk are used in one power cut-off possible circuit. You may make it use. In addition, regarding the symbol marking of the MOS transistor on the drawing, the gate of the p-channel MOS transistor is marked with a circle to distinguish it from the n-channel MOS transistor, and the gate of the thick film MOS transistor is marked relatively thick. This distinguishes it from a thin film MOS transistor.

  The thick film MOS transistors MNtk and MPtk constituting the power switch 10 can be freely laid out without performing region isolation such as well isolation with the thin film MOS transistors MNtn and MPtkn that perform logical operations and the like. The channel type thin film MOS transistor MNtn and the p channel type thin film MOS transistor MPtn can be freely laid out without performing region isolation such as well isolation.

  FIG. 8 shows a circuit configuration of a power cutoff possible region and a power non-shutdown region constituted by bulk MOS transistors as a comparative example of FIG. Although not specifically shown, in a bulk CMOS circuit, a p-channel MOS transistor is formed in an n-type well region, an n-channel MOS transistor is formed in a p-type well region, well region isolation is performed, and the substrate and well region are separated. Meanwhile, the well region and the source / drain are reversely biased for electrical isolation. FIG. 8 does not clearly show how the well region is separated by the conductivity type of the MOS transistor. However, in the configuration using the bulk type MOS transistor, the power-off possible region 6A and the power non-cut-off circuit 7A are separated and the power is cut off. In the possible region 6A, the region 6A_1 where the power switch is formed by the thick film MOS transistor MBNtk and the region 6A_2 where the logic operation or the like is performed are also required to be separated. The region 6A_1 for forming the power switch and the region 6A_2 for performing a logic operation or the like are separated from the region 6A_2 for performing a logic operation or the like in the power cutoff region 6A. This is to reduce junction leakage. In the configuration of FIG. 7, since each MOS transistor does not leak to the substrate by the buried oxide film EOX in the first place, such consideration is essentially not required for the device structure. In FIG. 8, the power supply cutoff region 6A and the power supply non-cutoff circuit 7A are separated from each other in that the well potential of the power supply noncutoff circuit 7A is the ground potential VSS. This is because there is a difference in that the well potential becomes a virtual ground VSSM which is the drain voltage of the power switch MBNtk when operating power is supplied. Although not specifically shown, the same applies to the case where the power switch is a p-channel MOS transistor or a thin film MOS transistor. In the configuration of FIG. 7, each MOS transistor can be separated from the body DBY by the buried oxide film EOX and the isolation region FTI (or the isolation region PTI), so that well region isolation is essentially not required.

<< Transistor characteristics according to the body bias type >>
Here, the characteristics of floating with respect to the body of the MOS transistor, body bias by the source potential, and variable control of the body bias will be described in advance. The relationship between the body potential of the MOS transistor and the threshold voltage tends to be as shown in FIG. In FIG. 9, the body potential 0V means equal to the source potential. A positive body potential means a potential closer to the drain, and a negative body potential means a potential in the opposite direction. In the case of an n-channel MOS transistor, the threshold voltage decreases (decreases) as the body voltage increases, and in the case of a p-channel MOS transistor, the threshold voltage decreases (decreases) as the body voltage decreases. For convenience, the body bias in the direction of decreasing the threshold voltage is referred to as a forward bias, and the body bias in the direction of increasing the threshold voltage is referred to as a reverse bias.

  If the body potential is fixed at its own source potential or the like, undesired fluctuations in the threshold voltage can be suppressed. In addition, in the SOI structure, radiation resistance can be increased by fixing or controlling the body potential, and high soft error resistance can be obtained in a memory circuit as will be described later.

  By floating the body, the body potential varies due to capacitive coupling with the gate, and the body potential varies in the direction of decreasing the threshold voltage when the MOS transistor is on. This can contribute to high-speed operation of the logic circuit.

  If the body bias is made variable, it is possible to emphasize the advantages of high-speed operation with a small threshold voltage by applying a forward bias, and reducing the subthreshold leak due to a large threshold voltage by applying a reverse bias. It becomes possible to emphasize low power consumption.

<Adoption of data-holding flip-flops for logic circuits>
FIG. 10 illustrates a logic circuit configured by mixing the power cutoff circuit 6 and the power non-cutoff circuit 7 together. Here, typically, five logic circuits LOG1 to LOG5 are illustrated, and the arrangement of flip-flops is illustrated for each of the logic circuits LOG1 to LOG5. The illustrated flip-flops are a data holding type flip-flop DR_FF and a completely volatile normal flip-flop V_FF. The data holding type flip-flop DR_FF is a flip-flop that maintains stored information by maintaining power supply to only some circuits when the operating power supply is shut off. In the normal flip-flop V_FF, all stored information is lost when the operating power is cut off. For the data holding flip-flop DR_FF and the completely volatile normal flip-flop V_FF, an appropriate storage form such as a set / reset type or a delay type may be basically adopted.

  A circuit such as the logic circuit LOG2 in which the power supply is not shut off by the power switch 10 may employ only the volatile flip-flop V_FF as the flip-flop. Further, even a circuit such as the logic circuit LOG4 in which the power supply is shut off by the power switch 10, a circuit in which the stored information of the flip-flop may be lost due to the power shutoff by the power switch 10, or the flip-flop at the time of power shutoff In the case of adopting a configuration in which the stored information is saved in the memory and the stored information is restored from the memory to the flip-flop when the power-off is released, only the volatile flip-flop V_FF may be employed. Naturally, since the memory save / restore structure requires memory access, it takes a time that cannot be ignored to save / restore the stored information of the flip-flop, and there is a case where the high-speed operation is not described manually. In a circuit such as the logic circuits LOG1, LOG3, and LOG4 in which the power supply is shut off by the power switch 10, a data holding type flip-flop DR_FF may be adopted as a flip-flop in a portion where the stored information is not lost due to the power shutdown. Since the data holding type flip-flop DR_FF holds stored information for each flip-flop when the power is cut off, the saving / restoring speed can be increased compared to the memory saving / restoring structure, which is suitable for high-speed operation.

  As shown in detail in part of the logic circuit LOG1, an appropriate combinational circuit CMBC is connected to the inputs and outputs of the flip-flops DR_FF and V_FF in the logic circuit LOG1, and the flip-flops DR_FF and V_FF input data in synchronization with the clock. Output.

《Data retention type FF that makes the slave latch part power off ''
FIG. 1 shows an example of a data holding flip-flop (DRFF) 12. The DRFF 12 shown in the figure includes a data path formed by connecting a data input buffer DIB, a master transfer gate unit MTRG, a master latch unit MLAT, a slave transfer gate unit STG, a slave latch unit SLATdr, and a data output buffer DOB, and a clock. And a buffer CBUFdr. The master transfer gate unit MTRG and the slave transfer gate unit STRG are composed of CMOS inverters. Each of master latch unit MLAT and slave latch unit SLATdr is formed of a CMOS static latch in which one input is coupled to the other output. The data input terminal D of the DRFF 12 is connected to the input terminal of the data input buffer DIB, and the data output terminal Q of the DRFF 12 is connected to the output terminal Q of the data output buffer DOB. The clock buffer CBUFdr includes a two-stage serial CMOS inverter coupled to the clock terminal CLK of the DRFF 12, and outputs a non-inverted internal clock signal cki from the subsequent CMOS inverter and outputs an inverted internal clock signal chibi from the previous CMOS inverter. . The master transfer gate unit MTRG and the slave transfer gate unit STRG are switch-controlled in opposite phases by the internal clock signals cki and ckib, and are prevented from penetrating during data latching.

  The master latch unit MLAT and the data input / output buffers DIB and DOB can be selectively cut off by the power switch 10. In the figure, the power switch 10 is disposed on each of the power supply voltage VDD side and the ground voltage VSS side, but it is sufficient if it is disposed on at least one of them. When the power switch 10 (n) on the ground terminal VSS side is cut off, the node vssm reaches the power supply voltage VDD. When the power switch 10 (p) on the power supply terminal VDD side is cut off, the node vddm reaches the ground voltage VSS. The slave latch unit SLATdr and the clock buffer CBUFdr are not subject to selective power-off by a power switch.

  The body vssx and vddx of the MOS transistors MPtn and MNtn constituting the master latch unit MLAT and the data input / output buffers DIB and DOB capable of shutting off the power supply are, for example, supplied to their sources, that is, Coupled to nodes vssm and vddm. Alternatively, the bodies vssx and vddx may be floated (open) when the power is shut off. That is, as illustrated in FIG. 11, when the power supply switch 10 (n) on the ground voltage VSS side is cut off, the node vssm reaches the power supply voltage VDD, and thus the body of the MOS transistor MNtn as shown in A and B. If BDY is connected to the ground voltage VSS, a junction leakage current may occur at the pn junction between the body BDY and the drain DRN of the MOS transistor MNtn. At this time, like C, the body BDY of the MOS transistor MNtn may be connected to the node vssm so as to be biased by the power supply voltage VDD on the side opposite to the power supply cutoff power supply VSS. Or you may make it floating. As a result, there is no junction leakage and the parasitic diode is not turned on between the source / drain and the body. The bodies of the transfer gate portions MTRG and STRG may be controlled similarly.

  On the other hand, when the power switch 10 (p) on the power supply voltage VDD side is cut off, the node vddm reaches the ground voltage VSS as illustrated in FIG. If the body BDY is connected to the power supply voltage VDD, a junction leakage current may occur at the pn junction between the body BDY and the drain DRN of the MOS transistor MPtn. At this time, as in C, the body BDY of the MOS transistor MPtn may be connected to the node vddm so as to be biased by the ground voltage VSS on the opposite side to the power cutoff side power supply VDD. Or you may make it floating. As a result, there is no junction leakage and the parasitic diode is not turned on between the source / drain and the body.

  11 and 12, when the nodes vssx and vddx are opened when the power is shut down, in a power-off state, if high speed operation is desired, a forward bias voltage is applied to the nodes vssx and vddx, and low power consumption is desired. A reverse bias voltage may be applied. Alternatively, a potential such as its own source potential may be applied. Such control is performed by the power supply control and body bias control circuit 5 in accordance with the operation mode and the like. The reason why the nodes vssx and vddx are not left floating in the non-power-off state is that it is considered to be advantageous to obtain high soft error resistance because of the nature of the memory circuit. That is, the SOI structure for fixing or controlling the body potential has high radiation resistance and high soft error resistance.

  In order to cut off the power switches 10 (n) and 10 (p) arranged on both the power supply voltage VDD side and the ground voltage VSS side in order to cut off the power supply to the master latch unit MLAT, the power supply was cut off. There is no problem even if the body bias control is not performed on the master latch unit MLAT.

  11 and 12, the body BDY is illustrated as a well. However, this is a drawing consideration for illustrating the body bias node, and does not limit the device structure.

  The bodies of the MOS transistors MPtn and MNtn constituting the slave latch unit SLATdr and the clock buffer CBUFdr that are not subject to power shutdown are controlled variably by body bias voltages vbp and vbn. The control is performed by the power supply control and body bias control circuit 5 according to the operation mode. The control mode is as follows. The power source control and body bias control circuit 5 makes the body bias voltages vvp and vbn of the MOS transistors MPtn and MNtn constituting the slave latch unit SLATdr different between the power cutoff state and the power non-off state of the master latch unit MLAT. . That is, the body bias voltages vvp and vbn are controlled so that the threshold voltages of the MOS transistors MPtn and MNtn constituting the slave latch unit SLATdr are larger when the power is not shut off than when the power is not turned off. According to this, the slave latch unit SLATdr is subjected to body bias control so that the threshold voltages of the MOS transistors MPtn and MNtn are reduced in the power supply non-cutoff state, and the threshold voltages of the MOS transistors MPtn and MNtn are increased in the power supply cutoff state. Since body bias control is performed, the DRFF 12 in the non-power-off state is guaranteed to increase the operating speed in the operating state. Further, when the operating power supply of the master latch unit MLAT is cut off due to the standby mode or the like, the body bias voltage of the slave latch unit SLATdr that holds the stored information is controlled to increase the threshold voltages of the MOS transistors MPtn and MNtn. Subthreshold leakage current is reduced.

  The body bias control for the slave latch unit SLATdr differs depending on the threshold voltage characteristics of the MOS transistors MPtn and MNtn constituting the slave latch unit. That is, first, when the threshold voltage when the body of the MOS transistors MPtn and MNtn constituting the slave latch unit SLATdr is biased with its own source potential is relatively large, the power supply control and body bias control circuit 5 In the non-power-off state of the master latch unit MLAT, a forward bias voltage for reducing the threshold voltage may be applied to the bodies of the MOS transistors MPtn and MNtn constituting the slave latch unit SLATdr. In the power cut-off state, it is not necessary to apply a reverse bias voltage in particular, and it is sufficient to apply a voltage corresponding to the potentials of the nodes vssm and vddm to the bodies of the MOS transistors MPtn and MNtn.

  Second, when the threshold voltage when the body of the MOS transistors MPtn and MNtn constituting the slave latch unit SLATdr is assumed to be biased with its own source potential is relatively small, the power supply control and body bias control circuit 5 The master latch unit MLAT may be controlled to apply a reverse bias voltage for increasing the threshold voltage to the bodies of the MOS transistors MPtn and MNtn constituting the slave latch unit SLATdr when the power is cut off. In the non-power-off state, no special forward bias voltage need be applied, and a voltage corresponding to the potentials of the nodes vssm and vddm may be applied to the bodies of the MOS transistors MPtn and MNtn.

  Third, when it is assumed that the body of the MOS transistors MPtn and MNtn constituting the slave latch unit SLATdr is biased by its own source potential, the power supply control is performed when the threshold voltage is intermediate between the above two modes. And the body bias control circuit 5 performs a control to apply a forward bias voltage for reducing a threshold voltage to the bodies of the MOS transistors MPtn and MNtn constituting the slave latch unit SLATdr when the master latch unit MLAT is in a power-off state. Control may be performed to apply a reverse bias voltage for increasing the threshold voltage to the bodies of the MOS transistors MPtn and MNtn constituting the slave latch unit SLATdr when the master latch unit MLAT is powered off.

  The reason why the clock buffer CBUFdr is not targeted for power shutdown by the power switch 10 is that the voltage at the output node of the master latch unit MLAT does not undesirably invert the stored information held by the slave latch unit SLATdr in the power shutdown state. This is because the slave transfer gate unit STRG can be kept cut off. Therefore, when the power is shut off, the input of the clock terminal CLK may be fixed at a low level. If the body bias voltage is controlled in the same manner as the slave latch unit SLATdr by vbp and vbn as shown in the figure, it can contribute to the reduction of the subthreshold leakage current in the power-off state.

<Data retention type FF having a power supply non-cut-off retraction latch unit>
FIG. 13 shows another example of a data holding type flip-flop (DRFF). The DRFF 13 shown in the figure includes a data path comprising a data input buffer DIB, a master transfer gate unit MTRG, a master latch unit MLAT, a slave transfer gate unit STG, a slave latch unit SLAT, and a data output buffer DOB, and a clock buffer. And CBUF. Furthermore, a save latch unit BLATdr is provided in which the storage node is connected to the storage node of the slave latch unit SLAT via the save / return transfer gate unit BTRG. The master transfer gate unit MTRG, the slave transfer gate unit STRG, and the save / return transfer gate unit BTRG are composed of CMOS inverters. Each of the master latch unit MLAT, the slave latch unit SLATdr, and the save latch unit BLATdr is configured by a CMOS static latch in which one input is coupled to the other output. TR is a transfer control signal of the save / return transfer gate unit BTRG.

  The power input switch DIB, the master latch unit MLAT, the slave latch unit SLAT, the data output buffer DOB, and the clock buffer CBUF can be selectively cut off by the power switch 10. In the figure, the power switch 10 is disposed on each of the power supply voltage VDD side and the ground voltage VSS side, but it is sufficient if it is disposed on at least one of them. When the power switch 10 (n) on the ground terminal VSS side is cut off, the node vssm reaches the power supply voltage VDD. When the power switch 10 (p) on the power supply terminal VDD side is cut off, the node vddm reaches the ground voltage VSS. The retraction latch unit BLATdr is not subject to selective power shut-off by a power switch.

  The body vssx and vddx of the MOS transistors MPtn and MNtn constituting the data input buffer DIB, the master latch unit MLAT, the slave latch unit SLAT, the data output buffer DOB, and the clock buffer CBUF that can be powered off by the power switch 10 are: As in the case of FIG. 1, in order to suppress the junction leakage when the power is shut off, the bodies vssx and vddx are floated (opened), for example, coupled to their own sources, ie, the nodes vssm and vddm, or when the power is shut off. To be. As described above, there is no leakage and no parasitic diode is turned on between the source / drain and the body.

  The bodies of the MOS transistors MPtn and MNtn that constitute the save latch unit BLATdr that is not subject to power shutoff are variably controlled by body bias voltages vbp and vbn. The control is performed by the power supply control and body bias control circuit 5 according to the operation mode. The control mode is as follows.

  The power supply control and body bias control circuit 5 performs save control to save the data held by the slave latch unit in the save latch unit when the power source of the master latch unit MLAT and the slave latch unit SLAT is shut off by the power switch 10. . In other words, the data held by the slave latch unit SLAT is latched by the save latch unit BLATdr via the save / return transfer gate unit BTRG. After the latch operation by the save latch unit BLATdr is completed, the operation power supply is shut off by the power switch 10. The power supply control and body bias control circuit 5 returns the data held by the save latch unit BLATdr to the slave latch unit SLAT when releasing the power cutoff of the master latch unit MLAT and the slave latch unit SLAT. Take control. That is, first, the power switch 10 is turned on, and thereafter, the data held by the save latch unit BLATdr is latched by the slave latch unit SLAT via the save / restore transfer gate unit BTRG.

  The power supply control and body bias control circuit 5 writes data from the slave latch unit SLAT to the save latch unit BLATdr in the save control when the power supply is cut off, and slaves from the save latch unit BLATdr in the return control when the power supply is released. When reading data into the latch unit SLAT, body voltage control is performed in consideration of the operation margin of the write operation and the read operation. As a first control mode, the power supply control and body bias control circuit 5 reduces the threshold voltage as the body voltages vbp and vbn of the MOS transistors MPtn and MNtn constituting the save latch unit BLATdr during the return control. Apply forward bias voltage. According to this, in the return operation in which data is read from the save latch unit BLATdr to the slave latch unit SLAT, the drive capability of the save latch unit BLATdr on the data output side is changed in a larger direction, and the latch data of the slave latch unit SLAT is changed. Therefore, the operation margin of the read operation to the slave latch unit SLAT can be increased in that the output of the evacuation latch unit BLATdr tends to prevail with respect to the collision with the slave latch unit SLAT.

  Although not specifically shown, in order to further increase the operation margin of the read operation to the slave latch unit, the power supply control and body bias control circuit 5 further includes the MOS transistor constituting the slave latch unit SLAT during the return control. A reverse bias voltage that increases the threshold voltage is preferably applied to the bodies of MPtn and MNtn. In order to further increase the operation margin of the read operation to the slave latch unit SLAT, the power supply control and body bias control circuit 5 further includes the MOS transistors MNtn, which constitute the save / return transfer gate unit BTRG during the return control. A forward bias voltage for reducing the threshold voltage is preferably applied to the body of MPtn.

  In consideration of an operation margin when writing to the save latch unit, the power supply control and body bias control circuit 5 applies a threshold voltage to the bodies of the MOS transistors MNtn and MPtn constituting the slave latch unit SLAT during the save control. A forward bias voltage to be reduced may be applied. In order to further increase the write operation margin, the power supply control and body bias control circuit 5 uses the threshold voltages as the body bias voltages vbn and vbp of the MOS transistors MNtn and MPtn constituting the save latch unit BLATdr during the save control. What is necessary is just to apply the reverse bias voltage which enlarges.

  FIG. 14 shows another example of a data holding type flip-flop (DRFF). The DRFF 14 shown in the figure is different from the DRFF 13 in FIG. 13 in the connection form of the slave latch unit SLAT and the save latch unit BLATdr. In the DRFF 13 of FIG. 13, the save / return transfer gate unit BTRG has a bidirectional data transfer direction. In the DRFF 14 of FIG. 14, the save transfer gate unit BTRG (S) is used when the data stored in the slave latch unit SLAT is written into the save latch unit BLATdr, and the data is restored when the data in the save latch unit BLATdr is read into the slave latch unit SLAT. The transfer gate part BTRG (R) is used. When this configuration is adopted, the following body bias control is adopted. That is, the power supply control and body bias control circuit 5 performs the threshold voltage on the bodies of the MOS transistors MPtn and MNtn constituting the inverter IVa and the save transfer gate part BTRG (S) included in the slave latch part SLAT during the save control. Apply a forward bias voltage to reduce the. Further, the power supply control and body bias control circuit 5 performs threshold voltage application to the bodies of the MOS transistors MPtn and MNtn constituting the inverter IVb and the return transfer gate part BTRG (R) included in the save latch part SLAT during the return control. Apply a forward bias voltage to reduce the. By this control, the driving margin of the output source circuit that outputs data is changed in each of save and return, so that the operation margin can be increased. As other configurations, the same configurations as those in FIG. 13 can be adopted as appropriate.

<< Expansion of return operation margin in data retention type FF >>
FIG. 15 shows another example of a data holding flip-flop (DRFF). The DRFF 15 shown in the figure makes it possible to greatly expand the operation margin in the data restoration operation from the retracting touch unit BLATdr to the slave latch unit SLAT. The difference from FIGS. 13 and 14 is that a transfer gate unit is used for evacuation and a gate receiving an input at the switch control terminal is used for restoration. That is, the save latch unit BLATdr is mainly used to back up the stored information of the slave latch unit SLAT when the power is cut off, and the save latch unit BLATdr needs to consider high-speed operation like the normal operation of DRFF. Alternatively, the transistor size may be reduced, or low power consumption may be prioritized using a large threshold voltage. In this case, a case where a necessary operation margin cannot be ensured only by the forward bias control for the save latch unit BLATdr when the save data is restored is considered. Therefore, for the saving from the slave latch unit SLAT to the save latch unit BLATdr, the save transfer gate unit SGT including the n-channel MOS transistors MNtn that are switch-controlled by the signal STR is used. To return from the save latch unit BLATdr to the slave latch unit SLAT, return gate units RGT (t) and RGT (b) each including a p-channel MOS transistor MPtn are employed. The return gate units RGT (t) and RGT (b) have a connection configuration in which the storage node of the save latch unit BLATdr is used as a switch control input to provide a switch output to the storage node of the slave latch unit SLAT. Specifically, one return gate portion RGT (t) has a gate connected to one input / output node constituting a static latch of the save latch portion BLATdr, and a power switch PST whose source is a p-channel MOS transistor. The drain is connected to the other input / output node of the slave latch unit SLAT. The other return gate portion RGT (b) has a gate connected to the other input / output node constituting the static latch of the save latch portion BLATdr, a source connected to a power switch PST formed of a p-channel MOS transistor, and a drain. Are connected to one input / output node of the slave latch unit SLAT. The power switch PST is turned on by a restore signal RSTR which is set to a low level in response to the return operation, thereby supplying the power supply voltage VDD.

  According to this, when the saved data is returned to the slave latch portion SLAT, the switch outputs of the return gate portions RGT (t) and RGT (b) using the return source data as switch control data are given to the return destination. The drive capability of the save latch unit BLATdr is made considerably smaller than the drive capability of the slave latch unit SLAT, and the read operation from the save latch unit BLATdr to the slave latch unit SLAT is normally performed even if the drive capability is insufficient. be able to.

  At this time, the power supply control and body bias control circuit 5 applies forward bias voltages vbp and vbn for reducing the threshold voltage to the bodies of the MOS transistors MPtn and MNtn constituting the save latch unit BLATdr during the return control. . Thereby, the operation margin of the data read operation from the save latch unit BLATdr to the slave latch unit SLAT can be further expanded. In order to further expand the operation margin, although not shown in particular, the power supply control and body bias control circuit 5 applies a threshold value to the bodies of the MOS transistors MPtn and MNtn constituting the slave latch unit SLAT during the return control. A reverse bias voltage for increasing the voltage may be applied. Further, the power supply control and body bias control circuit 5 performs a forward bias voltage for reducing a threshold voltage in the body of the MOS transistor MPtn constituting the return gate portions RGT (t) and RGT (b) during the return control. May be applied.

  In the case of this flip-flop DRFF15, the driving capability of the slave latch unit SLAT is larger than the driving capability of the save latch unit BLATDR, but considering the operation margin when writing to the save latch unit BLATdr, the power supply control and the body The bias control circuit 5 may apply a forward bias voltage for reducing a threshold voltage to the bodies of the MOS transistors MPtn and MNtn constituting the slave latch unit SLAT during the save control. The power supply control and body bias control circuit 5 may apply a reverse bias voltage for increasing a threshold voltage to the bodies of the MOS transistors MPtn and MNtn constituting the save latch unit BLATdr during the save control.

  As for the leakage current reduction of the master latch unit MLAT and the slave latch unit SLAT in the power cutoff state, the body of the MOS transistor constituting the master latch unit MLAT and the slave latch unit SLAT is the power cutoff side in the power cutoff state. Biasing with a power supply opposite to the power supply or floating is preferable.

  The power supply control and body bias control circuit 5 increases the threshold voltage in the body of the MOS transistor constituting the slave latch unit SLAT instead of applying a forward bias voltage to the save latch unit BLATdr during the return control. A reverse bias voltage may be applied. Further, the power supply control and body bias control circuit 5 does not need to apply the forward bias voltage to all the MOS transistors constituting the save latch unit BLATdr during the return control, as described with reference to FIG. In the save latch unit BLATdr, a forward bias voltage for reducing a threshold voltage may be applied to the body of the MOS transistor capable of driving at least the storage node of the slave latch unit SLAT.

  FIG. 16 shows another example of a data holding type flip-flop (DRFF). The DRFF 16 shown in the figure is an example in which the connection form of the master latch unit MLAT, the slave latch unit SLAT, and the save latch unit BLATdr is changed, and the number of CMOS inverters arranged in series in the data path is reduced to four. Furthermore, the difference from FIG. 15 is that the saving from the slave latch unit SLAT to the save latch unit BLATdr is performed by a complementary signal. SGT (t) and SGT (b) are save gate units that control transfer of save data of complementary signals. Needless to say, the connection form shown in FIG. 16 may be adopted for the static latch in the DRFF shown in FIGS.

  FIG. 17 illustrates the control timing of the evacuation operation for the DRFF of FIG. 15 or FIG. The power cutoff control target is the power switch 10 (n). The switch control signal is SWCNT (n). When the power supply control and body bias control circuit 5 shuts off the power supply at time t3, the body voltages vddx and vssx are changed to forward bias and the body voltages vbp and vbn are changed to reverse bias at the previous time t0. That is, the body bias voltage vddx is set to a forward bias voltage lower than the power supply voltage VDD, the body bias voltage vssx is set to a forward bias voltage higher than the ground voltage VSS, and the body bias voltage vbp is set to a reverse bias voltage higher than the power supply voltage VDD. The body bias voltage vbn is set to a reverse bias voltage lower than the ground voltage VSS. As a result, the drive capability of the slave latch unit SLAT is increased, and the drive capability of the save latch unit BLATdr is decreased. Therefore, after that, when the power supply control and body bias control circuit 5 activates the store signal STR (time t1), the slave latch unit SLAT drives the storage node of the save latch unit BLATdr according to the stored data. Since the driving capability of the driven side is reduced (the driving margin is increased for the driving side), the save latch unit BLATdr can reliably hold the stored data of the slave latch unit SLAT. (Time t2). Thereafter, the power supply is cut off by the control signal SWCNT (n) (time t3). After the power is shut off, the potential of the node vssm may be given to vssx and vddx to suppress the occurrence of junction leakage.

  FIG. 18 illustrates the control timing of the return operation for the DRFF of FIG. 15 or FIG. The power cutoff control target is a power switch 10 (n) that is switch-controlled by a switch control signal SWCNT (n). The power supply control and body bias control circuit 5 releases the power cut-off state by the power switch 10 (n) at time t0. It is assumed that vddx and vssx are set to the potential of the node vssm, that is, the power supply voltage in the power cutoff state. Thereafter, at time t1, the body voltages vddx and vssx are changed to the reverse bias, and the body voltages vbp and vbn are changed to the forward bias. That is, the body bias voltage vddx is set to a reverse bias voltage higher than the power supply voltage VDD, the body bias voltage vssx is set to a reverse bias voltage lower than the ground voltage VSS, and the body bias voltage vbp is set to a forward bias voltage lower than the power supply voltage VDD. The body bias voltage vbn is set to a forward bias voltage higher than the ground voltage VSS. As a result, the driving capability of the slave latch unit SLAT decreases, and the driving capability of the save latch unit BLATdr increases. Therefore, after that, when the power supply control and body bias control circuit 5 activates the restore signal RSTR (time t2), the save latch unit BLATdr drives the storage node of the slave latch unit SLAT according to the stored data. Since the driving capability of the driven side is reduced (the driving margin is increased for the driving side), the slave latch unit SLAT can reliably hold the storage data of the save non-latching BLATdr. (Time t3). Thereafter, for example, vbp and vddx are changed to VDD, and vbn and vssx are changed to VSS (time t4).

  FIG. 19 shows another example of a data holding flip-flop (DRFF). The DRFF 17 shown in the figure has a p-channel power switch 10 (p) with respect to the DRFF 16 of FIG. 16, and the power switch PST and the return gates RGT (t), RGT ( The difference is that b) is composed of n-channel MOS transistors. When the power switch 10 (p) is turned off in the DRFF 17, the node vssm converges to the ground voltage. Also in the DRFF 17, the power supply control and body bias control circuit 5 performs the body bias control by the same power supply cutoff control as described above.

  FIG. 20 illustrates the control timing of the return operation for the DRFF of FIG. The power cutoff control target is the power switch 10 (p) that is switch-controlled by the switch control signal SWCNT (p). The power supply control and body bias control circuit 5 cancels the power cut-off state by the power switch 10 (p) at time t0. It is assumed that vddx and vssx are set to the potential of the node vddm, that is, the ground voltage in the power-off state. Thereafter, at time t1, the body voltages vddx and vssx are changed to the reverse bias, and the body voltages vbp and vbn are changed to the forward bias. That is, the body bias voltage vddx is set to a reverse bias voltage higher than the power supply voltage VDD, the body bias voltage vssx is set to a reverse bias voltage lower than the ground voltage VSS, and the body bias voltage vbp is set to a forward bias voltage lower than the power supply voltage VDD. The body bias voltage vbn is set to a forward bias voltage higher than the ground voltage VSS. As a result, the driving capability of the slave latch unit SLAT decreases, and the driving capability of the save latch unit BLATdr increases. Therefore, after that, when the power supply control and body bias control circuit 5 activates the restore signal RSTR (time t2), the save latch unit BLATdr drives the storage node of the slave latch unit SLAT according to the stored data. Since the driving capability of the driven side is reduced (the driving margin is increased for the driving side), the slave latch unit SLAT can reliably hold the storage data of the save non-latching BLATdr. (Time t3). Thereafter, for example, vbp and vddx are changed to VDD, and vbn and vssx are changed to VSS (time t4).

《Power cutoff and body bias control circuit》
FIG. 21 shows a specific example of a circuit that controls the power switch and the body bias. Here, the DRFF 16 is a control target.

  The power control and body bias control circuit 5 includes a system controller (SYSCON) 20, a power switch control circuit (VSCON) 21, and a body bias control circuit (BBCON) 23. The power switch control circuit 21 outputs a switch control signal swcnt (n) for the power switch 10 (n). The body bias control circuit 23 outputs body bias voltages vddx, vssx, vbp, vbn. Although not particularly illustrated, the body bias control circuit 23 includes a generation circuit that generates a voltage to be output as the body bias voltages vddx, vssx, vbp, and vbn, and a selection circuit that selects the voltage. The system controller 20 determines whether or not the logic circuit LOG should be in a standby state according to the operation mode of the semiconductor integrated circuit 1, and in accordance with the determination result, the signal ASM for notifying the body bias control circuit 23 of the active mode or the standby mode. A signal BBT instructing transition of the body bias state is output, and a signal OFM instructing on / off of the power switch is output to the power switch control circuit 21.

  When the standby mode is notified by the signal ASM, the body bias control circuit 22 changes the body bias voltages vddx and vssx to the forward bias voltage and the body bias voltages vbp and vbn to the reverse bias voltage as described with reference to FIG. Completion is notified by the system controller 20 with an acknowledge signal ACK. The system controller 20 notified of the completion of the operation activates the store signal STR, whereby the data held by the slave latch unit SLAT is written into the save latch unit BLATdr. Thereafter, the system controller 20 instructs the power switch control circuit 21 to shut off the power switch 10 (n) by the signal OFM and instructs the body bias control circuit 22 to change the body state. As a result, the power switch 10 (n) is cut off, and vddx and vssx are set to the power supply voltage VDD (equal to the voltage of vssm when the power is cut off). Thus, the body bias control circuit 22 completes the process for the notification of the standby mode by the signal ASM.

  When the system controller 20 determines that the standby state should be returned to the active state, the system controller 20 gives an instruction to the power switch control circuit 21 to release the shut-off state of the power switch 10 (n) by the signal OFM, and the body bias control circuit 22 Is notified of the active mode by the signal ASM. The body bias control circuit 22 notified of the active mode sets the body bias voltages vddx and vssx to the reverse bias voltage and the body bias voltages vbp and vbn to the forward bias voltage as described with reference to FIG. To notify the system controller 20. The system controller 20 notified of the completion of the operation activates the restore signal RSTR, whereby the data held in the save latch unit BLATdr is read out to the slave latch unit SLAT. Thereafter, the system controller 20 instructs the body bias control circuit 22 to transition the body state, and causes vddx and vbp to be the power supply voltage VDD and vssx and vbn to be the ground voltage VSS. Thus, the body bias control circuit 22 completes the process for the active mode notification by the signal ASM.

<Independent optimization control of body voltage>
FIG. 22 shows an example of a body bias circuit 30 that autonomously controls the body potential by using other control signals. Here, the case where it applies to DRFF14 demonstrated in FIG. 14 is shown. The body bias circuit 30 is provided in the CMOS inverters IVa and IVb and the save / return transfer gate units BTRG (S) and BTRG (R) that are controlled by the forward bias and the reverse bias with respect to the body.

  FIG. 23 shows an example of the body bias circuit 30. The body bias control circuit 30 includes an inverter 33, a first switch 31 formed of a MOS transistor MPtn, and a second switch 32 formed of a MOS transistor MNtn. The gate voltage Vd1 of the first switch 31 is set such that a parasitic diode between the source and the body in the switch 31 does not turn on when the body bias voltage becomes Vd1 + Vthp. Vthp is a threshold voltage of the first switch 31. The gate voltage Vd2 of the second switch 32 is set such that the parasitic diode between the source and the body in the switch 32 does not turn on when the body bias voltage becomes Vd2-Vthn. Vthn is a threshold voltage of the second switch 22. In this example, the first switch 31 is coupled to the body of the p-channel MOS transistor MPtn that constitutes the inverter IVb, and the voltage at the node ND1 becomes the body voltage. Similarly, the second switch 32 is coupled to the body of the n-channel MOS transistor MNtn constituting the inverter IVb, and the voltage at the node ND2 becomes the body bias voltage. The restore signal RSTR is input to the inverter 33.

  When the return mode is not designated by the low level of the restore signal RSTR, the node ND1 is set to VDD and the node ND2 is set to 0V. On the other hand, when the return mode is designated by the high level of the restore signal RSTR, the node ND1 is set to Vd1 + Vthp <VDD, and the threshold voltage of the MOS transistor MPtn is reduced, so that the MOS transistor MPtn performs the turn-on operation at high speed. And a relatively large transconductance can be obtained. Similarly, the node ND2 is set to Vd2−Vthn <VSS, and the threshold voltage of the MOS transistor MNtn is reduced. As a result, the MOS transistor MNtn can be turned on at high speed and obtain a relatively large transconductance. It becomes possible. Therefore, the drive capability of the inverter IVb is made larger than the others in the return operation. The return gate BTRG (R) is similar to this. On the contrary, the saving inverter IVa and the saving gate BTRG (S) have a driving capability larger than the others in the saving operation. Thus, the operation margin for the return operation can be automatically expanded in response to the high level of the restore signal RSTR, and the operation margin for the save operation can be automatically expanded in response to the high level of the store signal STR. Can do.

  The operating power supply of the inverter 33 may be determined in consideration of the source voltages of the p-channel MOS transistor and the n-channel MOS transistor to be controlled by the body bias control circuit 30. VDD and VSS may be employed for the inverter IVb, and VDD and vssm may be employed for the inverter IVa and the gates BTRG (R) and BTRG (S). The specific circuit configuration of the body bias circuit is not limited to this, and can be changed as appropriate.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  The function of the circuit constituted by the thin film MOS transistor can be selected as appropriate. The conductivity type of the power switch, the number of hierarchical levels of the power switch, and the like can be changed as appropriate. The semiconductor integrated circuit is not limited to a digital processing LSI represented by a microcomputer, and can be widely applied to an analog processing LSI, an analog / digital mixed LSI, and the like. The standby mode is, for example, a sleep mode in which a transition is made when the CPU executes a sleep command, an external standby mode instructed from the outside by a standby signal or register setting, a module standby mode in which whether or not an operation can be set for each module, etc. It is said. The power switches can be arranged hierarchically. The power switch may be composed of only a thick film MOS transistor, or a thin film MOS transistor may be appropriately mixed as a lower layer power switch. The lower-layer power switch is not limited to the case where it is constituted by a thin film MOS transistor, and can naturally be constituted by a thick film MOS transistor. The flip-flop is not limited to the level sense type, and may be an edge trigger type. The flip-flop may be a simple static latch that is subject to latch control by a clock.

It is a circuit diagram showing an example of a data retention type flip-flop mounted on a semiconductor integrated circuit according to the present invention. 1 is a plan view illustrating a planar configuration of a semiconductor integrated circuit according to the present invention. It is sectional drawing which illustrates the longitudinal cross-section of the SOI type MOS transistor which comprises a semiconductor integrated circuit. It is a bird's-eye view of the n channel type MOS transistor of SOI structure. FIG. 5 is a longitudinal sectional view of the MOS transistor of FIG. 4. FIG. 5 is a plan view of the MOS transistor of FIG. 4. FIG. 3 is a circuit diagram illustrating a basic circuit configuration of a power cutoff circuit and a non-power cutoff circuit in consideration of the characteristics of the SOI structure. FIG. 8 is a circuit diagram illustrating a circuit configuration of a power supply interruptable region and a power supply non-interruption region configured by bulk MOS transistors as a comparative example of FIG. 7. It is a characteristic diagram which illustrates the relationship between the body potential of a MOS transistor and a threshold voltage. It is explanatory drawing which illustrates the difference of the flip-flop employ | adopted as the logic circuit comprised by mixing the circuit which can cut off a power supply, and a power supply non-cutoff circuit. It is explanatory drawing which illustrates the possibility that a junction leakage current may be produced in the pn junction of the body and drain of an n-channel MOS transistor when the power switch on the ground voltage VSS side is cut off, and countermeasures. It is explanatory drawing which illustrates the possibility that a junction leak current may arise in the pn junction of the body of a p channel type MOS transistor, and a drain when the power supply switch by the side of the power supply voltage VDD is interrupted, and the countermeasure. It is a circuit diagram illustrating a data holding type flip-flop having a save latch unit. It is a circuit diagram illustrating a data holding type flip-flop in which a save path and a return path are separated. FIG. 5 is a circuit diagram illustrating a data holding type flip-flop in which an operation margin in a data return operation from a retracting touch unit to a slave latch unit can be greatly expanded. FIG. 16 is a circuit diagram illustrating a data holding type flip-flop in which the connection form of the static latch is changed with respect to FIG. 15. 17 is a timing chart illustrating the control timing of the save operation for the data holding flip-flop of FIG. 15 or FIG. 16. 17 is a timing chart illustrating the control timing of the return operation for the data holding flip-flop of FIG. 15 or FIG. 16. FIG. 5 is a schematic view illustrating a data holding type flip-flop having a p-channel type power switch, and the power switch and the return gate unit configured by an n-channel type MOS transistor according to the p-channel type power switch. 20 is a timing chart illustrating the control timing of the return operation for the data holding flip-flop of FIG. It is a block diagram which shows the specific example of the circuit which controls control of a power switch and body bias. It is the schematic which illustrates the data holding type flip-flop using the body bias circuit which carries out the optimization control of the body potential independently using another control signal. It is a circuit diagram which shows an example of a body bias circuit.

Explanation of symbols

1 Semiconductor integrated circuit 2 Input / output circuit (external interface circuit)
3 Digital circuit area 4 Analog circuit area 5 Power supply control and body chair control circuit 6 Power cut-off possible circuit 7 Power supply non-cut-off circuit 8 Power supply cut-off possible circuit 9 Power supply non-cut-off circuit 10, 10 (p), 10 (n) Power switch BPL silicon substrate EOX buried oxide film SOC source DRN drain BDY body FTI complete isolation region PTI partial isolation region MNtn n-channel thin film MOS transistor MPtn p-channel thin film MOS transistor MNtk n-channel thick film MOS transistor MPtk p-channel thick film MOS Transistors LOG1 to LOG5 Logic circuit DR_FF Data retention type flip-flop V_FF Normal flip-flop 12 Data retention type flip-flop MLAT Master latch unit SLATdr Slay Blatch part 13 Data holding type flip-flop MLAT Mass latch SLAT Slave latch part BLATdr Save latch part STR Store signal RSTR Restore signal BTRG Save / return transfer gate part 14 Data hold type flip-flop BTRG (S) Save transfer gate part BTRG (R) Return transfer Gate part 15 Data holding type flip-flop RGT (t), RGT (b) Return gate part SGT Saving gate part 16 Data holding type flip-flop SGT (t), SGT (b) Saving gate part 20 System controller 21 Power supply Switch control circuit 23 Body bias control circuit vbn, vbp, vddx, vssx Body bias voltage IVa, IVb Inverter 30 Body bias circuit 33 Converter 31 first switch 32 second switch

Claims (30)

On the insulating thin film of the substrate, has a plurality of circuits composed of MOS transistors having a source, a drain, a body, a gate insulating film on the body, and a gate on the gate insulating film,
Including a control circuit and a controlled circuit as part of the plurality of circuits,
The controlled circuit includes a flip-flop including a power cutoff unit that is a target of selective power shutdown by a power switch and a power non-shut-off unit that is not targeted for selective power shutdown,
The power cutoff unit is a master latch unit that can be powered off by a power switch,
The power supply non-cut-off unit is a slave latch unit in which a storage node can be selectively connected to a storage node of a master latch unit,
The slave latch unit holds the data held by the master latch unit in the power-off state of the master latch unit,
The control unit controls a body voltage of the MOS transistor constituting the slave latch unit, and the threshold voltage of the MOS transistor by the body voltage control is when the power source is not shut off than the power source shut off state of the master latch unit. A semiconductor integrated circuit that is smaller.   2. The semiconductor integrated circuit according to claim 1, wherein the control unit performs control to apply a forward bias voltage for reducing a threshold voltage to a body of the MOS transistor constituting the slave latch unit when the master latch unit is in a non-power-off state. .   The control unit performs a control to apply a forward bias voltage for reducing a threshold voltage to a body of the MOS transistor constituting the slave latch unit in a power supply non-cutoff state of the master latch unit, and in a power cutoff state of the master latch unit 2. The semiconductor integrated circuit according to claim 1, wherein control is performed to apply a reverse bias voltage for increasing a threshold voltage to a body of the MOS transistor constituting the slave latch unit.   The semiconductor integrated circuit according to claim 1, wherein the control unit performs control to apply a reverse bias voltage for increasing a threshold voltage to a body of the MOS transistor constituting the slave latch unit when the master latch unit is powered off.   2. The semiconductor integrated circuit according to claim 1, wherein the body of the MOS transistor constituting the master latch portion is biased by a power supply opposite to the power supply cutoff side power supply in a power supply cutoff state.   6. The semiconductor integrated circuit according to claim 5, wherein the body of the MOS transistor constituting the master latch portion is coupled to its own source.   2. The semiconductor integrated circuit according to claim 1, wherein a body of the MOS transistor constituting the master latch portion is floated in a power-off state.   8. The semiconductor integrated circuit according to claim 7, wherein the body of the MOS transistor constituting the master latch portion is biased by its own source voltage in a non-power-off state. On the insulating thin film of the substrate, has a plurality of circuits composed of MOS transistors having a source, a drain, a body, a gate insulating film on the body, and a gate on the gate insulating film,
Including a control circuit and a controlled circuit as part of the plurality of circuits,
The controlled circuit includes a latch unit that can be powered off by a power switch, a save latch unit that cannot be shut off by a power switch, a storage node of the latch unit, and a storage node of the save latch unit And a transfer gate portion for selectively connecting the flip-flops,
The control unit performs retraction control to retreat data held by the latch unit in the retraction latch unit when the power to the latch unit is interrupted, and retreats to the latch unit when the power supply to the latch unit is released. Performs return control to restore the data held by the latch unit,
The control unit is a semiconductor integrated circuit that applies a forward bias voltage for reducing a threshold voltage to a body of the MOS transistor constituting the save latch unit during the return control. The latch unit includes a master latch unit and a slave latch unit connected in series, and the storage node of the slave latch unit can be connected to the storage node of the save latch unit via a transfer gate unit,
The semiconductor integrated circuit according to claim 9, wherein the control unit applies a reverse bias voltage for increasing a threshold voltage to a body of the MOS transistor constituting the slave latch unit during the return control.   11. The semiconductor integrated circuit according to claim 10, wherein the control unit applies a forward bias voltage for reducing a threshold voltage to a body of the MOS transistor constituting the transfer gate unit in the return control.   12. The semiconductor integrated circuit according to claim 11, wherein the control unit applies a forward bias voltage for reducing a threshold voltage to a body of the MOS transistor constituting the slave latch unit during the save control.   The semiconductor integrated circuit according to claim 12, wherein the control unit applies a reverse bias voltage for increasing a threshold voltage to a body of the MOS transistor constituting the save latch unit in the save control.   10. The semiconductor integrated circuit according to claim 9, wherein the body of the MOS transistor constituting the latch unit is biased by a power supply on the side opposite to the power supply cutoff side power supply in a power supply cutoff state.   15. The semiconductor integrated circuit according to claim 14, wherein the body of the MOS transistor constituting the latch portion is coupled to its own source.   10. The semiconductor integrated circuit according to claim 9, wherein the body of the MOS transistor constituting the latch portion is floated in a power-off state.   17. The semiconductor integrated circuit according to claim 16, wherein the body of the MOS transistor constituting the latch portion is biased by its own source voltage in a non-power-off state. On the insulating thin film of the substrate, has a plurality of circuits composed of MOS transistors having a source, a drain, a body, a gate insulating film on the body, and a gate on the gate insulating film,
Including a control circuit and a controlled circuit as part of the plurality of circuits,
The controlled circuit includes a master latch unit and a slave latch unit that can be powered off by a power switch, a save latch unit that cannot be shut off by a power switch, a storage node of the slave latch unit, and the save latch A flip-flop comprising a transfer gate portion for selectively connecting a storage node of the portion,
The control unit performs save control for saving data held by the slave latch unit to the save latch unit when shutting off the power supply of the master latch unit and the slave latch unit, and shuts off the power supply of the master latch unit and the slave latch unit. When releasing, perform a return control to return the data held by the save latch unit to the slave latch unit,
The control unit applies a reverse bias voltage for increasing a threshold voltage to a body of the MOS transistor constituting the slave latch unit during the return control. On the insulating thin film of the substrate, has a plurality of circuits composed of MOS transistors having a source, a drain, a body, a gate insulating film on the body, and a gate on the gate insulating film,
Including a control circuit and a controlled circuit as part of the plurality of circuits,
The controlled circuit includes a latch unit that can be powered off by a power switch, a save latch unit that cannot be shut off by a power switch, a storage node of the latch unit, and a storage node of the save latch unit And a transfer gate portion for selectively connecting the flip-flops,
The control unit performs retraction control to retreat data held by the latch unit in the retraction latch unit when the power to the latch unit is interrupted, and retreats to the latch unit when the power supply to the latch unit is released. Performs return control to restore the data held by the latch unit,
The control unit applies a forward bias voltage for reducing a threshold voltage to a body of the MOS transistor capable of driving at least a storage node of the latch unit in the save latch unit during the return control. On the insulating thin film of the substrate, has a plurality of circuits composed of MOS transistors having a source, a drain, a body, a gate insulating film on the body, and a gate on the gate insulating film,
Including a control circuit and a controlled circuit as part of the plurality of circuits,
The controlled circuit includes a latch unit that can be powered off by a power switch, a save latch unit that cannot be shut off by a power switch, and a storage node of the latch unit as a storage node of the save latch unit. A flip-flop comprising: a save gate unit that selectively communicates; and a return gate unit that provides a switch output to the storage node of the latch unit using the storage node of the save latch unit as a switch control input;
The control unit performs retraction control to retreat data held by the latch unit in the retraction latch unit when the power to the latch unit is interrupted, and retreats to the latch unit when the power supply to the latch unit is released. Performs return control to restore the data held by the latch unit,
The control unit is a semiconductor integrated circuit that applies a forward bias voltage for reducing a threshold voltage to a body of the MOS transistor constituting the save latch unit during the return control. The latch unit includes a master latch unit and a slave latch unit connected in series, and the storage node of the slave latch unit can be connected to the storage node of the save latch unit via the save gate unit and the return gate unit. ,
21. The semiconductor integrated circuit according to claim 20, wherein the control unit applies a reverse bias voltage for increasing a threshold voltage to a body of the MOS transistor constituting the slave latch unit in the return control.   22. The semiconductor integrated circuit according to claim 21, wherein the control unit applies a forward bias voltage for reducing a threshold voltage to a body of the MOS transistor constituting the return gate unit during the return control.   23. The semiconductor integrated circuit according to claim 22, wherein the control unit applies a forward bias voltage for reducing a threshold voltage to a body of the MOS transistor constituting the slave latch unit during the save control.   24. The semiconductor integrated circuit according to claim 23, wherein the control unit applies a reverse bias voltage for increasing a threshold voltage to a body of the MOS transistor constituting the save latch unit during the save control.   21. The semiconductor integrated circuit according to claim 20, wherein the body of the MOS transistor constituting the latch portion is biased by a power supply opposite to the power supply cutoff side power supply in a power supply cutoff state.   26. The semiconductor integrated circuit according to claim 25, wherein the body of the MOS transistor constituting the latch portion is coupled to its own source.   21. The semiconductor integrated circuit according to claim 20, wherein the body of the MOS transistor constituting the latch portion is floated in a power-off state.   28. The semiconductor integrated circuit according to claim 27, wherein the body of the MOS transistor constituting the latch portion is biased by its own source voltage in a non-power-off state. On the insulating thin film of the substrate, has a plurality of circuits composed of MOS transistors having a source, a drain, a body, a gate insulating film on the body, and a gate on the gate insulating film,
Including a control circuit and a controlled circuit as part of the plurality of circuits,
The controlled circuit includes a master latch unit and a slave latch unit that can be powered off by a power switch, a save latch unit that cannot be shut off by a power switch, and a storage latch of the slave latch unit. A flip-flop comprising: a save gate unit that selectively communicates with a storage node of a unit; and a return gate unit that provides a switch output to the storage node of the slave latch unit with the storage node of the save latch unit as a switch control input Have
The control unit performs save control for saving data held by the slave latch unit to the save latch unit when shutting off the power supply of the master latch unit and the slave latch unit, and shuts off the power supply of the master latch unit and the slave latch unit. When releasing, perform a return control to return the data held by the save latch unit to the slave latch unit,
The control unit applies a reverse bias voltage for increasing a threshold voltage to a body of the MOS transistor constituting the slave latch unit during the return control. On the insulating thin film of the substrate, has a plurality of circuits composed of MOS transistors having a source, a drain, a body, a gate insulating film on the body, and a gate on the gate insulating film,
Including a control circuit and a controlled circuit as part of the plurality of circuits,
The controlled circuit includes a latch unit that can be powered off by a power switch, a save latch unit that cannot be shut off by a power switch, and a storage node of the latch unit as a storage node of the save latch unit. A flip-flop comprising: a save gate unit that selectively communicates; and a return gate unit that provides a switch output to the storage node of the latch unit using the storage node of the save latch unit as a switch control input;
The control unit performs retraction control to retreat data held by the latch unit in the retraction latch unit when the power to the latch unit is interrupted, and retreats to the latch unit when the power supply to the latch unit is released. Performs return control to restore the data held by the latch unit,
The control unit applies a forward bias voltage for reducing a threshold voltage to a body of the MOS transistor capable of driving at least a storage node of the latch unit in the save latch unit during the return control.

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