JP2007201030A - Electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain an electronic device in which warp of a substrate is suppressed when a chip is mounted by reducing a stress on the interface between an electronic device chip and a thin mounting substrate. <P>SOLUTION: A framelike member 5 having an elastic modulus of 10 GPa or above is stuck to the surface at the outer circumference of a thin multilayer substrate 1 mounting an electronic device chip 6, and elastic modulus of insulating resin composing the thin multilayer substrate 1 is set to 100 MPa or less. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electronic device, and in particular, warpage caused by stress when an electronic device chip such as a semiconductor integrated circuit device is mounted on a thin multilayer LSI package substrate having a thickness of 500 μm or less such as a coreless or thin core substrate. It relates to electronic devices that are characterized by a structure for preventing the occurrence of cracks, etc.In particular, it is possible to greatly reduce the stress to the interlayer connection via in the substrate, without replacing the chip and the motherboard, The present invention relates to a stack via connection technology that is connected at the shortest distance.

  A conventional LSI package substrate has a core layer with a thickness of 500 μm or more reinforced with a glass cloth at the center of the substrate in order to suppress warping due to stress generated between the LSI chip having a low thermal expansion coefficient and a high elastic modulus. It was common to use a cored substrate arranged.

  However, by reducing the distance between the LSI chip placed on the front and back of the package substrate and the decoupling capacitor that removes noise, that is, the substrate thickness, the inductance caused by the via can be reduced and the transmission speed can be further improved. For this reason, a coreless package and a multilayer stack via structure in which the core layer is removed and the substrate is formed only by the buildup layer are being developed.

However, since the substrate is thinned as described above, the following points are problematic.
First, since it is composed only of a resin having a large thermal expansion coefficient compared to a substrate with a core, the thermal expansion coefficient of the substrate itself is large, and the mismatch of the thermal expansion coefficient at the chip / substrate interface is also large. As a result, a great amount of stress is generated on the joint surface such as the underfill and the bump, which causes cracks in the fine wiring portion on the LSI surface, the underfill and the bump.

  Second, since there is no core material, substrate deformation and scaling due to dimensional changes are problematic due to the stress generated between the LSI chip and the package substrate, making it difficult to mount the LSI chip.

In order to solve these problems, various low stress / warp mounting technologies have been proposed.
For example, in order to relieve stress, it has been proposed to attach a stress relieving layer composed of a porous material to a chip via an adhesive (see, for example, Patent Document 1).

Alternatively, in order to suppress the warpage of the substrate, a normal underfill is used between the electrode terminal and the chip where stress due to thermal expansion coefficient mismatch occurs, and the surface opposite to the solder joint is made of resin via an adhesive. It has been proposed to include a thermal stress relaxation layer (see, for example, Patent Document 2).
In this case, the stress is offset by suppressing warping by arranging the resin symmetrically with respect to the chip.

  Alternatively, in order to reduce the stress applied to the semiconductor element at the time of sealing, the elastic modulus of the adhesive layer and the coating film surrounding the LSI chip is made lower than the elastic modulus of the mold resin, for example, 0.1 GPa or less. It has been proposed to absorb the distortion due to the difference in thermal expansion coefficient between the sealing resin and the LSI chip (for example, see Patent Document 3).

  Alternatively, it has also been proposed to reduce the stress by sandwiching a structure having an inclined coefficient of thermal expansion with respect to the adhesive that bonds the semiconductor chip and the package substrate (for example, see Patent Document 4).

  Alternatively, in a semiconductor device in which a semiconductor chip is internally connected by bump connection to a package substrate having a wiring circuit and an external connection portion is provided on the lower surface, a flexible layer may be provided either inside the package substrate or between the package substrate and the semiconductor chip. It has been proposed (see, for example, Patent Document 5).

Alternatively, in order to reduce the stress on the bump and improve the reliability, when the semiconductor chip is mounted on the bump, the insulating layer of the rewiring layer and the insulating layer between the vias have low thermal expansion (30 ppm / ° C.) and low elasticity ( It has also been proposed to use a material of 3 GPa) (see, for example, Patent Document 6).
JP 2000-133683 A JP-A-11-345898 JP 09-289269 A International publication pamphlet WO00 / 49652 JP 2002-289735 A Japanese Patent Laid-Open No. 2001-127095

  However, in the case of the proposal according to Patent Document 1 or Patent Document 5, there is no specific limitation on the stress, and there is a problem that the distance between the chip boards becomes large because the stress relaxation layer or the flexible layer is provided.

  Moreover, in the proposal by patent document 2, there exists a problem that the stress which generate | occur | produces in an underfill cannot be reduced, and generation | occurrence | production of a crack becomes a problem.

  The proposal in Patent Document 3 is a technique for lead frame mounting, and does not solve problems such as substrate warpage in flip chip mounting.

  Furthermore, the biggest problem is that in each of the above patent documents, it is disclosed that the underfill or sealing resin is made of a low elastic material, but the multilayer insulating material used for the package substrate is also made of low elastic properties. No mention is made, and there is a problem that no measures are shown for the problem of warping of the substrate when the substrate is a low-elasticity thin multilayer substrate.

  Accordingly, an object of the present invention is to reduce the stress at the interface between an electronic device chip such as an LSI chip and a thin mounting substrate, and to suppress substrate warpage during chip mounting.

FIG. 1 is a diagram illustrating the basic configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
Note that reference numerals 2, 3, 4, and 7 in the figure denote a pad, a solder resist, a solder bump, and an underfill, respectively.
In order to solve the above-mentioned problem, in the electronic device, the present invention attaches a frame-like member 5 having an elastic modulus of 10 GPa or more to the outer peripheral surface of the thin multilayer substrate 1 on which the electronic device chip 6 is mounted, The elastic modulus of the insulating resin constituting the thin multilayer substrate 1 is 100 MPa or less.

In this way, by setting the elastic modulus of the insulating resin constituting the thin multilayer substrate 1 such as the coreless substrate to 100 MPa or less, the elastic modulus of the material constituting the entire substrate and the joint can be lowered. When the electronic device chip 6 is mounted, the stress generated due to the thermal expansion coefficient mismatch at the interface can be greatly reduced, and the occurrence of defects such as cracks and peeling at the joint can be suppressed.
Furthermore, the stress generated between the interlayer connection vias formed in the thin multilayer substrate 1 can also be reduced, and stack via connection without via replacement is possible.

  Further, the frame member 5 having an elastic modulus of 10 GPa or more is bonded to the outer periphery of the thin multilayer substrate 1 to hold the thin multilayer substrate 1, thereby suppressing warpage deformation and dimensional change of the thin multilayer substrate 1, and the electronic device chip 6 Implementation and operation may be possible.

  In addition, when the underside of the electronic device chip 6 is sealed with the underfill 7 and molded with resin, it is desirable that the elastic modulus of the underfill material and the molding resin is also set to 100 MPa or less. Can be further reduced.

  Insulating resin, underfill material and mold resin in this case include thermoplastic elastomer or a rubber material as a base resin, a resin obtained by intermolecular crosslinking or copolymerization with an arbitrary resin, or an arbitrary resin as a base resin. Alternatively, it is desirable to use either a resin in which any of rubber materials is mixed, or a resin in which an arbitrary resin is used as a base resin and a thermoplastic elastomer or rubber material is introduced into the polymer side chain.

  For example, as the thermoplastic elastomer, any of a styrene elastomer, an olefin elastomer, a vinyl chloride elastomer, a urethane elastomer, an ester elastomer, or an amide elastomer is suitable.

  Rubber materials include nitrile rubber, hydrogenated nitrile rubber, fluorine rubber, acrylic rubber, silicone rubber, urethane rubber, ethylene propylene rubber, chloroprene rubber, chlorosulfonated polyethylene, epichlorohydrin rubber, isoprene rubber, styrene butadiene rubber, butadiene. Any of rubber, polysulfide rubber and norbornene rubber is suitable.

  The frame member 5 is preferably a metal, a composite material, an engineer plastic, or an inorganic material. For example, as a metal having an elastic modulus of 10 GPa or more, Al, Cr, Cu, Fe, Ni, Ag , Ti, W, Zn, or Mg is desirable.

  The composite material having an elastic modulus of 10 GPa or more is any of carbon fiber reinforced fiber resin impregnated material, glass fiber reinforced fiber resin impregnated material, aramid fiber reinforced fiber resin impregnated material, or silicon carbide fiber reinforced fiber resin impregnated material. Is desirable.

  As the engineer plastic having an elastic modulus of 10 GPa or more, MC nylon, polyether ether ketone, polyacetal, polyether imide, polyphenyl sulfone, or polyimide is desirable.

  In addition, as the inorganic material having an elastic modulus of 10 GPa or more, any of alumina, graphite, or silica is desirable.

  Further, the thin multilayer substrate 1 is intended for a mounting substrate having a thickness of 500 μm or less, and is typically intended for a coreless substrate. However, if the thickness is 500 μm or less, the thin multilayer substrate 1 is thin. A mounting substrate having a core material is also a target.

ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to reduce the stress between electronic device chips, such as a mounting board | substrate, and a semiconductor element, and to suppress the curvature deformation and dimensional change of a mounting board | substrate, a coreless board | substrate without a core material, etc. The electronic device chip can be surely mounted on the thin multilayer substrate.
Furthermore, it becomes possible to take a stack structure for the via, and a structure that makes the most of the merit of the coreless substrate structure.

  The present invention provides a frame having an elastic modulus of 10 GPa or more on the outer peripheral surface of a thin multilayer substrate when an electronic device chip such as an LSI chip is mounted on a thin multilayer substrate, typically a coreless substrate having a thickness of 500 μm or less. Member, for example, metal such as Al, Cr, Cu, Fe, Ni, Ag, Ti, W, Zn, Mg, carbon fiber reinforced fiber resin impregnated material, glass fiber reinforced fiber resin impregnated material, aramid fiber reinforced fiber resin impregnated Materials, or composite members such as silicon carbide fiber reinforced fiber resin impregnated materials, MC plastics such as MC nylon, polyetheretherketone, polyacetal, polyetherimide, polyphenylsulfone, polyimide, or alumina, graphite, Or a frame-shaped member made of inorganic material such as silica As an insulating resin, underfill material and mold resin having an elastic modulus of 100 MPa or less, for example, a resin obtained by intermolecular crosslinking or copolymerization with an arbitrary resin using a thermoplastic elastomer or a rubber material as a base resin, an arbitrary resin as a base resin Either a resin mixed with either a thermoplastic elastomer or a rubber material, or a resin in which an arbitrary resin is used as a base resin and a thermoplastic elastomer or a rubber material is introduced into the polymer side chain is used.

  Examples of the thermoplastic elastomer mixed in the base resin or introduced into the polymer side chain include styrene elastomers, olefin elastomers, vinyl chloride elastomers, urethane elastomers, ester elastomers, and amide elastomers. Also, as rubber materials, nitrile rubber, hydrogenated nitrile rubber, fluorine rubber, acrylic rubber, silicone rubber, urethane rubber, ethylene propylene rubber, chloroprene rubber, chlorosulfonated polyethylene, epichlorohydrin rubber, isoprene rubber, styrene butadiene rubber, Examples thereof include butadiene rubber, polysulfide rubber, and norbornene rubber.

Here, with reference to FIG.2 and FIG.6, the mounted semiconductor device of Example 1 of this invention is demonstrated.
See Figure 2
First, after the wiring 12 is formed on the support member 11, a low elastic modulus insulating resin 13 of 100 MPa or less is pasted by a vacuum lamination method.
In this case, as the low-elasticity insulating resin, TLF-Y30 (trade name manufactured by Yodogawa Paper Co., Ltd.) having a modulus of elasticity at room temperature of 10 MPa is a high-spread flat glass cloth (roving) (Asahi Fiber Glass Co., Ltd.). Product name) is used for the impregnated resin.

Next, after a via hole 14 is opened in the low elastic modulus insulating resin 13 using a CO ₂ gas laser, a Cu plating seed layer 15 is formed on the entire surface using, for example, an electroless plating solution manufactured by Rohm and Haas.

  Next, by using the plating frame 16 made of a resist, for example, FOTEC RY-3229 (trade name, manufactured by Hitachi Chemical Co., Ltd.) as a mask, the via 17 is subjected to electrolytic plating using a Cu electrolytic plating solution manufactured by Rohm and Haas, for example. At the same time, after the wiring 18 is formed, the plating frame 16 is removed.

See Figure 3
Next, unnecessary Cu plating seed layer 15 is removed from the region where via 17 and wiring 18 are not formed by etching.

  For example, by a semi-additive process in which such a process is repeated six times, a coreless seven-layer substrate including a six-stage stacked via having a via diameter of 40 μmφ and a wiring having a minimum L (line) / S (space) = 30/30 μm is formed.

See Figure 4
Finally, after the support member 11 is removed, a solder mounting pad 20 is formed on the surface of the opening patterned with a solder resist 19, for example, SR7200 (trade name, manufactured by Hitachi Chemical Co., Ltd.) on the coreless substrate surface layer. In both cases, a thin multilayer substrate 10 is completed by forming nickel / gold plating electrode pads 21 for mounting on the motherboard on the back surface of the coreless substrate.

See Figure 5
Next, a stiffener 23 having an elastic modulus of 10 GPa or more using an adhesive 22, for example, EG tape (trade name, manufactured by Arisawa Manufacturing Co., Ltd.) is used on the periphery of the surface of the completed thin multilayer substrate 10. After laminating 1 mm Cu stiffeners, they are mounted on the substrate by, for example, thermosetting at 160 ° C. for 10 minutes.
In this case, the stiffener 23 is a quadrangular frame-like member that follows the shape of the thin multilayer substrate 10.

  Next, as an underfill 32, for example, a build-up material is used for flip-chip bonding the LSI chip 30 in which bumps 31, for example, solder bumps made by Senju Metal Industry, in advance, are formed on the chip bonding portion to the pads 20 provided on the thin multilayer substrate 10. And a solid solution by pouring a solution (resin concentration 70%) of a low-elasticity insulating resin TLF-Y30 (trade name, manufactured by Yodogawa Paper Mill Co., Ltd.), which is a low-elasticity material of 100 MPa or less, in a solvent dimethylacetamide (DMAc). Thus, the mounting semiconductor device is completed.

  When a stacked via conduction reliability test was performed on the mounted semiconductor device thus manufactured as a mounting reliability evaluation, a thermal cycle test of −10 ° C. → 100 ° C., 300 cycles, no connection open was observed.

  Further, when the substrate warpage temperature dependency after chip mounting was evaluated, the warpage of the entire substrate (4 cm □) was about 100 μm, and no defects such as chip peeling and via disconnection were observed.

Next, a comparative example is shown.
In this comparative example, a via opening process using a CO ₂ gas laser was performed in exactly the same manner as in Example 1 except that GX-3 (trade name, manufactured by Ajinomoto Co., Inc.) having an elastic modulus at room temperature of 4 GPa was used as the insulating resin. Using a semi-additive process using electroless copper plating and electrolytic plating, a coreless seven-layer substrate including a six-step stacked via with a via diameter of 40 μmφ and a wiring with a minimum L / S = 30/30 μm is formed. Also, a pad was formed in exactly the same manner as in Example 1.

  Next, a Cu stiffener (1 mm thick) bonded with an adhesive was bonded to the periphery of the substrate in the same manner as in Example 1, and then an underfill material CRP-4075S3 (manufactured by Sumitomo Bakelite Co., Ltd.) having a general elastic modulus of 10 GPa as an underfill. Using a product name), a mounting semiconductor device was prototyped by heating at 150 ° C. for 30 minutes for thermosetting.

  When a stack via conduction reliability test of 300 cycles of a thermal cycle test of −10 ° C. → 100 ° C. was performed on the prototyped mounting semiconductor device in the same manner as in Example 1, an open due to stress peeling was observed. .

  Further, when the substrate warpage temperature dependency after chip mounting was evaluated, the warpage of the whole substrate (4 mm □) was about 300 μm, and chip peeling, via disconnection and the like were observed.

  As described above, in the first embodiment of the present invention, the insulating resin and the underfill constituting the coreless substrate are made of the low elastic modulus insulating resin having an elastic modulus of 100 MPa or less. While preventing peeling, the curvature of a board | substrate can be reduced significantly.

See FIG.
FIG. 6 is a visual representation of the operational effects of the first embodiment of the present invention, wherein the amount of deformation due to stress deformation is represented by the length of the arrow, and the hardness is visualized as the thickness of the arrow. It is. As shown in the drawing, both the thin multilayer substrate and the underfill are greatly reduced in elastic modulus, and this reduction in elastic modulus reduces thermal stress and suppresses peeling.

  Next, a mounted semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. 7. In the second embodiment, the LSI chip is completely different from the first embodiment except that an LSI chip is molded using a mold resin. Since it is similar, only the final mounting structure will be described.

See FIG.
FIG. 7 is a schematic cross-sectional view of the mounting semiconductor device according to the second embodiment of the present invention. As in the first embodiment, an adhesive 22 such as an EG tape (Arisawa) is formed on the periphery of the surface of the thin multilayer substrate 10. After bonding together a stiffener 23 having a modulus of elasticity of 10 GPa or more using, for example, a 1 mm thick Cu stiffener, the substrate is thermally cured, for example, at 160 ° C. for 10 minutes. Installing.
In this case, the stiffener 23 is a quadrangular frame-like member that follows the shape of the thin multilayer substrate 10.

  Next, as an underfill 32, for example, a build-up material is used for flip-chip bonding the LSI chip 30 in which bumps 31, for example, solder bumps made by Senju Metal Industry, in advance, are formed on the chip bonding portion to the pads 20 provided on the thin multilayer substrate 10. In the same manner as described above, a solution (resin concentration 70%) of a low elastic modulus insulating resin TLF-Y30 (trade name, manufactured by Yodogawa Paper Co., Ltd.), which is a low elastic material of 100 MPa or less, dissolved in a solvent dimethylacetamide (DMAc) is poured and solidified.

  Finally, a low elastic modulus insulating resin 33 having an elastic modulus of 100 MPa or less using a potting method, for example, a low elastic modulus insulating resin TLF-Y30 having a low elastic modulus of 100 MPa or less as in the case of the underfill material (Yodogawa Paper Co., Ltd.) The mounted semiconductor device of Example 2 of the present invention is completed by molding the LSI chip 30 using a solution (resin concentration 70%) in which the product name) is dissolved in the solvent dimethylacetamide (DMAc).

  In the second embodiment of the present invention, when the LSI chip is molded, the mold resin is also made of a low elastic modulus resin having an elastic modulus of 100 MPa or less, so that an increase in the stress of the entire substrate is effectively prevented. be able to.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications can be made. The description is based on the assumption that the substrate is a coreless substrate. However, the substrate is not necessarily limited to a coreless substrate, and a cored substrate having a thin layer core is also a target if the substrate is a thin multilayer substrate having a thickness of 500 μm or less. .

  In each of the above embodiments, the stiffener is a rectangular frame-shaped member. However, the stiffener does not have to be strictly a square, may be an octagon, and further does not have to be a complete annular member, but a U-shape. It may be.

  In each of the above embodiments, the stiffener is made of Cu. However, the stiffener is not limited to Cu and may be any metal having an elastic modulus of 10 GPa or more, such as Al, Cr, Fe, Ni, Ag, Ti, W, Zn, Mg, etc. may be used.

  Further, the stiffener is not limited to metal, and if the elastic modulus is 10 GPa or more, the carbon fiber reinforced fiber resin impregnated material, the glass fiber reinforced fiber resin impregnated material, the aramid fiber reinforced fiber resin impregnated material, or the carbonized material. Some may be a composite material such as a silicon fiber reinforced fiber resin impregnated material.

  Alternatively, if the elastic modulus is 10 GPa or more, engineer plastic such as MC nylon, polyether ether ketone, polyacetal, polyether imide, polyphenyl sulfone, or polyimide may be used.

  Alternatively, if the elastic modulus is 10 GPa or more, an inorganic material such as alumina, graphite, or silica may be used.

  Further, in each of the above examples, since a commercially available resin material is used as the underfill and the mold resin, the detailed composition is unknown even if the elastic modulus can be measured, but the elastic modulus may be 100 PMa. The acceptance / rejection may be determined by measuring the elastic modulus of each resin material.

  For example, if the elastic modulus of the base resin is 100 MPa or more, a thermoplastic elastomer such as a styrene elastomer, an olefin elastomer, a vinyl chloride elastomer, a urethane elastomer, an ester elastomer, or an amide elastomer is mixed with the base resin. What is necessary is just to introduce into the polymer side chain of a base resin, and to use it, reducing an elasticity modulus to 100 Mpa or less.

  Or, instead of thermoplastic elastomers, nitrile rubber, hydrogenated nitrile rubber, fluorine rubber, acrylic rubber, silicone rubber, urethane rubber, ethylene propylene rubber, chloroprene rubber, chlorosulfonated polyethylene, epichlorohydrin rubber, isoprene rubber, styrene butadiene rubber A rubber material such as butadiene rubber, polysulfide rubber, or norbornene rubber may be used by mixing or introducing it into the polymer side chain of the base resin to lower the elastic modulus to 100 MPa or less.

The detailed features of the present invention will be described again with reference to FIG. 1 again.
Again see Figure 1
(Additional remark 1) While attaching the frame-shaped member 5 whose elastic modulus is 10 GPa or more to the outer peripheral surface of the thin multilayer substrate 1 on which the electronic device chip 6 is mounted, the elastic modulus of the insulating resin constituting the thin multilayer substrate 1 is set to 100 MPa. An electronic device characterized by the following.
(Supplementary note 2) The electronic device according to supplementary note 1, wherein the electronic device chip 6 is sealed with an underfill material having an elastic modulus of 100 MPa or less and molded with a resin having an elastic modulus of 100 MPa or less.
(Additional remark 3) As said insulating resin, underfill material, and mold resin, thermoplastic elastomer or rubber material is used as a base resin, a resin obtained by intermolecular crosslinking or copolymerization with any resin, and any resin as a base resin is thermoplastic. Additional resin according to claim 2, wherein either a resin mixed with either an elastomer or a rubber material, or a resin in which a thermoplastic elastomer or a rubber material is introduced into a polymer side chain using any resin as a base resin is used. Electronic devices.
(Supplementary note 4) The electron according to supplementary note 3, wherein the thermoplastic elastomer is any one of a styrene elastomer, an olefin elastomer, a vinyl chloride elastomer, a urethane elastomer, an ester elastomer, or an amide elastomer. device.
(Appendix 5) The rubber material is nitrile rubber, hydrogenated nitrile rubber, fluorine rubber, acrylic rubber, silicone rubber, urethane rubber, ethylene propylene rubber, chloroprene rubber, chlorosulfonated polyethylene, epichlorohydrin rubber, isoprene rubber, styrene butadiene rubber. The electronic device according to appendix 3, wherein the electronic device is any one of butadiene rubber, polysulfide rubber, and norbornene rubber.
(Additional remark 6) The said frame-shaped member 5 consists of either a metal, a composite material, an engineer plastic, or an inorganic material, The electronic device of any one of Additional remark 1 thru | or Additional remark 5 characterized by the above-mentioned.
(Supplementary note 7) The electronic device according to supplementary note 6, wherein the metal having an elastic modulus of 10 GPa or more is any one of Al, Cr, Cu, Fe, Ni, Ag, Ti, W, Zn, and Mg.
(Supplementary note 8) The composite material having an elastic modulus of 10 GPa or more is a carbon fiber reinforced fiber resin impregnated material, a glass fiber reinforced fiber resin impregnated material, an aramid fiber reinforced fiber resin impregnated material, or a silicon carbide fiber reinforced fiber resin impregnated material. The electronic device according to appendix 6, wherein the electronic device is any one.
(Additional remark 9) The engineer plastic with the said elasticity modulus of 10 GPa or more is MC nylon, polyetheretherketone, polyacetal, polyetherimide, polyphenyl sulfone, or polyimide, Additional remark 6 characterized by the above-mentioned Electronic devices.
(Supplementary note 10) The electronic device according to supplementary note 6, wherein the inorganic material having an elastic modulus of 10 GPa or more is any one of alumina, graphite, and silica.
(Additional remark 11) The thickness of the said thin multilayer substrate 1 is 500 micrometers or less, The electronic device of any one of Additional remark 1 thru | or 10 characterized by the above-mentioned.

  As an application example of the present invention, an LSI chip mounting structure using a coreless substrate is typical, but an electronic device chip to be mounted is not limited to an LSI chip, but a ferroelectric material such as a light polarizing element. It can also be applied to mounting structures such as device chips and superconducting device chips, and the mounting substrate is not limited to a coreless substrate. If the overall thickness is 500 μm or less, it is also applicable to a core-containing substrate. Applicable.

It is explanatory drawing of the fundamental structure of this invention. It is explanatory drawing of the manufacturing process to the middle of the thin multilayer substrate used for Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 2 of the thin multilayer substrate used for Example 1 of this invention. It is explanatory drawing of the manufacturing process after FIG. 3 of the thin multilayer substrate used for Example 1 of this invention. It is a schematic sectional drawing of the mounting semiconductor device of Example 1 of this invention. It is explanatory drawing which showed the effect in Example 1 of this invention visually. It is a schematic sectional drawing of the mounting semiconductor device of Example 2 of this invention.

DESCRIPTION OF SYMBOLS 1 Thin multilayer substrate 2 Pad 3 Solder resist 4 Solder bump 5 Frame-like member 6 Electronic device chip 7 Underfill 10 Thin multilayer substrate 11 Support member 12 Wiring 13 Low elastic modulus insulating resin 14 Via hole 15 Cu plating seed layer 16 Plating frame 17 Via 18 Wiring 19 Solder resist 20 Pad 21 Electrode pad 22 Adhesive 23 Stiffener 30 LSI chip 31 Bump 32 Underfill 33 Low elastic modulus insulating resin

Claims (5)

A frame-like member having an elastic modulus of 10 GPa or more is bonded to the outer peripheral surface of the thin multilayer substrate on which the electronic device chip is mounted, and the elastic modulus of the insulating resin constituting the thin multilayer substrate is 100 MPa or less. Electronic devices. 2. The electronic device according to claim 1, wherein the electronic device chip is sealed with an underfill material having an elastic modulus of 100 MPa or less and an elastic modulus of 100 MPa or less, and molded with a resin having an elastic modulus of 100 MPa or less. . As the insulating resin, underfill material and mold resin, a thermoplastic elastomer or rubber material as a base resin, a resin obtained by intermolecular crosslinking or copolymerization with an arbitrary resin, and an arbitrary resin as a base resin, a thermoplastic elastomer or rubber material 3. The electronic device according to claim 2, wherein either one of the above resin or a resin in which a thermoplastic elastomer or a rubber material is introduced into the polymer side chain of any resin as a base resin is used. The electronic device according to any one of claims 1 to 3, wherein the frame-shaped member is made of any one of a metal, a composite material, an engineer plastic, and an inorganic material. 5. The electronic device according to claim 1, wherein the thin multilayer substrate has a thickness of 500 μm or less.

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