JP2007194313A - Multilayer ceramic capacitor - Google Patents

Multilayer ceramic capacitor Download PDF

Info

Publication number
JP2007194313A
JP2007194313A JP2006009556A JP2006009556A JP2007194313A JP 2007194313 A JP2007194313 A JP 2007194313A JP 2006009556 A JP2006009556 A JP 2006009556A JP 2006009556 A JP2006009556 A JP 2006009556A JP 2007194313 A JP2007194313 A JP 2007194313A
Authority
JP
Japan
Prior art keywords
element body
multilayer ceramic
pair
ceramic capacitor
external electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006009556A
Other languages
Japanese (ja)
Inventor
Satoshi Oomi
智 大参
Toshiya Kawamura
俊哉 川村
Susumu Tanii
晋 谷井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2006009556A priority Critical patent/JP2007194313A/en
Publication of JP2007194313A publication Critical patent/JP2007194313A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To reduce vibration noises due to the vibration of a multilayer ceramic capacitor which is generated by superposition of an AC voltage on a DC voltage. <P>SOLUTION: In order to realize the purpose, the multilayer ceramic capacitor is provided with a base in which dielectric layers and internal electrodes are alternately laminated, and a pair of external electrodes to which the internal electrodes are alternately connected on at least both end surfaces and the rear surface of the base. The internal electrode connected to one external electrode is provided with a first notch on at least a portion opposite to the other external electrode provided on the rear surface of the base, and the internal electrode connected to the other external electrode is provided with a second notch on at least a portion opposite to the one external electrode provided on the rear surface of the base. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、各種電子機器に用いられる積層セラミックコンデンサに関する。   The present invention relates to a multilayer ceramic capacitor used in various electronic devices.

近年、電子機器の電源回路における平滑用回路において、積層セラミックコンデンサが用いられるようになってきている。図14は、電子機器であるノート型パソコンの斜視図、図15は、同電源の回路図である。   In recent years, multilayer ceramic capacitors have been used in smoothing circuits in power supply circuits of electronic devices. FIG. 14 is a perspective view of a notebook personal computer which is an electronic device, and FIG. 15 is a circuit diagram of the power source.

図14においてノート型パソコンは、ディスプレー部51と本体部52からなり、電源はアダプタ(図示せず)、バッテリの少なくともいずれかから供給される。   In FIG. 14, the notebook computer includes a display unit 51 and a main unit 52, and power is supplied from at least one of an adapter (not shown) and a battery.

図15において、バッテリ53は、DC−DCコンバータ54、チョークコイル55を介してCPU56に電力を供給している。前記DC−DCコンバータ54の入力側には、電源平滑用として積層セラミックコンデンサ57が並列に接続され、また、前記DC−DCコンバータ54と前記CPU56の間にはデカップリングコンデンサ58が並列に接続されている。   In FIG. 15, a battery 53 supplies power to a CPU 56 via a DC-DC converter 54 and a choke coil 55. On the input side of the DC-DC converter 54, a multilayer ceramic capacitor 57 is connected in parallel for smoothing the power source, and a decoupling capacitor 58 is connected in parallel between the DC-DC converter 54 and the CPU 56. ing.

そして、前記CPU56から制御IC59に接続されており、制御IC59は、表示装置60、入出力装置61、記憶装置62とそれぞれ接続され信号をやり取りしている。   The CPU 56 is connected to a control IC 59, and the control IC 59 is connected to the display device 60, the input / output device 61, and the storage device 62 to exchange signals.

近年、ノート型パソコンにおいても省電力化のため、電源投入後の不使用時には、バッテリ53からCPU56への電力供給においてスイッチング周波数を変えずにそのインターバルを変えることで待機電力を削減する、いわゆる、スリープモードが採用されている。   In recent years, in order to save power even in notebook personal computers, when not in use after turning on the power, the standby power is reduced by changing the interval without changing the switching frequency in the power supply from the battery 53 to the CPU 56. Sleep mode is adopted.

なお、本願の発明に関連する先行技術文献情報としては、例えば、特許文献1が知られている。
特開2000−232030号公報
As prior art document information related to the invention of the present application, for example, Patent Document 1 is known.
JP 2000-23320 A

ここで上述した電源回路の積層セラミックコンデンサ57に着目すると、この積層セラミックコンデンサ57は、誘電体の材料として、主として強誘電体材料であるチタン酸バリウムが用いられている。強誘電体材料は、直流電圧が印加されている状態において交流電圧が重畳されると圧電作用を発現する。そのため、それを用いた積層セラミックコンデンサ57は、直流電圧に交流電圧が重畳されると振動を発生させる。   Focusing on the above-described multilayer ceramic capacitor 57 of the power supply circuit, the multilayer ceramic capacitor 57 mainly uses barium titanate, which is a ferroelectric material, as a dielectric material. A ferroelectric material exhibits a piezoelectric action when an AC voltage is superimposed in a state where a DC voltage is applied. Therefore, the multilayer ceramic capacitor 57 using the same generates vibration when an AC voltage is superimposed on a DC voltage.

この直流電圧に交流電圧が重畳された状態とは、上述した、いわゆる、スリープモードにおける積層セラミックコンデンサの状態である。   The state in which the AC voltage is superimposed on the DC voltage is the above-described state of the multilayer ceramic capacitor in the so-called sleep mode.

この振動は、積層セラミックコンデンサが実装されているプリント基板に伝わることでさらに大きな振動に増幅され、その結果、耳障りな振動音が発生するという問題があった。   This vibration is transmitted to the printed circuit board on which the multilayer ceramic capacitor is mounted, so that it is amplified to a larger vibration, and as a result, there is a problem that an unpleasant vibration sound is generated.

そこで、本発明は、この振動音を低減することを目的とする。   Therefore, an object of the present invention is to reduce this vibration sound.

この目的を達成するために、本発明は、誘電体と内部電極を交互に積層した素体と、この素体の少なくとも両端面および裏面に、前記内部電極が交互に接続された一対の外部電極とを備え、一方の外部電極に接続された内部電極は、前記素体の裏面に設けた他方の外部電極との少なくとも対向部に第1切欠部を設けてなるとともに前記他方の外部電極に接続された内部電極は、前記素体の裏面に設けた前記一方の外部電極との少なくとも対向部に第2切欠部を設けた構成としたものである。   In order to achieve this object, the present invention provides an element body in which dielectric bodies and internal electrodes are alternately stacked, and a pair of external electrodes in which the internal electrodes are alternately connected to at least both end faces and the back surface of the element body. The internal electrode connected to one external electrode is provided with a first notch at least at a portion facing the other external electrode provided on the back surface of the element body and connected to the other external electrode. The formed internal electrode has a configuration in which a second notch is provided at least at a portion facing the one external electrode provided on the back surface of the element body.

本発明は、第1、第2の切欠部を設けることで一対の外部電極間における内部電極の対向部面積を少なくして一対の外部電極間の誘電体の圧電効果を小さくするものである。これにより、はんだで固着される外部電極部分の振動の変位量を小さくすることができ、その結果、振動音を低減することができるという作用効果を有するものである。   In the present invention, by providing the first and second cutout portions, the area of the facing portion of the internal electrode between the pair of external electrodes is reduced, and the piezoelectric effect of the dielectric between the pair of external electrodes is reduced. As a result, the amount of vibration displacement of the external electrode portion fixed with solder can be reduced, and as a result, vibrational noise can be reduced.

以下、本発明の積層セラミックコンデンサについて一実施の形態および図面を用いて説明する。   Hereinafter, a multilayer ceramic capacitor of the present invention will be described with reference to an embodiment and drawings.

図1は、本発明の一実施の形態における積層セラミックコンデンサの斜視図、図2は、同内部電極の斜視図、図3は図1のa−a’線での断面図、図4は図1のb−b’線での断面図、図5は図1のc−c’線での断面図である。   1 is a perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention, FIG. 2 is a perspective view of the internal electrode, FIG. 3 is a cross-sectional view taken along the line aa ′ of FIG. 1, and FIG. 1 is a cross-sectional view taken along line bb ′ of FIG. 1, and FIG. 5 is a cross-sectional view taken along line cc ′ of FIG.

図1〜図5において、誘電体1と内部電極3は交互に積層され素体8を構成し、前記内部電極3は交互に一対の外部電極2に接続されている。そして、前記一対の外部電極2は、素体8の幅方向の素体8の両端面、表面、裏面に形成され積層セラミックコンデンサが構成されている。なお、本発明での幅方向とは、積層セラミックコンデンサの長手方向と前記積層方向に垂直の方向を意味する。   1 to 5, dielectrics 1 and internal electrodes 3 are alternately stacked to form an element body 8, and the internal electrodes 3 are alternately connected to a pair of external electrodes 2. The pair of external electrodes 2 are formed on both end surfaces, the front surface, and the back surface of the element body 8 in the width direction of the element body 8 to constitute a multilayer ceramic capacitor. In the present invention, the width direction means a direction perpendicular to the longitudinal direction of the multilayer ceramic capacitor and the lamination direction.

この一対の外部電極2は、少なくとも素体8の両端面、裏面に形成されていればよく、必要に応じて素体8の表面にも設けることができる。この場合、プリント基板に実装する際表裏を区別する必要がなくなるという利点がある。   The pair of external electrodes 2 only need to be formed on at least both end surfaces and the back surface of the element body 8, and can also be provided on the surface of the element body 8 as necessary. In this case, there is an advantage that it is not necessary to distinguish between the front and the back when mounting on a printed circuit board.

図2に示すように、一対の外部電極2に接続された一組の内部電極3には、素体8の裏面に設けた他方の外部電極2との少なくとも対向部に第1切欠部4を設けており、同様に、他方の外部電極2に接続された内部電極3にも、素体8の裏面に設けた前記一方の外部電極2との少なくとも対向部に第2切欠部5を設けている。それ故、図3に示すa−a’線での断面図では、内部電極3が対向していない構成になっている。   As shown in FIG. 2, the set of internal electrodes 3 connected to the pair of external electrodes 2 has a first notch 4 at least at a portion facing the other external electrode 2 provided on the back surface of the element body 8. Similarly, the internal electrode 3 connected to the other external electrode 2 is also provided with a second notch 5 at least at a portion facing the one external electrode 2 provided on the back surface of the element body 8. Yes. Therefore, in the cross-sectional view taken along line a-a ′ shown in FIG. 3, the internal electrodes 3 are not opposed to each other.

一方、図5に示すように、外部電極2間でない部位、例えば、図1のc−c’線の断面図では内部電極3が対向する構成になっている。   On the other hand, as shown in FIG. 5, the internal electrode 3 is opposed to a portion not between the external electrodes 2, for example, in a cross-sectional view taken along the line c-c ′ in FIG. 1.

このように第1、第2の切欠部4、5を内部電極3の所定の位置に設けることで一対の外部電極2間における内部電極3の対向部面積を少なくして一対の外部電極2間の誘電体1の圧電効果を小さくすることができる。これにより、はんだで固着される外部電極部分の振動の変位量を小さくすることができ、その結果、振動音を低減することができるという作用効果を有する。   Thus, by providing the first and second cutout portions 4 and 5 at predetermined positions of the internal electrode 3, the area of the opposing portion of the internal electrode 3 between the pair of external electrodes 2 can be reduced, and the space between the pair of external electrodes 2. The piezoelectric effect of the dielectric 1 can be reduced. Thereby, the amount of vibration displacement of the external electrode portion fixed with solder can be reduced, and as a result, there is an effect that vibration noise can be reduced.

上記第1、第2の切欠部4、5は、図3に示したように、外部電極2間における内部電極3が全く対向しないように設定することが最も振動音の低減に効果があるが、全く対向しないという設定までしなくても振動音の低減効果は認められる。   As shown in FIG. 3, the first and second cutouts 4 and 5 are most effective in reducing vibration noise when the internal electrodes 3 are not opposed to each other between the external electrodes 2. Even if the setting is not made so that they do not face each other, the effect of reducing the vibration noise is recognized.

図6(a)は、内部電極の斜視図、図6(b)、(c)はそれぞれ同上面図であるが、図6に示すように、外部電極2間における一組の内部電極3が対向する面積(図6A、すなわち、上面から見て一組の内部電極3が重なる面積)を外部電極2間における一組の内部電極3の投影面積(図6B、すなわち、上面から見た外部電極2間の一組の内部電極3の総面積)の2/3以下になるように第1、第2切欠部を設定することにより4dbの音圧低下が確認できた。   6 (a) is a perspective view of the internal electrodes, and FIGS. 6 (b) and 6 (c) are the same top views, respectively. As shown in FIG. The opposing area (FIG. 6A, ie, the area where the set of internal electrodes 3 overlaps when viewed from above) is the projected area of the set of internal electrodes 3 between the external electrodes 2 (FIG. 6B, ie, external electrodes when viewed from above) By setting the first and second notches to be 2/3 or less of the total area of the pair of internal electrodes 3 between the two, a sound pressure drop of 4 db could be confirmed.

一般的に、人間の耳では音圧が3db違えば明らかに差を感じることができるものであるが、それ以上の4dbの音圧低下は人間の耳で明らかに振動音が低下したと認識できるレベルの値である。   In general, the difference in sound pressure can be clearly felt in the human ear if the sound pressure is different by 3 db. However, if the sound pressure is further reduced by 4 db, it can be recognized that the vibration sound is clearly reduced in the human ear. Level value.

また、さらなる振動音の低下が必要な場合は、外部電極間における一組の内部電極が対向する面積を外部電極間における一組の内部電極の投影面積の1/2以下になるように第1、第2切欠部を設定すればよい。この構成によれば約6dbの音圧低下が確認でき、さらなる振動音の低下を実現することができる。   When further reduction in vibration noise is required, the first area is set so that the area of the pair of internal electrodes facing each other between the external electrodes is equal to or less than ½ of the projected area of the pair of internal electrodes between the external electrodes. What is necessary is just to set a 2nd notch part. According to this configuration, a sound pressure reduction of about 6 db can be confirmed, and a further reduction in vibration sound can be realized.

さて、次に図7を用いて、特に、素体の裏面に形成する一対の外部電極(以下、一対の裏面電極と記す)について説明する。以下に説明する一対の裏面電極の構成を上述した内部電極の構成と組み合わせることで、振動音をより低減することができる。   Now, a pair of external electrodes (hereinafter referred to as a pair of back electrodes) formed on the back surface of the element body will be described with reference to FIG. By combining the configuration of the pair of back electrodes described below with the configuration of the internal electrodes described above, vibration noise can be further reduced.

図7(a)は一実施の形態における積層セラミックコンデンサの斜視図であり、図7(b)は同裏面図である。   Fig.7 (a) is a perspective view of the multilayer ceramic capacitor in one Embodiment, FIG.7 (b) is the same rear view.

一対の裏面電極12は、積層セラミックコンデンサの振動をプリント基板に伝搬させる部位である。したがって、この振動の伝搬を抑制することで振動音を抑制することができるが、その一方で、この部位は積層セラミックコンデンサとプリント基板との接続を担う部位でもある。そのため、一対の裏面電極に関してこの両方の観点、すなわち、振動伝搬の抑制と接続強度の確保という両面から考える必要がある。   The pair of backside electrodes 12 are parts that propagate the vibration of the multilayer ceramic capacitor to the printed circuit board. Therefore, vibration noise can be suppressed by suppressing propagation of this vibration, but this part is also a part responsible for connection between the multilayer ceramic capacitor and the printed board. Therefore, it is necessary to consider both aspects of the pair of back electrodes, that is, from the viewpoint of suppressing vibration propagation and ensuring connection strength.

図7は、一対の裏面電極12の形状を素体8の幅方向の端部に向かって電極幅が狭くなる形状にしたものである。つまり、一対の裏面電極12の素体8端部の辺の長さをa、一対の裏面電極12が対向する辺の長さをbとした場合、a<bという関係になるように構成するものである。この構成によれば、振動の抑制をできるだけ阻害せずに接合強度を向上させることができる。   In FIG. 7, the pair of back surface electrodes 12 have a shape in which the electrode width becomes narrower toward the end in the width direction of the element body 8. In other words, when the length of the side of the pair of back electrode 12 at the end of the element body 8 is a and the length of the side facing the pair of back electrodes 12 is b, the relationship is a <b. Is. According to this configuration, the bonding strength can be improved without inhibiting the suppression of vibration as much as possible.

すなわち、素体の裏面の幅方向に裏面電極を設けているので振動が抑制できるとともに、一対の裏面電極の対向辺の長さを対向方向に増加させている(つまり、a<bという関係にしている)ので、電極幅を変えない形状のものと比較して接続強度も向上させることができる。この対向辺の長さを対向方向に増加させるのは振動の抑制をできるだけ阻害しないようにするためである。   That is, since the back surface electrode is provided in the width direction of the back surface of the element body, vibration can be suppressed and the length of the opposing sides of the pair of back surface electrodes is increased in the facing direction (that is, the relationship of a <b). Therefore, the connection strength can be improved as compared with a shape that does not change the electrode width. The reason for increasing the length of the opposing side in the opposing direction is to prevent the suppression of vibration as much as possible.

次に、図8(a)は一実施の形態における積層セラミックコンデンサの斜視図、図8(b)は同裏面図である。図8に示すように、一対の外部電極2を設ける素体8の両端面に凹部28を設け、少なくともこの凹部28に一対の外部電極2を設けたものであり、このように凹部28を設けることで一対の外部電極2の面積を増やし、これによりプリント基板との固着強度を向上させることができる。また、このような構成にすることにより内部電極と外部電極との接触面積が増加するのでESRを低減することができるとともに接続不良による容量低下を抑制することもできる。   Next, FIG. 8A is a perspective view of the multilayer ceramic capacitor in one embodiment, and FIG. 8B is a rear view thereof. As shown in FIG. 8, recesses 28 are provided on both end faces of the element body 8 on which the pair of external electrodes 2 are provided, and at least the pair of external electrodes 2 is provided on the recesses 28. Thus, the recesses 28 are provided in this way. As a result, the area of the pair of external electrodes 2 can be increased, thereby improving the fixing strength with the printed circuit board. Further, with such a configuration, the contact area between the internal electrode and the external electrode is increased, so that ESR can be reduced and a decrease in capacity due to poor connection can be suppressed.

次に、図9(a)は一実施の形態における積層セラミックコンデンサの斜視図、図9(b)は同裏面図である。図9に示すように、素体8に設けた一対の裏面電極12間に凸部29を設けたものであり、これにより積層セラミックコンデンサの周端部をプリント基板から離すことができ、これにより積層セラミックコンデンサの振動をプリント基板に伝えにくくすることができ、その結果、振動音を低減することができる。また、一対の裏面電極12間に凸部29を設けることで短絡の防止という作用効果も有する。   Next, FIG. 9A is a perspective view of the multilayer ceramic capacitor in one embodiment, and FIG. 9B is a rear view thereof. As shown in FIG. 9, a convex portion 29 is provided between a pair of backside electrodes 12 provided on the element body 8, whereby the peripheral end portion of the multilayer ceramic capacitor can be separated from the printed circuit board. The vibration of the multilayer ceramic capacitor can be made difficult to be transmitted to the printed circuit board, and as a result, vibration noise can be reduced. Further, providing the convex portion 29 between the pair of back surface electrodes 12 also has an effect of preventing a short circuit.

ここで、凸部29の高さをt1、素体8の長手方向の長さをLとしたとき1/8100×L2<t1になるように凸部29を設定することで、特に、プリント基板のたわみに対して剥離しにくい積層セラミックコンデンサとすることができる。 Here, when the height of the convex portion 29 is t1, and the length in the longitudinal direction of the element body 8 is L, the convex portion 29 is set so that 1/8100 × L 2 <t1. A multilayer ceramic capacitor that does not easily peel off from the deflection of the substrate can be obtained.

以下、図10を用いて説明する。図10(a)は積層セラミックコンデンサの裏面図、(b)同側面図、(c)積層セラミックコンデンサを実装したプリント基板をたわませた側面図である。   Hereinafter, a description will be given using FIG. FIG. 10A is a back view of the multilayer ceramic capacitor, FIG. 10B is a side view thereof, and FIG. 10C is a side view of the printed circuit board on which the multilayer ceramic capacitor is mounted.

プリント基板のたわみ量はIEC規格においてスパン90mmでたわみ量1mmが規格化されている。したがって、仮に、プリント基板のたわみ量が最大量であったとしても積層セラミックコンデンサの周縁部がプリント基板に触れなければはんだ接合部に引きはがし方向の力が発生せず、結果、剥離しにくいということになる。   The deflection amount of the printed circuit board is standardized by the IEC standard with a span of 90 mm and a deflection amount of 1 mm. Therefore, even if the amount of deflection of the printed circuit board is the maximum amount, if the peripheral edge of the multilayer ceramic capacitor does not touch the printed circuit board, no force in the peeling direction is generated at the solder joint, and as a result, it is difficult to peel off. It will be.

プリント基板11のたわみ量が最大量のときの必要な凸部29の高さを以下に求める。図10(c)に示すようにたわんだプリント基板11は放物線で近似可能となるので、この放物曲線は(数1)で表される。   The required height of the convex portion 29 when the amount of deflection of the printed circuit board 11 is the maximum amount is obtained below. Since the bent printed board 11 can be approximated by a parabola as shown in FIG. 10C, this parabolic curve is expressed by (Equation 1).

Figure 2007194313
Figure 2007194313

上記IEC規格においてXは45、Yは1であるからこれによりAは1/2025となる。ここで、積層セラミックコンデンサの長手方向の長さをL、凸部29の高さをt1とするとt1は(数2)を満たせば、積層セラミックコンデンサの周縁部がプリント基板11に触れないことになる。   In the IEC standard, X is 45 and Y is 1, so A becomes 1/2025. Here, assuming that the length of the multilayer ceramic capacitor in the longitudinal direction is L and the height of the convex portion 29 is t1, if t1 satisfies (Equation 2), the peripheral portion of the multilayer ceramic capacitor does not touch the printed circuit board 11. Become.

Figure 2007194313
Figure 2007194313

そして、(数2)から(数3)が導出される。   Then, (Equation 3) is derived from (Equation 2).

Figure 2007194313
Figure 2007194313

例えば、3216サイズの積層セラミックコンデンサの場合、Lは3.2mmであるからt1は、約1.246μmを超える値になる。したがって、マージンを考慮して凸部29の高さ2μmに設定すれば、積層セラミックコンデンサの周縁部がプリント基板11に触れることはないため、はんだ接合部に引きはがし方向の力が発生せず、その結果、剥離しにくいという作用効果を有する。   For example, in the case of a 3216 size multilayer ceramic capacitor, since L is 3.2 mm, t1 is a value exceeding about 1.246 μm. Therefore, if the height of the convex portion 29 is set to 2 μm in consideration of the margin, the peripheral portion of the multilayer ceramic capacitor does not touch the printed circuit board 11, so that no force in the peeling direction is generated at the solder joint, As a result, it has the effect of being difficult to peel off.

この凸部29の材料としては、素体8と同じ材料を用いることもできるし、シリコーン樹脂、ゴム等の弾性体を用いることも可能である。   As the material of the convex portion 29, the same material as that of the element body 8 can be used, or an elastic body such as silicone resin or rubber can be used.

また、弾性体を積層セラミックコンデンサとプリント基板の間に介在させることも振動音を低減するために有効である。図11(a)は一実施の形態における積層セラミックコンデンサの斜視図、図11(b)は同裏面図である。図11に示すように、積層セラミックコンデンサの素体8の裏面端部に弾性体30を設け、この弾性体30を緩衝材として積層セラミックコンデンサ10とプリント基板11の間に介在させて振動音を低減させるものである。上述した弾性体の他、緩衝材が入った両面テープも用いることができる。   In addition, interposing an elastic body between the multilayer ceramic capacitor and the printed board is also effective for reducing vibration noise. FIG. 11A is a perspective view of the multilayer ceramic capacitor in one embodiment, and FIG. As shown in FIG. 11, an elastic body 30 is provided at the back end of the multilayer ceramic capacitor element body 8, and this elastic body 30 is interposed between the multilayer ceramic capacitor 10 and the printed circuit board 11 as a cushioning material to generate vibration noise. It is to reduce. In addition to the elastic body described above, a double-sided tape containing a cushioning material can also be used.

また、上述した凸部29に代わり、外部電極2、特に、裏面電極12自体を上記凸部29と同様の役割を持たせることも可能である。以下、図12を用いて説明する。   Further, instead of the above-described convex portion 29, the external electrode 2, in particular, the back electrode 12 itself can have the same role as the convex portion 29. Hereinafter, a description will be given using FIG.

図12(a)は一実施の形態における積層セラミックコンデンサの斜視図、図12(b)は同裏面図、図12(c)は同側面図である。   12A is a perspective view of the multilayer ceramic capacitor according to the embodiment, FIG. 12B is a back view thereof, and FIG. 12C is a side view thereof.

図12に示すように、素体8に設けた一対の裏面電極12の厚み(上記凸部29の高さと同様)をt2、素体8の長手方向の長さをLとしたとき1/8100×L2<t2とすることにより、上述した理由と同様の理由から、プリント基板11がたわんだとしても積層セラミックコンデンサの周縁部がプリント基板11に触れることはない。そのため、はんだ接合部に引きはがし方向の力が発生せず、その結果、剥離しにくいという作用効果を有する。 As shown in FIG. 12, when the thickness of the pair of backside electrodes 12 provided on the element body 8 (similar to the height of the convex portion 29) is t2, and the length in the longitudinal direction of the element body 8 is L, 1/8100. By setting × L 2 <t2, the peripheral portion of the multilayer ceramic capacitor does not touch the printed circuit board 11 even if the printed circuit board 11 is bent for the same reason as described above. For this reason, a force in the peeling direction is not generated at the solder joint, and as a result, there is an effect that it is difficult to peel off.

また、これにより積層セラミックコンデンサの周縁部をプリント基板11から離すことができるので振動を伝えにくくすることができ、その結果、振動音を低減することができる。   Moreover, since the peripheral part of a multilayer ceramic capacitor can be separated from the printed circuit board 11 by this, it can make it difficult to convey a vibration and, as a result, a vibration sound can be reduced.

次に、図13(a)は、一実施の形態における積層セラミックコンデンサの斜視図、図13(b)は同裏面図である。図13に示すように、少なくとも素体8に設けた一対の裏面電極32は導電性樹脂からなり、その導電性樹脂は、エポキシ系樹脂、フェノール系樹脂から選ばれる樹脂を含む構成とするものである。これらの材料を外部電極2、特に、裏面電極32に用いることによりプリント基板11に対するクッション作用を有するので積層セラミックコンデンサの振動をプリント基板に伝えにくくすることができ、その結果、振動音を抑制することができる。   Next, FIG. 13A is a perspective view of the multilayer ceramic capacitor in one embodiment, and FIG. 13B is a back view of the same. As shown in FIG. 13, at least a pair of backside electrodes 32 provided on the element body 8 is made of a conductive resin, and the conductive resin includes a resin selected from an epoxy resin and a phenol resin. is there. By using these materials for the external electrode 2, particularly the back electrode 32, it has a cushioning effect on the printed circuit board 11, so that the vibration of the multilayer ceramic capacitor can be made difficult to be transmitted to the printed circuit board, thereby suppressing vibration noise. be able to.

また、図示はしないが、積層セラミックコンデンサの振動の節を接着剤にてプリント基板に固定する方法も有効である。振動の節を利用するのでその接着によるプリント基板への振動の伝搬は大幅に抑制される。例えば、一対の裏面電極間に節がある場合はそこに接着剤を設ければよいし、その場合、接着剤を上述した凸部29にすることにより凸部29と同様の作用効果も得ることができる。   Although not shown, a method of fixing the vibration node of the multilayer ceramic capacitor to the printed circuit board with an adhesive is also effective. Since the vibration node is used, the propagation of vibration to the printed circuit board due to the adhesion is greatly suppressed. For example, if there is a node between the pair of back electrodes, an adhesive may be provided there, and in that case, the same effect as the convex 29 can be obtained by using the convex 29 as the adhesive. Can do.

なお、上述した実施の形態においては、一対の外部電極を素体の幅方向の少なくとも両端面および裏面に設けた構成を例に説明したが、本発明は、従来のような、素体の長手方向の両端部に一対の外部電極を設ける構成においても同様の作用効果を有するものである。   In the above-described embodiment, the configuration in which the pair of external electrodes is provided on at least both end surfaces and the back surface in the width direction of the element body has been described as an example. Even in a configuration in which a pair of external electrodes are provided at both ends in the direction, the same effect is obtained.

本発明は、前記素体の裏面に設けた他方の外部電極との少なくとも対向部に第1切欠部を設けてなるとともに前記他方の外部電極に接続された内部電極は、前記素体の裏面に設けた前記一方の外部電極との少なくとも対向部に第2切欠部を設けるという特徴を有し、これにより直流電圧に交流電圧が重畳されたときに発生していた振動音を低減することができるという作用効果を有し、各種電子機器に有用である。   According to the present invention, a first notch is provided at least in a portion facing the other external electrode provided on the back surface of the element body, and an internal electrode connected to the other external electrode is provided on the back surface of the element body. The second cutout portion is provided at least in a portion facing the one external electrode provided, and thereby vibration noise generated when the AC voltage is superimposed on the DC voltage can be reduced. It is useful for various electronic devices.

本発明の一実施の形態における積層セラミックコンデンサの斜視図The perspective view of the multilayer ceramic capacitor in one embodiment of the present invention 同内部電極の斜視図Perspective view of the internal electrode 図1のa−a’線での断面図Sectional drawing in the a-a 'line of FIG. 図1のb−b’線での断面図Sectional view taken along line b-b 'in FIG. 図1のc−c’線での断面図Sectional view taken along line c-c 'in FIG. (a)は内部電極の斜視図、(b)、(c)は同上面図(A) is a perspective view of an internal electrode, (b) and (c) are top views of the same. (a)は一実施の形態における積層セラミックコンデンサの斜視図、(b)は同裏面図(A) is a perspective view of the multilayer ceramic capacitor in one embodiment, (b) is the back view of the same (a)は一実施の形態における積層セラミックコンデンサの斜視図、(b)は同裏面図(A) is a perspective view of the multilayer ceramic capacitor in one embodiment, (b) is the back view of the same (a)は一実施の形態における積層セラミックコンデンサの斜視図、(b)は同裏面図(A) is a perspective view of the multilayer ceramic capacitor in one embodiment, (b) is the back view of the same (a)は一実施の形態における積層セラミックコンデンサの裏面図、(b)は同側面図、(c)は積層セラミックコンデンサを実装したプリント基板の側面図(A) is the back view of the multilayer ceramic capacitor in one Embodiment, (b) is the side view, (c) is the side view of the printed circuit board which mounted the multilayer ceramic capacitor (a)は一実施の形態における積層セラミックコンデンサの斜視図、(b)は同裏面図(A) is a perspective view of the multilayer ceramic capacitor in one embodiment, (b) is the back view of the same (a)は一実施の形態における積層セラミックコンデンサの斜視図、(b)は同裏面図、(c)は同側面図(A) is the perspective view of the multilayer ceramic capacitor in one Embodiment, (b) is the back view, (c) is the side view (a)は一実施の形態における積層セラミックコンデンサの斜視図、(b)は同裏面図(A) is a perspective view of the multilayer ceramic capacitor in one embodiment, (b) is the back view of the same ノート型パソコンの斜視図Perspective view of notebook computer 同電源の回路図Circuit diagram of the same power supply

符号の説明Explanation of symbols

1 誘電体
2 外部電極
3 内部電極
4 第1切欠部
5 第2切欠部
8 素体
10 積層セラミックコンデンサ
12 裏面電極
28 凹部
29 凸部
30 弾性体
32 裏面電極
DESCRIPTION OF SYMBOLS 1 Dielectric 2 External electrode 3 Internal electrode 4 1st notch part 5 2nd notch part 8 Element body 10 Multilayer ceramic capacitor 12 Back surface electrode 28 Recess 29 Projection 30 Elastic body 32 Back surface electrode

Claims (11)

誘電体と内部電極を交互に積層した素体と、この素体の少なくとも両端面および裏面に、前記内部電極が交互に接続された一対の外部電極とを備え、一方の外部電極に接続された内部電極は、前記素体の裏面に設けた他方の外部電極との少なくとも対向部に第1切欠部を設けてなるとともに前記他方の外部電極に接続された内部電極は、前記素体の裏面に設けた前記一方の外部電極との少なくとも対向部に第2切欠部を設けてなる積層セラミックコンデンサ。 An element body in which dielectric bodies and internal electrodes are alternately stacked, and a pair of external electrodes in which the internal electrodes are alternately connected to at least both end faces and the back surface of the element body are connected to one external electrode. The internal electrode is provided with a first cutout at least in a portion facing the other external electrode provided on the back surface of the element body, and the internal electrode connected to the other external electrode is provided on the back surface of the element body. A multilayer ceramic capacitor comprising a second cutout at least at a portion facing the one external electrode provided. 第1切欠部を素体の裏面に設けた他方の外部電極との対向部から一方の外部電極の方向に延設するとともに第2切欠部を素体の裏面に設けた一方の外部電極との対向部から他方の外部電極の方向に延設することにより、
前記一対の外部電極間における少なくとも一組の内部電極の対向部面積は、
前記一対の外部電極間における前記一組の内部電極の投影面積の2/3以下とした請求項1記載の積層セラミックコンデンサ。
The first cutout portion extends from the facing portion of the other external electrode provided on the back surface of the element body in the direction of the one external electrode, and the second cutout portion is provided with one external electrode provided on the back surface of the element body. By extending in the direction of the other external electrode from the facing part,
The opposing area of at least one set of internal electrodes between the pair of external electrodes is:
The multilayer ceramic capacitor according to claim 1, wherein the projected area of the pair of internal electrodes between the pair of external electrodes is 2/3 or less.
第1切欠部を素体の裏面に設けた他方の外部電極との対向部から一方の外部電極の方向に延設するとともに第2切欠部を素体の裏面に設けた一方の外部電極との対向部から他方の外部電極の方向に延設することにより、
前記一対の外部電極間における少なくとも一組の内部電極の対向部面積は、
前記一対の外部電極間における前記一組の内部電極の投影面積の1/2以下とした請求項1記載の積層セラミックコンデンサ。
The first cutout portion extends from the facing portion of the other external electrode provided on the back surface of the element body in the direction of the one external electrode, and the second cutout portion is provided with one external electrode provided on the back surface of the element body. By extending in the direction of the other external electrode from the facing part,
The opposing area of at least one set of internal electrodes between the pair of external electrodes is:
The multilayer ceramic capacitor according to claim 1, wherein the projected area of the set of internal electrodes between the pair of external electrodes is ½ or less.
第1切欠部を素体の裏面に設けた他方の外部電極との対向部から一方の外部電極の方向に延設するとともに第2切欠部を素体の裏面に設けた一方の外部電極との対向部から他方の外部電極の方向に延設することにより、
前記一対の外部電極間における少なくとも一組の内部電極を非対向とした請求項1記載の積層セラミックコンデンサ。
The first cutout portion extends from the facing portion of the other external electrode provided on the back surface of the element body in the direction of the one external electrode, and the second cutout portion is provided with one external electrode provided on the back surface of the element body. By extending in the direction of the other external electrode from the facing part,
The multilayer ceramic capacitor according to claim 1, wherein at least one pair of internal electrodes between the pair of external electrodes is not opposed.
一対の外部電極は、素体の幅方向の少なくとも両端面および裏面に設けた請求項1記載の積層セラミックコンデンサ。 The multilayer ceramic capacitor according to claim 1, wherein the pair of external electrodes are provided on at least both end surfaces and the back surface in the width direction of the element body. 素体の裏面に設けた一対の外部電極の形状は、素体の幅方向の端部に向かって前記外部電極の幅が狭くなる形状である請求項1記載の積層セラミックコンデンサ。 2. The multilayer ceramic capacitor according to claim 1, wherein the pair of external electrodes provided on the back surface of the element body has a shape in which the width of the external electrode becomes narrower toward an end portion in the width direction of the element body. 一対の外部電極を設ける素体の両端面に凹部を設け少なくともこの凹部に一対の外部電極を設けた請求項1記載の積層セラミックコンデンサ。 2. The multilayer ceramic capacitor according to claim 1, wherein recesses are provided on both end faces of the element body on which the pair of external electrodes are provided, and at least a pair of external electrodes are provided in the recesses. 素体の裏面に設けた一対の外部電極間に凸部を設けた請求項1記載の積層セラミックコンデンサ。 The multilayer ceramic capacitor according to claim 1, wherein a convex portion is provided between a pair of external electrodes provided on the back surface of the element body. 凸部は、凸部の高さをt1、素体の長手方向の長さをLとしたとき1/8100×L2<t1である請求項8記載の積層セラミックコンデンサ。 9. The multilayer ceramic capacitor according to claim 8, wherein the height of the convex portion is 1/8100 × L 2 <t1 where t1 is the height of the convex portion and L is the length of the element body in the longitudinal direction. 素体の裏面に設けた一対の外部電極は、外部電極の厚みをt2、素体の長手方向の長さをLとしたとき1/8100×L2<t2である請求項1記載の積層セラミックコンデンサ。 2. The multilayer ceramic according to claim 1, wherein the pair of external electrodes provided on the back surface of the element body is 1/8100 × L 2 <t 2 where t 2 is the thickness of the external electrode and L is the length in the longitudinal direction of the element body. Capacitor. 少なくとも素体の裏面に設けた一対の外部電極は導電性樹脂からなり、その導電性樹脂は、エポキシ系樹脂、フェノール系樹脂から選ばれる樹脂を含む請求項1記載の積層セラミックコンデンサ。 The multilayer ceramic capacitor according to claim 1, wherein at least a pair of external electrodes provided on the back surface of the element body is made of a conductive resin, and the conductive resin includes a resin selected from an epoxy resin and a phenol resin.
JP2006009556A 2006-01-18 2006-01-18 Multilayer ceramic capacitor Pending JP2007194313A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006009556A JP2007194313A (en) 2006-01-18 2006-01-18 Multilayer ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006009556A JP2007194313A (en) 2006-01-18 2006-01-18 Multilayer ceramic capacitor

Publications (1)

Publication Number Publication Date
JP2007194313A true JP2007194313A (en) 2007-08-02

Family

ID=38449783

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006009556A Pending JP2007194313A (en) 2006-01-18 2006-01-18 Multilayer ceramic capacitor

Country Status (1)

Country Link
JP (1) JP2007194313A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009038187A (en) * 2007-08-01 2009-02-19 Tdk Corp Chip type electronic component and manufacturing method thereof
CN104240946A (en) * 2013-06-14 2014-12-24 三星电机株式会社 Multilayer ceramic capacitor and board having the same mounted thereon
US20150022937A1 (en) * 2013-07-18 2015-01-22 Samsung Electro-Mechanics Co., Ltd. Composite electronic component and board having the same
JP2015019045A (en) * 2013-07-15 2015-01-29 サムソン エレクトロ−メカニックス カンパニーリミテッド. Array type multilayer ceramic electronic component and mounting substrate thereof
WO2015098990A1 (en) * 2013-12-24 2015-07-02 京セラ株式会社 Laminated electronic component and structure for mounting same
KR101548769B1 (en) 2011-04-29 2015-09-11 삼성전기주식회사 Multi-layered capacitor and manufacturing method thereof
CN111048310A (en) * 2018-10-11 2020-04-21 株式会社村田制作所 Electronic component

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009038187A (en) * 2007-08-01 2009-02-19 Tdk Corp Chip type electronic component and manufacturing method thereof
KR101548769B1 (en) 2011-04-29 2015-09-11 삼성전기주식회사 Multi-layered capacitor and manufacturing method thereof
CN108288544A (en) * 2013-06-14 2018-07-17 三星电机株式会社 Multilayer ceramic capacitor and the plate for being equipped with the multilayer ceramic capacitor
EP2822008A3 (en) * 2013-06-14 2015-05-06 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor with improves sizes and board having the same mounted thereon
US9384892B2 (en) 2013-06-14 2016-07-05 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and board having the same mounted thereon
CN108288544B (en) * 2013-06-14 2020-02-21 三星电机株式会社 Multilayer ceramic capacitor and board mounted with the same
US9502177B2 (en) 2013-06-14 2016-11-22 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and board having the same mounted thereon
CN104240946A (en) * 2013-06-14 2014-12-24 三星电机株式会社 Multilayer ceramic capacitor and board having the same mounted thereon
JP2015019045A (en) * 2013-07-15 2015-01-29 サムソン エレクトロ−メカニックス カンパニーリミテッド. Array type multilayer ceramic electronic component and mounting substrate thereof
KR102064013B1 (en) * 2013-07-18 2020-01-08 삼성전기주식회사 Composite electronic component and board for mounting the same
KR20150010181A (en) * 2013-07-18 2015-01-28 삼성전기주식회사 Composite electronic component and board for mounting the same
US20150022937A1 (en) * 2013-07-18 2015-01-22 Samsung Electro-Mechanics Co., Ltd. Composite electronic component and board having the same
US9520244B2 (en) * 2013-07-18 2016-12-13 Samsung Electro-Mechanics Co., Ltd. Composite electronic component and board having the same
WO2015098990A1 (en) * 2013-12-24 2015-07-02 京セラ株式会社 Laminated electronic component and structure for mounting same
CN105849835A (en) * 2013-12-24 2016-08-10 京瓷株式会社 Laminated electronic component and structure for mounting same
CN111048310A (en) * 2018-10-11 2020-04-21 株式会社村田制作所 Electronic component

Similar Documents

Publication Publication Date Title
JP2007194312A (en) Multilayer ceramic capacitor
JP6395002B2 (en) Circuit board mounting structure of multilayer ceramic capacitor
JP2007194313A (en) Multilayer ceramic capacitor
JP6263849B2 (en) Multilayer ceramic capacitor
TW439073B (en) Method for mounting circuit board for multilayer ceramic capacitor and circuit board
JP6136916B2 (en) Multilayer capacitor
JP2007103496A (en) Capacitor and substrate assembly
JP5724968B2 (en) Multilayer capacitor and method for reducing vibration noise of circuit board
US9148955B2 (en) Mounting structure of circuit board having multi-layered ceramic capacitor thereon
JP2010123614A (en) Ceramic capacitor and electronic component equipped with the same
JP5974653B2 (en) How to use multilayer capacitors
US11004608B2 (en) Composite electronic component
US9472344B2 (en) Electronic component
KR20180047892A (en) The multilayered electronic component
KR20190024186A (en) Electronic component and board having the same mounted thereon
JP2014187322A (en) Electronic component
US9615460B2 (en) Circuit board device and circuit board device for reducing acoustic noise
JP5768782B2 (en) Mounting board land structure and mounting board vibration noise reduction method
US20150136464A1 (en) Electronic Device
JP4290385B2 (en) Capacitor circuit board mounting method and capacitor mounting circuit board
JP4724147B2 (en) Multilayer ceramic capacitor and its mounting structure
JP2003318057A (en) Method for mounting capacitor on circuit board, and capacitor mounted circuit board
JP2014203994A (en) Multilayer capacitor, taping multilayer capacitor series, and mounting structure of multilayer capacitor
WO2009096003A1 (en) Mounting structure for chip capacitor, electronic device and mounting method
US8614876B2 (en) Multilayer ceramic capacitor