JP2007181136A - Agc circuit, agc method, program and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an AGC circuit capable of preventing the omission of a required signal while suppressing an unwanted noise signal by controlling an attack time, a release time and the like while taking into account the continuity of noise generation. <P>SOLUTION: An AGC circuit comprises a means for comparing an input signal level with a reference level, an attack processing means for reducing an AGC gain when the input signal level is equal with or higher than the reference level, and a release processing means for returning the AGC gain to a reference value when the input signal level is lower than the reference level. In such an AGC circuit, an attach continuation time measuring means is provided for measuring how many times attack processing is continued prior to present processing, and an AGC response coefficient setting means is provided for setting an AGC response coefficient based on a measured result of the attack continuation time measuring means in release processing, and an AGC gain of release processing is then set on the basis of a value set by the AGC response coefficient setting means. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to an AGC circuit, an AGC method, and a program thereof suitable for a communication device or the like.

  In communication devices that handle audio signals such as wireless telephone devices and wired telephone devices, keep the audio signal level sent to the communication line below a certain value so as not to disturb other channels, or In order to prevent overmodulation and the like, a means for keeping the audio signal level as a modulation signal constant is provided. In general, this function is called automatic gain control (AGC) or automatic level control (ALC). Hereinafter, the present invention is not limited to this, but an audio signal automatic gain control (hereinafter referred to as “AGC”) used in a wireless communication device will be described as an example.

FIG. 6 is a block diagram showing a configuration example of a part of a wireless communication apparatus provided with a conventional audio signal automatic gain control (AGC) circuit. In the apparatus shown in this example, an output of the microphone 20 is converted into a digital signal by an analog / digital converter (A / D converter) 21, and a low-pass filter (LPF) 22 configured as a digital processing circuit, a pre-emphasis circuit 23. , AGC circuit 24, converted to an analog signal again by a digital / analog converter (D / A converter) 25, and then supplied to a voltage controlled oscillator (VCO) 26 having a modulation function It is. In this circuit, a portion surrounded by a broken line often uses an integrated circuit for digital processing such as a DSP (Digital Signal Processor or Processing). The AGC circuit keeps the level of the audio signal supplied from the microphone 20 or the like as a modulation signal at a constant value, and an excessive signal is supplied to the modulation circuit to adjust the maximum modulation frequency and other specified modulation levels. I try not to exceed it.
In such an AGC circuit, the reference signal level is compared with the input audio signal level, and for the signal exceeding the reference level, the amplification level of the amplification circuit of the AGC circuit and the attenuation amount of the attenuator (hereinafter collectively referred to as these). "AGC gain") is changed so that the level does not exceed a certain value.At this time, the process of suppressing the level against excessive input is called attack processing, and conversely below the reference value. The process for returning the reduced AGC gain to the original value for the input signal is called release process, and the time required for each process is called attack time and release time.

In general, it is known that the audibility and intelligibility when listening to the processed audio signal differ greatly depending on the length of the release time and the attack time.
For example, when an excessive level signal is input, the AGC circuit must react quickly and be suppressed to an appropriate level, so a shorter attack time is preferable. On the other hand, when an input signal returns to a normal level immediately after an excessive level signal is input, it is known that a natural audibility can be obtained by returning to the original gain over a relatively long time.
As the AGC circuit used in such a wireless communication device, for example, one disclosed in Japanese Patent Laid-Open No. 6-314942 “Automatic Audio Signal Amplitude Control Circuit” exists. This is done by providing a variable attenuator with electronically adjustable attenuation before the analog / digital converter, comparing the average value of the required sampling period with the reference value, and releasing it according to the deviation from the reference value level. The length of time is set, and the amount of attenuation of the electronically controllable variable attenuator is adjusted.
This device adjusts the length of the attack time and release time according to the magnitude of the excessive signal level that is input, the release time after a signal with a level that greatly exceeds the reference level is input, Since the release time after input of a signal that slightly exceeds the reference level is shortened, even if a signal of a relatively small level is input after the input signal that slightly exceeds the reference level, it is suppressed and missing from the playback sound. The possibility of doing so is reduced, and the clarity can be improved.
JP-A-6-314942

  However, in the above-described conventional AGC circuit, the attack time and release time are controlled according to the magnitude of the input signal level. For example, the gain is greatly limited immediately after an excessive signal exceeding the reference level is input. Therefore, if a relatively small audio signal is input immediately after that, the amplitude of the audio signal of that portion is reduced, resulting in a lack of that portion from the reproduced audio signal, resulting in reduced clarity. there were. For example, excessive audio signals mixed in the microphone of a radio communication device include single noises such as horns of automobiles and noises generated continuously for a relatively long time, such as flight of an airplane or passage of a large automobile. There are various types of noise such as background noise that continues for a longer time.

In this case, for example, when the AGC circuit responds to a single excessive noise such as a car horn, the gain is instantaneously greatly reduced by a short attack time, and the noise is suppressed to a predetermined level. Therefore, a relatively small level audio signal input during the release time is dropped as a result of the level limitation, and clear conversation is hindered.
The present invention eliminates the drawbacks of the conventional AGC circuit, and controls the attack time, release time, etc. in consideration of the continuity of noise generation, while suppressing unnecessary noise signals. An object of the present invention is to provide an AGC circuit, an AGC method, and a program capable of preventing signal loss.

  In order to solve the above problems, the present invention provides an AGC circuit according to claim 1, wherein means for comparing an input signal level with a reference level, and attack processing means for reducing the AGC gain when the input signal level is equal to or higher than the reference level. And an AGC circuit having a release processing means for returning the AGC gain to the reference value when the input signal level is lower than the reference level, and a continuous attack count measuring means for measuring the number of consecutive attack processes before the current process, and a release AGC response coefficient setting means for setting an AGC response coefficient based on the measurement result of the consecutive attack count measurement means at the time of processing, and an AGC gain for the release process is set based on a value set by the AGC response coefficient setting means It is characterized by.

  The AGC circuit according to claim 2, wherein the comparing means for comparing the input signal level with the reference level, the attack processing means for reducing the AGC gain when the input signal level is equal to or higher than the reference level, and the input signal level being lower than the reference level. In an AGC circuit having a release processing means for returning the AGC gain to a reference value sometimes, an A / D conversion means for converting an input analog signal into a digital signal, and a delay for adjusting the timing by delaying the input signal for a predetermined time Means for comparing the average value (Pn) of power calculated from the input signal with a predetermined reference level value (Pref), and when the comparison result of the comparison means is Pn ≧ Pref, as attack processing means , AGC gain setting means for setting an AGC gain based on a coefficient (α) of α = Pref / Pn, and before the current processing An attack continuous number measuring means for measuring the number of consecutive attack processes, and when the comparison result is Pn <Pref, an AGC response count (μ) corresponding to a measured value of the attack continuous number measuring means as a release processing means. AGC response coefficient setting means for setting and resetting the measurement value of the continuous attack count measurement means, and the delay means sets a coefficient based on the AGC gain set based on the attack processing means and the release processing means. Multiplying means for multiplying the timing-adjusted input signal is provided.

  4. The AGC circuit control method according to claim 3, wherein a process for comparing the input signal level with the reference level, an attack process for reducing the AGC gain when the input signal level is equal to or higher than the reference level, and the input signal level is smaller than the reference level. In the AGC circuit control method including the release process for returning the AGC gain to the reference value, the result of the continuous attack count measurement process for measuring the number of consecutive attack processes before the current process and the result of the continuous attack count measurement process during the release process An AGC response coefficient setting process for setting an AGC response coefficient (μ) based on the AGC, and a release gain setting process for setting an AGC gain of the release process based on the value set by the AGC response coefficient setting process And

  5. The AGC circuit control method according to claim 4, wherein the comparison processing for comparing the input signal level with the reference level, the attack processing for reducing the AGC gain when the input signal level is equal to or higher than the reference level, and the input signal level higher than the reference level. In an AGC circuit control method including a release process for returning an AGC gain to a reference value when it is small, an A / D conversion process for converting an input analog signal into a digital signal, and adjusting the timing by delaying the input signal for a predetermined time Delay processing, comparison processing for comparing the average value (Pn) of power calculated from the input signal with a predetermined reference level value (Pref), and attack processing when the result of the comparison processing is Pn ≧ Pref, = AGC gain setting processing for setting the AGC gain based on the coefficient (α) of Pref / Pn, and continuous processing before the current processing AGC response coefficient (μ) corresponding to the measured value of the attack continuous count measurement process as a release process when the result of the comparison process is Pn <Pref. And an AGC response coefficient setting process for resetting a measurement value in the continuous attack count measurement process, and the timing based on the coefficient based on the AGC gain set by the attack process and the release process is adjusted by the delay process. And a multiplication process for multiplying the input signal.

The invention according to claim 5 is an AGC processing program in which each process of the AGC circuit control method according to claim 3 or 4 is programmed to be processed by a computer.
The invention according to claim 6 is a recording medium in which the AGC processing program according to claim 5 is recorded in a computer-readable format.

  The AGC circuit according to claim 1, wherein the AGC circuit includes an attack processing means and a release processing means, and further comprises an attack continuation number measuring means for measuring the number of consecutive attack processes before the current process, and the attack continuation in the release process. Since the AGC response coefficient is set based on the measurement result of the frequency measurement means, and the AGC gain of the release process is set based on the value set by the response coefficient setting means, according to the number of attack processes before the current process Thus, the AGC gain at the time of release processing can be adjusted, and the AGC gain at the time of release processing can be selected corresponding to a single excessive input and a continuously generated excessive input. This makes it possible to lengthen the release time in the release process for excessive input signals that occur continuously such as background noise, and to quickly respond to excessive input that occurs continuously. In the release process, the AGC response count can be set so that the release process period is shortened, so that it is possible to prevent a normal level signal that is input immediately thereafter from being lost.

  According to the second aspect of the present invention, in the AGC circuit including the attack processing means and the release processing means, the A / D conversion means for converting the input analog signal into the digital signal, the input signal is delayed for a predetermined time, and the timing is set. Delay means for adjustment, comparison means for comparing an average value (Pn) of power calculated from the input signal with a predetermined reference level value (Pref), and an attack when the comparison result of the comparison means is Pn ≧ Pref The processing means includes an AGC gain setting means for setting an AGC gain based on a coefficient (α) of α = Pref / Pn, and a continuous attack count measuring means for measuring the number of consecutive attack processes before the current process, the comparison When the result is Pn <Pref, as the release processing means, an AGC response count (corresponding to the measured value of the consecutive attack count measuring means ( μ) and an AGC response coefficient setting means for resetting the measured value of the continuous attack count measuring means, and a coefficient based on the AGC gain set based on the attack processing means and the release processing means The AGC circuit according to the first aspect is easily configured as a digital processing circuit because the multiplication means for multiplying the input signal whose timing is adjusted by the delay means is provided. Furthermore, these digital processes are useful in carrying out the present invention using a general-purpose integrated circuit such as a DSP that has been frequently used in recent years.

In the inventions according to claims 3 to 5, since the AGC circuit according to claims 1 and 2 is configured as a processing procedure, respectively, the AGC circuit according to claims 1 and 2 is realized by a dedicated hardware circuit. Each processing procedure can be programmed and realized by software processing.
Further, since these softwares are stored in a recording medium such as a CD-ROM, they are carried, read by a required computer, and installed in a CPU-equipped device that can be driven by the same OS, thereby AGC of the present invention. A circuit can be realized.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings. However, the components, types, combinations, shapes, relative arrangements, and the like described in this embodiment are merely illustrative examples and not intended to limit the scope of the present invention only unless otherwise specified. .
FIG. 1 is a block diagram of an AGC circuit showing an embodiment according to the present invention.
The circuit shown in this example includes a delay device 1 that delays an input signal converted into a digital signal for a predetermined time, a squarer 2 that squares the input signal, an integrator 3 that integrates an output thereof, and the integrator 3. And the first threshold memory 5 for storing the above-described threshold value (Pref1), the comparator 4 for comparing the output of the output and the threshold value (Pref1) stored in advance, and the integration result. A selector switch (SW1) 6 for switching and outputting the output signal of the multiplier 3, a multiplier 7 connected to one terminal of the selector switch 6, and a reference value for supplying a reference value (Pref) to the multiplier 7 A memory 8, a counter 9 for coefficient of the number of consecutive times determined to be attack processing, an AGC coefficient setting unit 10 connected to the other terminal of the changeover switch SW1, and an AGC response for setting the value of the AGC response coefficient μ. A coefficient setter 11; a square root calculator 12 for calculating the square root of the signal output via the changeover switch 6; and a buffer memory 13 for storing the processing data before one sampling output by the square root calculator 12; A second comparator 14 for comparing the processing data before one sampling stored in the buffer memory 13 with the sampling data currently being processed output from the square root calculator 12, and the second comparator 14 A second changeover switch (SW2) 15 to be controlled, an AGC coefficient computing unit 16 connected to one terminal of the changeover switch, an output of the delay unit 1, and an output of the other end of the changeover switch 15; An output multiplier 17 for multiplying the output of the AGC coefficient calculator 16 is provided.
The integrator 3 need not be limited to this example, but a first-order low-pass filter type circuit may be used as shown in FIG.

  FIG. 3 is a flow chart showing a specific embodiment for controlling the AGC circuit configured as shown in FIG. 1 and FIG. The embodiment of the present invention shown in FIG. 3 will be described below with reference to FIGS. In recent years, digital wireless communication devices often use digital processing integrated circuits such as a DSP (Digital Signal Processor or Processing). In the following description, the functional block including the configuration diagram of FIG. 1 is expressed as a functional block. However, in implementing the present invention, in addition to realizing the same block as hardware, the following procedure is programmed. Needless to say, it can be realized by software.

  First, when the flow starts, an analog signal of a voice signal input from a microphone is converted into a digital signal in a transmission circuit such as a wireless communication device (S1) and supplied to the delay device 1 and the squarer 2. The amplitude level of the signal waveform is usually proportional to the voltage value of the signal, but by squaring it, it becomes a value having a power dimension (dimension) (S2), and the data is integrated for a predetermined period of time. When integration is performed at 3, an average power value Pw (a value in the n-th sampling process is expressed as Pn but has the same meaning) is obtained (S3). Therefore, the average power value Pw is compared with a threshold value (Pref, in this example, the reference value is set as a threshold value) stored in the power value threshold value memory 5 of the reference value set in advance in the comparator 4 (S4). , Pw ≧ Pref, the input signal level is higher than the threshold level, so that the signal for reducing the gain of the AGC circuit, that is, the attack processing described above is performed in order to keep the level at a constant value. Is output (S4 Yes). Based on the signal from the comparator 4, the selector switch (SW 1) 6 is controlled to switch to the upper terminal side (attack) of the drawing, and at the next multiplier 7, the reference value (stored in the reference value memory 8) Pref) is used to calculate α = Pref / Pw (S5). At this time, since Pw ≧ Pref, α <1, and this coefficient is used as an AGC coefficient, and the automatic gain function is activated to reduce the gain of the AGC circuit to reduce the output signal level. It will be controlled not to exceed. At this time, for the reason described later, the counter 9 counts how many times the input exceeding the reference value has continuously occurred in the comparison by the comparator 4 (S6). On the other hand, if the result of determination in S4 is Pw <Pref (S4 No), since the input signal level is below the reference value, the selector switch (SW1) 6 is switched to the terminal side (release) at the bottom of the drawing, A signal for performing the release process described above is generated, and the AGC coefficient α at this time is set to a maximum value (MAX), for example, 1 (S7). At this time, the numerical value of the counter 9 is reset, and the number of times that the reference value is continuously exceeded (the count of the number of consecutive attack processes) is set to zero (S8). As will be described later, in order to adjust the gain recovery speed in the release process, an AGC response coefficient μ is defined and a plurality of values are set, and the previous number of consecutive attack processes (the amplitude value of the input signal) The AGC response coefficient μ in the release process immediately after that is controlled according to the number of times that exceeds the reference value. The number of consecutive attack processes before the process is measured by the counter 9, and the μ value is selected from several numerical values based on the measurement result.

  When the AGC coefficient α and the AGC response coefficient μ are obtained as described above, the square root of the AGC coefficient α obtained as described above is calculated in the next square root calculator 12 (S9). The purpose of obtaining the square root of α is to obtain a value corresponding to the voltage value (amplitude value) of the input signal waveform because α itself is a value corresponding to the power of the input signal. The calculation result is supplied to the second comparator 14 at the next stage and the same value is stored in the buffer memory 13. Note that the processing described above has been executed before that, and the buffer memory 13 stores the same square root value of α before one sampling.

  In this state, it is determined whether or not the process at that time is a release process (S10). That is, the determination of whether or not Pw ≧ Pref in S4 is a process of determining whether or not the input signal level is greater than the reference value, but the determination here is the release process. Whether or not. The determination in this step may determine whether or not the actual processing at that time is the release processing, or determine whether or not the release processing is necessary by comparing with the processing before one sampling. You may do. For example, if it is determined that the release process is a result of the comparison by the first comparator 4 in S4, it is determined that the release process is necessary (S10 Yes). When it is determined that the comparison result of one comparator 4 is attack processing, and when α = MAX (for example, α = 1), the input signal level does not exceed the reference value, that is, the attack processing is not released. If it is not processing (S10 No), the process proceeds to step 11 to detect the magnitude relationship between the square root of the current αn (√αn) and the square root of the value αn-1 at the previous sampling (√αn-1). .

When this result (√αn) ≧ (√αn−1), that is, that the current AGC coefficient value is larger than the AGC coefficient value at the previous sampling, the input signal level when the coefficient α is calculated. In the comparison of values, if this time is smaller, the release process is required as in the case of S10, Yes, and the process proceeds to S12. In S12, as described above, the AGC response coefficient μ is selected based on the processing results of the counter 9 and the AGC response coefficient setting unit 11 in accordance with the number of consecutive attack processes before that (S12). In this μ value selection, the value of the AGC response coefficient μ is increased as the count value of the counter 9 is larger, that is, as the number of consecutive attack processes before that is larger, and conversely, the number of consecutive attack processes is smaller. When the AGC response coefficient is reduced, the AGC gain Gn is calculated using this coefficient (S13). The calculation formula is, for example, Gn = (Gn−1) + [(Gref) − (Gn−1)] * μ (Formula 1)
And In this equation, Gn is the gain (gain) of the AGC circuit in the current sampling process, Gn−1 is the gain of the AGC circuit in the process before one sampling, Gref is the target gain of the AGC circuit, and μ is the AGC response coefficient. .
As is clear from this equation, the gain Gn calculated here is obtained by multiplying the target gain by subtracting the gain at the time of the processing before one sampling by the AGC response coefficient μ, and multiplying that value by the gain of the one sampling preprocessing. Gn increases as the AGC response count μ value increases.

FIG. 4 is a diagram for explaining the relationship between the AGC response coefficient μ value and the convergence speed of the system. In this example, for example, the AGC response coefficient μ is set to μ1 = 1/128 and μ2 = 1/512. , Μ3 = 1/2048, and the relationship is μ1>μ2> μ3. As is clear from this figure, the larger the μ value, the larger the AGC gain and the shorter the release time. Conversely, when the μ value becomes smaller, the release time becomes longer. Therefore, once the AGC gain that has been greatly reduced is rapidly recovered, the AGC response coefficient μ is increased, and in the opposite case, it may be set smaller.
In this way, the calculation of Equation 1 is performed based on the set AGC response coefficient μ (S13), and the gain (gain) Gn obtained as a result of the calculation is supplied to the output multiplier 17, and the delay device 1 Is multiplied by the input signal (S14) whose timing is adjusted through (S15), it is output to the next processing block as a required signal amplitude value. On the other hand, when (√αn) <(√αn−1) as a result of the determination result in the processing of S11, that is, the AGC coefficient square root value (√αn−1) in the processing one sampling before is larger. In this case, since the current input signal level is larger, it is not necessary to further reduce the AGC gain, and the gain Gn (= √αn) obtained at that time is supplied to the output multiplier 17 ( S16) An output is obtained (S15).

FIG. 5 illustrates the above-described signal processing based on a specific example of an input signal waveform. (A) is an input signal waveform, (B) is an AGC gain coefficient Gn, and (C) is an output signal waveform. Thus, the input signal in FIG. (A) is multiplied by the AGC gain (Gn) in FIG.
In the input signal shown in FIG. 5A, the line 51 crossing the signal waveform corresponds to the reference level (Pref), and the portion above this level line is excessively input and reduced and controlled by the AGC circuit. In the conventional AGC circuit, the signal exceeding the reference level is suppressed by the AGC gain at the uniform attack time, and the release time is uniformly set corresponding to the excessive input signal level. . In the present invention, as described above, the previous process result is referred to, the AGC gain in the release process is set according to the number of consecutive attack processes, and the increase / decrease tendency of the AGC count α in the previous process is detected. Based on this, the AGC gain is set.

  In the waveform shown in this example, the AGC coefficient α in the previous processing is compared during the time timings a to b, c to f, ef and g to h in FIG. Is selected. That is, since the reference value is exceeded at time timing a, attack processing is started, the largest gain suppression function is activated at timing b, and release processing is performed thereafter. Similarly, attack processing is performed at timings c to d, and release processing is performed during the timing period from d to e. In addition, since the time c to f period is an excessively long input and the count-up number increases, the AGC circuit gain is reduced and the release time is extended by reducing the above-described AGC response coefficient μ value. ing. The input signal level values at timings b and d are substantially the same, but the subsequent release times are different because the gain of subsequent release processing is controlled based on the continuous length of the excessive input signal. Because.

As a result, as shown in FIG. 5B, the AGC gain signal waveform during the time timings a to b, c to f, e to f, and g to h is different from the processing of the conventional AGC circuit. As shown in FIG. 5C, the portion exceeding the reference level is suppressed, but the signal waveform below the reference level is not lost, and almost the same waveform is maintained. Yes. That is, since the period of time timings a to b and g to h is a single excessive input signal for a relatively short time, each release time, i and j in the figure, returns to the reference gain in a short time. Thereafter, the level suppression more than necessary for the normal level signal does not occur. On the other hand, since the period of time timings c to f is an excessively large input signal that continues for a relatively long time, the subsequent release time (k in the figure) is long, but although the signal is slightly deformed, Even during attack processing during the period, in the periods ef, the signal level increase / decrease trend is detected by comparing the coefficients in the preprocessing, and the gain control is performed precisely, resulting in significant waveform deformation of the reproduced signal. It will be clear that this has been prevented.
By these processes, the effects of preventing signal distortion due to unnecessary gain suppression and unclear communication as pointed out in the conventional problems can be obtained.

Although the embodiments of the present invention have been described above, the present invention need not be limited to these examples and can be variously modified. For example, the AGC response coefficient μ value is not limited to three types, and more values can be prepared and the μ value can be selected finely while referring to the results before the current processing. Since the value of √α calculated by the square root calculator 12 of 1 only needs to be a value corresponding to the voltage of the input signal, the result of A / D conversion of the input signal can be used.
Further, regarding the configuration shown in FIG. 1 and the processing procedure shown in FIG. 3, each functional block and processing can be realized by software processing by a computer device including a CPU. Furthermore, regarding the gain control of the release time, various selections such as a method of returning linearly and a method of changing exponentially will be possible.

In addition, each function or method constituting the AGC circuit of the above-described embodiment is programmed and written in a recording medium such as a CD-ROM in advance, and these programs are stored in a memory or a storage device of a computer. It goes without saying that the object of the present invention can be achieved by implementing it.
In this case, the program itself read from the recording medium realizes the functions of the above-described embodiment, and the program and the recording medium recording the program also constitute the present invention.

As a recording medium for storing the program, a semiconductor medium (for example, ROM, nonvolatile memory card, etc.), an optical medium (for example, DVD, MO, MD, CD, etc.), a magnetic medium (for example, magnetic tape, flexible disk, etc.) ) Or the like.
Further, not only the functions of the above-described embodiment are realized by executing the loaded program, but also the above-described implementation by cooperating with the operating system or other application programs based on the instructions of the program. The case where the function of the form is realized is also included.
When distributing to the market, store the program in a portable recording medium for distribution, or store the program in a storage device of a server computer connected via the Internet, etc. It can also be transferred to a computer. In this case, the storage device of this server computer is also included in the recording medium of the present invention.
In the computer, the functions of the above-described embodiments are realized by installing a program on a portable recording medium or a transferred program on a recording medium connected to the computer and executing the installed program. Is done.

It is a block diagram which shows the AGC circuit concerning one Embodiment of this invention. It is a functional circuit diagram which shows one Embodiment of the integrator used in this invention. It is a flowchart which shows the AGC circuit control method concerning one Embodiment of this invention. It is a figure which shows the example of the AGC response coefficient used in one Embodiment of this invention. It is a signal waveform diagram in one embodiment of the present invention, (A) is an input signal waveform diagram, (B) is an AGC gain signal waveform diagram, (C) is an AGC output signal waveform diagram. It is a block diagram which shows a part of radio | wireless communication apparatus provided with the conventional AGC circuit.

Explanation of symbols

  1 delay unit, 2 square unit, 3 integrator, 4 comparator, 5 threshold value (threshold value) memory, 6, 15 changeover switch, 7, 17 multiplier, 8 reference value memory, 9 counter, 10 AGC coefficient setting unit 11 AGC response coefficient setting unit, 12 square root calculator, 13 comparator, 14 buffer memory, 16 AGC coefficient calculator, 20 microphone, 21 analog-to-digital converter (A / D), 22 low-pass filter (LPF), 23 Pre-emphasis circuit, 24 AGC circuit, 25 Digital-to-analog converter (D / A), 26 Voltage controlled oscillator (VCO), 27 DSP circuit, α AGC coefficient, μ AGC response coefficient.

Claims (6)

  Comparing means for comparing the input signal level with the reference level, attack processing means for reducing the AGC gain when the input signal level is higher than the reference level, and returning the AGC gain to the reference value when the input signal level is lower than the reference level In the AGC circuit comprising the release processing means, the AGC response coefficient is calculated based on the measurement result of the continuous attack count measuring means for measuring the number of consecutive attack processes before the current process and the continuous attack count measuring means during the release process. An AGC circuit characterized in that an AGC response coefficient setting means for setting and an AGC gain for release processing are set based on a value set by the AGC response coefficient setting means. Comparing means for comparing the input signal level with the reference level, attack processing means for reducing the AGC gain when the input signal level is higher than the reference level, and returning the AGC gain to the reference value when the input signal level is lower than the reference level An AGC circuit comprising release processing means,
A / D conversion means for converting an input analog signal into a digital signal;
Delay means for delaying an input signal for a predetermined time to adjust timing;
A comparison means for comparing an average value (Pn) of power calculated from the input signal with a predetermined reference level value (Pref);
When the comparison result of the comparison means is Pn ≧ Pref, the AGC gain setting means for setting the AGC gain based on the coefficient (α) of α = Pref / Pn as the attack processing means, and the number of consecutive attack processes before the current process, Means for measuring the number of consecutive attacks, and
When the comparison result is Pn <Pref, the AGC response count (μ) is set as the release processing means corresponding to the measurement value of the attack continuous number measuring means, and the measurement value of the attack continuous number measuring means is reset. Response coefficient setting means;
An AGC circuit comprising: multiplication means for multiplying an input signal whose timing is adjusted by the delay means by a coefficient based on the AGC gain set by the attack processing means and the release processing means. Processing for comparing the input signal level with the reference level, attack processing for reducing the AGC gain when the input signal level is higher than the reference level, and release processing for returning the AGC gain to the reference value when the input signal level is lower than the reference level In an AGC circuit control method including:
A continuous attack count measurement process for measuring the number of consecutive attack processes before the current process; an AGC response coefficient setting process for setting an AGC response coefficient (μ) based on the result of the continuous attack count measurement process during the release process; An AGC method comprising a release gain setting process for setting an AGC gain of a release process based on a value set by an AGC response coefficient setting process. Comparison processing that compares the input signal level with the reference level, attack processing that reduces the AGC gain when the input signal level is equal to or higher than the reference level, and release that returns the AGC gain to the reference value when the input signal level is lower than the reference level In an AGC circuit control method including processing,
A / D conversion processing for converting an input analog signal into a digital signal;
Delay processing for delaying the input signal for a predetermined time and adjusting timing;
A comparison process for comparing an average value (Pn) of power calculated from the input signal with a predetermined reference level value (Pref);
When the result of the comparison process is Pn ≧ Pref, as the attack process, an AGC gain setting process for setting an AGC gain based on a coefficient (α) of α = Pref / Pn, and the number of consecutive attack processes before the current process are measured. The attack continuous count measurement process,
When the result of the comparison process is Pn <Pref, as the release process, an AGC gain return process for returning the AGC gain to the reference value and an AGC response coefficient (μ) are set corresponding to the measurement value of the consecutive attack count measurement process. AGC response coefficient setting processing for resetting the measurement value in the attack continuous number measurement processing,
An AGC method comprising: a multiplication process for multiplying an input signal whose timing is adjusted by the delay process by a coefficient based on an AGC gain set by the attack process and the release process.   5. An AGC processing program in which each process of the AGC method according to claim 3 or 4 is programmed so as to be processed by a computer.   A recording medium in which the AGC processing program according to claim 5 is recorded in a computer-readable format.

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