JP2007180576A - Field-effect transistor and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem, where in order to maintain/improve performance while promoting micronization for a high integration of LSI, a gate insulating film of high dielectric constant, with proper interface characteristics, is required. <P>SOLUTION: A field effect transistor, as well as a method of manufacturing the field effect transistor, are provided: which includes a gate insulating film 33 where a silicide film or a silicate film of two mono layers or less on an Si substrate 31, over which an insulating film is laminated; and which includes a gate insulating film where after an Si surface is terminated with a silicide film and a silicate film of two mono layers or less, an insulating film is laminated. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a semiconductor device and a manufacturing method, and more particularly, to a field effect transistor having a MOS or MIS structure and a manufacturing method thereof.

High-speed and high-integration LSIs are based on MOS type field effect transistors (FE
T: Field-Effective-Transistor). It is possible to maintain normal device characteristics and improve performance when miniaturizing by simultaneously reducing the height and lateral dimensions of each part of the MOS field effect transistor such as the insulating film and gate length. I did it.

According to the scaling law, MOS field effect transistors are being miniaturized, and next-generation MOS field effect transistors from the year 2000 AD are required to have a thickness of 2 nm or less for the SiO 2 gate insulating film. However, this film thickness region is a thickness at which the tunnel current begins to flow directly, and the leakage current cannot be suppressed, and problems such as an increase in power consumption cannot be avoided. Therefore, it is necessary to use a material having a dielectric constant higher than that of SiO2 to increase the physical film thickness and suppress the leakage current while suppressing the effective thickness in terms of silicon oxide film to 2 nm or less. Also,
Since the MOS field effect transistor is a field effect transistor as well as suppressing leakage current, Si interface characteristics are particularly important. Therefore, a gate insulating film that has a high dielectric constant and can maintain good interface characteristics is required.

A high dielectric material such as TiO 2 or ZrO 2 used as a gate insulating film is formed on a Si substrate by sputtering or CVD. However, the silicon oxide film (SiOx) with a low dielectric constant formed at the interface with the Si substrate during film formation or subsequent heat treatment reduces the capacitance between the substrate and the gate and forms a gate with a sufficiently small equivalent film thickness. There is a big problem that it is difficult to do. In recent years, using molecular beam epitaxy (MBE) method, SrTiO3 is changed to Si.
An FET using a gate insulating film epitaxially grown on a substrate has been reported (K. E
isenbeiser et al., App.Phys.Lett. 76, 1324 (2000)). In this report as well, Si substrate and SrTiO
An amorphous layer considered to be silicon oxide is formed at the interface between the three films. In order to suppress the formation of the silicon oxide film, an attempt was made to form a submonolayer of Sr silicide during the formation of the SrTiO3 film, and SrTiO3 was directly formed on Si (RAMcKee et al., Phys. Rev. Lett. 81, 3014 (1998)). However, Sr has a larger covalent bond radius than Si, and a large mismatch exists at the interface between Sr silicide and Si. For this reason, in this structure, it is difficult to expect good interface characteristics even if the generation of the silicon oxide film can be suppressed.

As described above, in order to advance miniaturization while maintaining and improving performance with the aim of higher integration of LSI, an insulating film gate insulating film that has a high dielectric constant and can maintain good interface characteristics is required. . However, maintaining a high dielectric constant without forming a silicon oxide film at the interface with the Si substrate,
In addition, a gate insulating film having good interface characteristics has not been realized.

The present invention has been made in order to solve such problems, and provides a field effect transistor having a gate insulating film that has a high dielectric constant and can satisfactorily maintain interface characteristics, and a method for manufacturing the same. Objective.

In order to achieve the above object, the present invention basically uses a gate insulating film in which a silicide film of two monolayers or less is provided on a Si substrate and an insulating film is stacked thereon. To form this gate insulating film, the Si surface is terminated with a silicide film of 2 monolayers or less (
This can be realized by using a manufacturing method in which an insulating film is stacked after termination. Furthermore, particularly good interface characteristics can be obtained when the silicide film mainly contains any of the rare earth metals La, Ce, Pr, Nd, and Sm in its composition.

Alkaline earth metals such as Sr and Ba used in the present invention have a larger covalent bond radius than Si. Whereas the Si covalent bond radius is 1.11 Å, Sr is 1.91 Å and Ba is 1.9.
It is 8cm. Therefore, when the Sr silicide film is formed on the Si substrate, there is a problem that Si dangling bonds are likely to occur due to the presence of a large mismatch due to the difference in covalent bond radius. This leads to deterioration of the interface characteristics. A silicon oxide film tends to be easily formed at the interface where such an interface structure exists. On the other hand, the covalent bond radius of La is 1.69.
Å, Ce is 1.65Å, Pr is 1.64Å, and mismatch with Si is also small.
i Dangling bonds are unlikely to occur. For this reason, a silicide film containing these metals is used to form Si.
When the surface is terminated, a stable silicide surface structure is obtained. It has been found that when an insulating film is deposited on such a surface to form a gate insulating film, it is difficult to form a silicon oxide film. In addition, the interface state can be reduced by reducing the mismatch, a gate insulating film with good interface characteristics can be realized, and the characteristics as a field effect transistor can be improved.

According to the present invention described above, the interface state is small and the mobility of the inversion layer is high.
A field effect transistor having a gate insulating film with good characteristics can be obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 3 is a diagram showing a cross-sectional configuration of an n-channel MOS field effect transistor according to a basic embodiment of the present invention. 31 is a p-type silicon substrate, 32 is an element isolation region, and 33 is a gate insulating film. The structure and manufacturing method of the gate insulating film will be described later. 34 is a gate electrode made of polysilicon, and 35 is a diffusion layer (source / drain region) into which an n-type impurity is introduced. Reference numeral 36 denotes an insulating film (for example, a CVD silicon nitride film) formed on the side wall of the gate electrode 34, and reference numeral 37 denotes an interlayer insulating film (for example, a CVD silicon oxide film).
7 and the source / drain regions 35 through the contact holes provided in the
An Al wiring 38 is connected to this.

The MOS field effect transistor having the structure as shown in FIG. 3 is manufactured as follows. The manufacturing method (first embodiment) (reference example) will be described with reference to FIG.
First, a trench for element isolation is formed on a p-type silicon substrate 11 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm by reactive ion etching. Subsequently, the element isolation region 12 is formed by embedding an LP-TEOS film, for example (FIG. 1A). As an example, MBE
A case where a gate insulating film is formed using a method will be described. The Si surface is first wet-treated with dilute hydrofluoric acid, and the surface is terminated (terminated) with hydrogen. Next, this board is
Introduce to E equipment. The substrate temperature is set to 300 ° C., La is deposited as a monolayer on the Si substrate using metal La as an evaporation source, and then the Si substrate temperature is raised to 600 ° C. to thereby form a monolayer La silicide (LaSi 2) film 13. Then, the Si surface is terminated (FIG. 1B). Although the silicide film is a metal, it can be used as a part of the gate insulating film if it has a thickness of 2 monolayers or less as in the present invention. Then set the substrate temperature to 3
The temperature is lowered to 00 ° C., La and oxygen gas are simultaneously supplied, and a high dielectric film 14 of La2O3 amorphous layer having a high dielectric constant is laminated on the La silicide film 13 by 5 nm (FIG. 1C).

By using the manufacturing method as described above, a gate insulating film can be formed without forming a silicon oxide film at the interface with the Si substrate. The effective thickness in terms of silicon oxide film of the gate insulating film produced in this embodiment can be 1 nm. On the other hand, La
When La2O3 was formed directly without terminating the Si surface with a silicide film, a silicon oxide film of 2.5 nm was formed at the interface. In this case, the effective equivalent thickness of the silicon oxide film is 3 nm or more, and it is impossible to realize the equivalent thickness of 2 nm or less required for the next generation LSI.

In order to manufacture the MOS field effect transistor as shown in FIG. 3, a polysilicon film is deposited on the entire surface by chemical vapor deposition after the gate insulating film manufacturing process as shown in FIG. A gate electrode 34 is formed by patterning the silicon film. Subsequently, for example, SiH 4 gas diluted with nitrogen gas and NH 3 at 450 ° C. and a pressure of 0.1 Pa to 1 atm.
A CVD silicon nitride film 36 of, for example, 5 to 200 nm is deposited using a gas mixture. Subsequent processes are the same as the manufacturing process of a normal MOS field effect transistor. That is, for example, arsenic ions are implanted at an acceleration voltage of 20 keV and a dose of 1 × 10 ¹⁵ cm ⁻² to form a source region and a drain region 35. Subsequently, a CVD silicon oxide film to be an interlayer insulating film 37 is deposited on the entire surface by chemical vapor deposition, and contact holes are opened in the interlayer insulating film. Subsequently, an Al film is deposited on the entire surface by sputtering, and this Al film is patterned by reactive ion etching, thereby completing a MOS field effect transistor having a gate insulating film as shown in FIG. MOS fabricated in this way
Since the field effect transistor has few interface states and the mobility of the inversion layer is high, it was confirmed that good characteristics were obtained.

An example in which the method for manufacturing the gate insulating film of the MOS field effect transistor having the structure as shown in FIG. 3 is modified will be described as a second embodiment. First, as in the first embodiment, a trench for element isolation is formed on a silicon substrate to form an element isolation region. A Si substrate whose surface is terminated with hydrogen is introduced into the MBE apparatus. A single monolayer La silicide (LaSi2) film is formed by evaporating one monolayer of La on a Si substrate using a metal La as an evaporation source and then raising the Si substrate temperature to 600 ° C. Then, the Si surface is terminated. Thereafter, the substrate temperature is lowered to 400 ° C., Si, Zr, and oxygen gas are simultaneously supplied, and Zr silicate (ZrO2− having a high dielectric constant on La silicide).
A SiO2) film is laminated to 5 nm. By using the manufacturing method as described above, a gate insulating film having a high dielectric constant could be formed without forming a silicon oxide film at the interface with the Si substrate. The effective thickness of the gate insulating film manufactured in this embodiment in terms of silicon oxide film is 1.
6 nm could be achieved. The MOS field effect transistor using this gate insulating film has few interface states and high mobility of the inversion layer, so that it was confirmed that good characteristics were obtained. In this embodiment, La silicide is used. However, the same characteristics can be obtained when the Zr silicate insulating film is formed after the Sr silicide is formed.

An example in which the method for manufacturing the gate insulating film of the MOS field effect transistor having the structure as shown in FIG. 3 is modified will be described as a third embodiment (reference example). First, as in the first embodiment, a trench for element isolation is formed on a silicon substrate to form an element isolation region. A Si substrate having a Si surface terminated with hydrogen is introduced into the MBE apparatus. 30 substrate temperature
After depositing 1 monolayer of La on the Si substrate using metal La as the evaporation source at 0 ° C.,
By raising the temperature of the Si substrate to 600 ° C., one monolayer La silicide (LaSi
2) Form a film and terminate the Si surface. After that, the substrate temperature is lowered to 300 ° C.
Ti, oxygen gas are simultaneously supplied, and an epitaxial SrTiO 3 film having a high dielectric constant is laminated on the La silicide film by 10 nm. By using the manufacturing method as described above, Si
A gate insulating film having a high dielectric constant could be produced without forming a silicon oxide film at the interface with the substrate. The effective thickness of the gate insulating film formed in this embodiment in terms of silicon oxide film can be 0.2 nm. The MOS field effect transistor using this gate insulating film has few interface states and high mobility of the inversion layer, so that it was confirmed that good characteristics were obtained. In this embodiment, the SrTiO 3 film is laminated on the La silicide, but the same effect can be obtained even when SrZrO 3 is laminated. The converted film thickness in this case was 0.7 nm.

In the first to third embodiments described above, the La silicide film or the Sr silicide film is used, but a silicide film of another metal can also be used. In particular, La, Ce, Pr, N
A remarkable effect is obtained when either of the silicide films of d and Sm is used. Also, La2O3, Zr silicate, SrTiO3, SrZrO3 were used as the high dielectric film, but TiO2
It is possible to use a wide range of high dielectric layers such as other amorphous layers such as Ta2O5, Al2O3, ZrO2, crystal layers such as LaAlO3, Hf silicate, La silicate, and the like.

Next, an example in which the manufacturing method of the gate insulating film of the MOS field effect transistor having the structure shown in FIG. 3 is changed will be described as a fourth embodiment (reference example) (see FIG. 2).
. First, a trench for element isolation is formed on a p-type silicon substrate 21 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm by reactive ion etching. Subsequently, for example, LP-TEOS
The element isolation region 22 is formed by embedding the film (FIG. 2A). As an example, MB
A case where a gate insulating film is formed using the E method will be described. The Si surface is first wet-treated with dilute hydrofluoric acid, and the surface is terminated with hydrogen. Next, this substrate is introduced into the MBE apparatus. The substrate temperature is set to 300 ° C., and Ce is deposited as a monolayer on the Si substrate by using metal Ce as an evaporation source, and then the Si substrate temperature is raised to 600 ° C. to thereby form a monolayer Ce silicide (CeSi 2) film 23. Form and terminate the Si surface (Fig. 2 (b)
). Next, oxygen of 1 × 10 ⁻⁴ Pa is introduced into the MBE apparatus to oxidize the silicide film 23 and change it into a silicate film (FIG. 2C). Thereafter, the substrate temperature is lowered to 300 ° C.
SrT having a high dielectric constant on the Ce silicate film 24 by simultaneously supplying r, Ti and oxygen gas
An iO3 high dielectric film 25 is epitaxially grown. The film thickness was 10 nm (FIG. 2 (d
)).

By using the manufacturing method as described above, a gate insulating film can be produced without forming a silicon oxide film at the interface with the Si substrate. The effective thickness of the gate insulating film formed in this embodiment in terms of silicon oxide film can be 0.2 nm. After forming the gate insulating film according to the present embodiment, a MOS field effect transistor as shown in FIG. 3 was fabricated by the same method as described in the first embodiment. It was confirmed that the MOS type field effect transistor manufactured in this way has good characteristics because it has few interface states and the mobility of the inversion layer is high.

Next, an example in which the method for manufacturing the gate insulating film of the MOS field effect transistor having the structure shown in FIG. 3 is modified will be described as a fifth embodiment (reference example). First, a trench for element isolation is formed on a silicon substrate to form an element isolation region. The Si surface is terminated with hydrogen and introduced into the MBE apparatus. One monolayer of Zr silicide (ZrSi2) film is formed by evaporating one monolayer of Zr on a Si substrate using a metal Zr as an evaporation source at a substrate temperature of 300 ° C. and then raising the Si substrate temperature to 600 ° C. Terminate the Si surface. Next, oxygen of 1 × 10 ⁻⁴ Pa is introduced into the MBE apparatus to oxidize the silicide film and change it into a silicate film. Thereafter, the substrate temperature is lowered to 300 ° C., and Sr, Z
r and oxygen gas are simultaneously supplied to epitaxially grow SrZrO3 having a high dielectric constant on the Zr silicate. The film thickness was 5 nm. By using such a manufacturing method, S
A gate insulating film can be produced without forming a silicon oxide film at the interface with the i substrate. The effective thickness of the gate insulating film formed in this embodiment in terms of silicon oxide film is 0.3 nm.
Could be achieved. It was confirmed that the MOS type field effect transistor manufactured in this way has good characteristics because it has few interface states and the mobility of the inversion layer is high.

In the fourth and fifth embodiments, Ce silicate or Zr silicate film is used, but other metal silicate films can also be used. In particular, when any silicate of La, Ce, Pr, Nd, and Sm is used, a remarkable effect can be obtained. In addition, SrTiO is used as a high dielectric film.
3, SrZrO3 was used, but La2O3, TiO2, Ta2O5, Al2O3, ZrO
It is possible to use a wide range of high dielectric layers such as amorphous layers such as 2, crystal layers such as LaAlO 3, Hf silicate films, La silicate films, Zr silicate films, and the like.

Process sectional drawing for demonstrating 1st Embodiment of this invention manufacturing method. Process sectional drawing for demonstrating 4th Embodiment of this invention manufacturing method. The figure for demonstrating the MOS type field effect transistor of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11, 21, 31 ... Silicon substrate 12, 22, 32 ... Element isolation region 13, 23 ... Silicide film 24 ... Silicate film | membrane 14, 25 ... High dielectric film 33 ... Gate insulating film 34 ... Gate electrode 35 ... Diffusion layer (source)・ Drain region)
36 ... CVD silicon nitride film 37 ... Interlayer insulating film 38 ... Al wiring

Claims (4)

In a field effect transistor in which a source / drain region is provided in a Si semiconductor substrate and a gate electrode is provided between the source / drain regions via a gate insulating film, La, Ce, Pr of 2 monolayers or less are formed on the Si substrate. , Nd, Sm is provided, and a laminated film in which a silicate film is provided thereon is used as a gate insulating film. 2. The field effect transistor according to claim 1, wherein the silicate film is at least one selected from Zr silicate, Hf silicate, and La silicate. In manufacturing a field effect transistor having a source / drain region on a Si semiconductor substrate and a gate electrode provided between the source / drain regions via a gate insulating film, the S
Forming a gate insulating film by forming a silicide film containing any of La, Ce, Pr, Nd, and Sm of 2 monolayers or less on the surface of the i substrate to terminate the Si surface, and then laminating a silicate film A method for manufacturing a field effect transistor, which is characterized. 3. The method of manufacturing a field effect transistor according to claim 2, wherein the silicate film is at least one selected from Zr silicate, Hf silicate, and La silicate.

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