JP2007180207A - Process evaluation device, semiconductor device therewith, and evaluation method of semiconductor manufacturing process using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process evaluation device equipped with evaluation patterns for evaluating correctly the electric stress derived from the potential difference in the wafer surface generated in the process of manufacturing a semiconductor device. <P>SOLUTION: The process evaluation device formed on a semiconductor substrate comprises: a plurality of two-terminal elements 3a and 3b consisting of wiring layers with inspection regions opposing each other while sandwiching an insulating film; and an antenna pattern 5 consisting of two or more conductive patterns having the same antenna ratio which are formed as top layer wiring in a predetermined region of the semiconductor substrate, so that it may be brought into contact with at least one terminal of the two-terminal elements 3a and 3b, respectively. Accordingly, the electric charge induced on the antenna pattern can be detected by the breakdown caused by the voltage rise between the two-terminal element 3a and 3b. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a device for process evaluation, a semiconductor device including the device, and a method for evaluating a semiconductor manufacturing process using the device, and more particularly, plasma charging damage due to an antenna effect during semiconductor manufacturing is more appropriately and accurately evaluated. It is about the method.

  In recent years, in the manufacturing process of semiconductor integrated circuit devices, various plasma treatments have been widely used as a method for increasing the reactivity by using energy from plasma, reducing the processing temperature, and realizing active processing. . Among these, plasma processes such as plasma CVD and RIE are indispensable for forming a wiring layer, an interlayer insulating film, and the like.

Solid-state imaging devices including a CCD (Charge Coupled Device), which is an imaging device such as an area sensor, are increasingly required to be reduced in size and thickness due to the necessity of application to mobile phones and digital cameras.
Such a solid-state imaging device includes, as a basic structure, a photoelectric conversion unit such as a photodiode, a charge reading unit from the photoelectric conversion unit, and a charge transfer unit including a charge transfer electrode for transferring the read charge. Have. A plurality of charge transfer electrodes are arranged adjacent to each other on a charge transfer channel formed on a semiconductor substrate, and are sequentially driven by a clock signal.

  In such a solid-state imaging device, a conductive film such as polysilicon is patterned to form a wiring layer, or diffused into the conductive film when plasma etching is performed on an insulating film or a conductive film on the wiring layer. When the layers are not connected, plasma charges are accumulated in the wiring layer, and current flows into the gate oxide film or the interelectrode insulating film below the charge transfer electrode to which the wiring layer is connected. This current causes problems such as gate breakdown, changes in characteristics due to changes in gate oxide film quality, and deterioration of hot carrier life. Such a phenomenon is called an “antenna effect”, and a defect due to such an antenna effect is called “antenna damage”, which is a serious problem in semiconductor manufacturing.

Such antenna damage causes a more serious problem as miniaturization progresses, and the cause is as follows.
In other words, the gate oxide film is becoming thinner, and the breakdown voltage of the gate oxide film is considerably lower than that of the conventional process, and it is said that the antenna damage is worsening as the thickness is further reduced. ing.

What has not been a problem in the past due to the above factors, in the recent fine process, even if the antenna ratio is about several thousand levels, not only the solid-state imaging device but also general LSI design, the manufacturing process During the process, antenna damage such as destruction of the gate oxide film and deterioration of transistor characteristics has occurred. Conventionally, “antenna ratio” generally refers to the ratio between the area of a conductive layer in which plasma charges generated in a plasma processing step such as plasma etching are accumulated and the area of a gate.
For these reasons, it has become necessary to evaluate and take countermeasures for antenna damage with higher accuracy than required for conventional input / output terminals.

  Conventionally, as a method for evaluating antenna damage of a solid-state image sensor, an evaluation pattern is formed in a predetermined region on the surface of a silicon substrate on which the solid-state image sensor is formed, as shown in FIG. ing.

  As the evaluation pattern, for example, a first layer pattern 3a formed in the same process as the first layer electrode made of the first amorphous silicon layer formed on the surface of the silicon substrate 1 with the gate oxide film 2 interposed therebetween, For the second layer pattern 3b formed in the same process as the second layer electrode made of the second amorphous silicon layer formed so as to partially overlap the upper layer through the silicon oxide film as the interlayer insulating film 4 A contact hole is formed, and a contact plug 5P is formed in the contact hole, and an antenna pattern (metal electrode) 5a, 5b formed in the same process as an aluminum wiring or the like is used.

Assume that the semiconductor substrate on which such an evaluation pattern is formed is subjected to plasma processing.
For example, when the silicon oxide film 6 is formed on the upper layer of the evaluation pattern by plasma CVD as shown in FIG. 8, charges are accumulated in the silicon oxide films on the antenna patterns 5a and 5b. Charges are induced on the antenna patterns 5a and 5b.

Here, if the capacitance between the charge Q2 induced in the antenna pattern 5b connected to the first layer electrode and the charge Q1 induced in the antenna pattern 5a connected to the second layer electrode is C, V = When the voltage of (Q1-Q2) / C is related to the capacitance between the first layer pattern 3a and the second layer pattern 3b, and this is larger than a certain level, dielectric breakdown occurs.
Utilizing this fact, arrangements in which the area ratio of the overlap portions of the first layer pattern 3a and the second layer pattern 3b constituting the capacitor and the antenna patterns 5a and 5b serving as antennas are variously changed are arranged. A method of evaluating the magnitude of the electrical stress applied in the manufacturing process by measuring the IV characteristics of these capacitors and examining the relationship with the antenna ratio is used.

  However, in plasma processing processes such as plasma CVD and RIE in the semiconductor manufacturing process, the potential distribution in the wafer surface may become steep in some cases. In this case, the capacitor is destroyed between a place where the potential is high and a place where the potential is low. In other words, because it is caused by a change in the potential in the plane, there are cases where the conventional evaluation pattern (Test Element Group) in which the antenna ratio is changed cannot be evaluated.

  For example, as shown in FIG. 9, when the silicon oxide film 6 is formed on the metal electrode (antenna pattern) by the plasma CVD method, the charge left in the film is not uniform, and there is unevenness depending on the location. As shown in this figure, when the charge suddenly changes in a narrow range, the charge induced in the polycrystalline silicon becomes the total charge amount, so that the voltage between the first layer pattern 3a and the second layer pattern 3b is Will not be large.

  However, in an actual device such as a solid-state imaging device, there is a region where a pattern as shown in FIG. 10 exists. However, since the evaluation pattern is in the state shown in FIG. 9, the charge is canceled out on the antenna pattern due to the plasma distribution, so that the space between the first layer pattern 3a and the second layer pattern 3b as the inspection region is excessive. No excessive voltage is applied. Therefore, in the evaluation pattern, although the capacitor is not destroyed and no warning is issued, a large voltage is applied in the actual device. Here, the antenna patterns (metal electrodes) 5a and 5b may not be directly above the first layer pattern 3a and the second layer pattern 3b, and may be electrically connected even when there is wiring. The same effect is achieved.

  As described above, when the plasma is distributed, it is difficult to perform accurate evaluation with the conventional evaluation pattern, which causes a decrease in yield.

The present invention has been made in view of the above circumstances, and a device for process evaluation having an evaluation pattern for correctly evaluating an electrical stress caused by a potential difference in a wafer plane generated in a manufacturing process of a semiconductor device The purpose is to provide.
Another object of the present invention is to provide a semiconductor device including the above-described process evaluation device.
It is another object of the present invention to provide a process evaluation method for a semiconductor manufacturing process using the process evaluation device.

Therefore, a process evaluation device according to the present invention includes a plurality of two-terminal elements formed on a semiconductor substrate, each of which includes a wiring layer having inspection regions facing each other across an insulating film, and at least one of the two-terminal elements. A plurality of antenna patterns, each of which is provided as an uppermost layer wiring in a predetermined region of the semiconductor substrate so as to be in contact with each terminal and is made of a conductor pattern having the same antenna ratio.
With this configuration, when there is a change in the potential distribution, a plurality of antenna patterns consisting of conductor patterns having the same antenna ratio are arranged, so that charges caused by the plasma distribution in that region are induced in the antenna pattern. As a result, a potential difference is generated between the antenna pattern charged up by the antenna effect and one of the two-terminal elements, and this two-terminal element is destroyed, and one of the two-terminal elements is destroyed. As a result, efficient evaluation becomes possible.

In the process evaluation device according to the present invention, a plurality of the two-terminal elements are arranged on the semiconductor substrate at a predetermined interval, and the first layer pattern, the first layer pattern, and the insulating film are interposed. The antenna pattern is connected to the first layer pattern or the second layer pattern and provided at a predetermined interval. The second layer pattern is formed to have a region opposite to the first layer pattern. And formed as the uppermost layer wiring of the same area.
With this configuration, by using the antenna pattern as the uppermost layer wiring having the same area, it is possible to efficiently detect the charge-up due to the potential distribution change by repeating the same pattern.

In the process evaluation device according to the present invention, the first layer pattern of each two-terminal element is connected to an external connection terminal, and the second layer pattern of each two-terminal element is arranged at a predetermined interval. The antenna pattern is arranged at a predetermined interval in a direction orthogonal to the line pattern through an insulating film, and the corresponding line pattern is formed through a contact hole formed at an intersection. The line pattern and the antenna pattern include a matrix wiring structure so as to be connected.
With this configuration, it is possible to detect damage caused by charge-up with extremely simple and high accuracy by a simple matrix wiring structure.

  Further, the present invention includes the process evaluation device, wherein the first layer pattern is integrally formed.

  With this configuration, the first layer pattern only needs to be connected to the reference potential, and manufacturing is easy and detection is simple. Further, by connecting the first layer pattern to the reference potential so as not to cause the antenna effect, the charge up due to the antenna pattern is detected only by the second layer pattern which is one electrode of the two-terminal element. Thus, even when the plasma is distributed, the battery is efficiently charged up, and the charge-up breakdown can be detected.

Further, the present invention includes the above process evaluation device, wherein the antenna pattern is formed of a plurality of layers of conductor patterns, and adjacent layers form a matrix wiring structure.
With this configuration, if the wiring patterns are sequentially overlapped with the progress of the process, the antenna pattern can always be arranged in the uppermost layer, and can be formed without any additional process.

In the process evaluation device, the first layer and the second layer pattern may be a conductor pattern formed in the same process as the charge transfer electrode of the solid-state imaging device, and the insulating film may be an interelectrode insulating film. Including some.
With this configuration, it is possible to perform process evaluation of a solid-state imaging device in which the first layer and the second layer form the charge transfer electrode.

  By using the semiconductor substrate on which the device for process evaluation is mounted, it is possible to detect breakdown due to charge-up due to the antenna effect for each process.

Further, the present invention uses a mask pattern for process evaluation, and uses a same process to form a plurality of wiring layers each comprising a wiring layer having inspection areas facing each other across an insulating film on a semiconductor substrate. A terminal element and an antenna pattern formed of a plurality of conductor patterns having the same antenna ratio provided as a top layer wiring in a predetermined region of the semiconductor substrate so as to make contact with each of the two terminal elements Forming a process evaluation device; and performing a process on the process evaluation device, and determining, in each process process, that the two-terminal element is destroyed due to an antenna effect and is defective due to plasma charge. Including.
With this configuration, since the antenna pattern including a plurality of conductor patterns having the same antenna ratio is provided, charge-up due to plasma charge can be detected with higher accuracy.

According to the present invention, in the method of manufacturing a semiconductor device using the process evaluation device, the step of forming the process evaluation device includes forming a first layer pattern on at least a part of the semiconductor substrate and externally connecting the process evaluation device. A step of connecting to a terminal, a step of forming a line pattern arranged at a predetermined interval to form a second layer pattern of each of the two-terminal elements, and a direction orthogonal to the line pattern via an insulating film Forming an antenna pattern so as to be connected to the corresponding line pattern via a contact hole formed at a crossing portion, and arranging the antenna pattern so as to be matrix wiring with the line pattern and the antenna pattern It includes what is a process of forming a process evaluation device having a process evaluation region constituting the structure.
With this configuration, the potential distribution can be efficiently detected by repeating a very simple pattern, and breakdown due to charge-up can be detected. Desirably, if the first layer patterns are connected in common, for example, connected to the ground potential, only the charge-up by the second layer electrode pattern can be detected, and highly accurate detection is possible.

Furthermore, the present invention includes the above-described method for manufacturing a semiconductor device, including a step of forming a semiconductor device while performing the same process as the manufacturing process of the semiconductor device in the process evaluation region using the process evaluation device. This includes a step of determining that the terminal element is defective when the terminal element is broken.
With this configuration, process evaluation can be efficiently realized by detecting dielectric breakdown.

According to the present invention, in the method of manufacturing a semiconductor device, the step of forming the semiconductor device includes a step of forming an interlayer insulating film and a step of forming a wiring pattern. Forming a contact hole in the interlayer insulating film so as to be in contact with each other in one region, and forming a line pattern in a direction orthogonal to the antenna pattern.
With this configuration, the electric charge charged in the antenna on the uppermost layer is transmitted to the electrode of the two-terminal element by propagating to the second layer pattern. Since the change in potential due to the charge-up charge of the antenna pattern destroys the two-terminal element, it is possible to detect the charge-up efficiently by adding contact holes and line patterns sequentially as the process proceeds. it can.

  Here, the device can be applied to various devices such as a solid-state imaging device, a transistor, and a nonvolatile memory. For example, when the gate insulating film of a transistor is subjected to plasma charging damage, the resistance value as the gate wiring varies. This affects the operation of the device itself connected to the plasma charging damage and the device connected to the gate portion. Even such a minute change can be detected by arranging the pattern so as to increase the antenna ratio.

  In addition, considering the device type, leakage current, switching speed, and part or all of the resistance value, the antenna ratio should be set so that the evaluation result can be output when the degradation exceeds a certain range as device destruction. It is preferable to decide. This makes it possible to more accurately determine whether or not this is an error in the antenna check.

According to the present invention, it is possible to evaluate destruction of an element due to a potential difference in a wafer surface generated in a process with high efficiency, and it is possible to form a semiconductor device with higher efficiency and higher quality than in the past.
Further, by adding a conductor pattern to be an antenna pattern for each conductor pattern forming process, it is possible to always detect antenna destruction with high accuracy even when the plasma is distributed.

Embodiments of the present invention will be described below.
1 to 3 are schematic diagrams showing a method for evaluating plasma charging damage according to the present invention. FIG. 1 is a cross-sectional view showing a process evaluation device according to an embodiment of the present invention, FIG. 2 is a top view, and FIG. 3 is a schematic view of a semiconductor wafer as a semiconductor device provided with this process evaluation device. In the present embodiment, as shown in FIG. 3, one process evaluation device 10R is formed for each shot. Here, one process evaluation device is formed for each shot, but one process evaluation device may be formed on one semiconductor wafer.

  As shown in FIG. 1, the semiconductor device provided with the process evaluation device according to the present embodiment has a two-terminal element in which the process evaluation device has an antenna pattern on a silicon substrate 1 via a gate oxide film 2. It is formed as. This device for process evaluation is connected to an external connection terminal 5a of a two-terminal element, and is arranged at a predetermined interval and is formed with a line pattern, and an insulation made of a silicon oxide film with respect to the first layer pattern 3a. As a two-terminal element arranged in one row, which is composed of a second layer pattern 3b composed of line patterns arranged at a predetermined interval so as to face each other through the film 4 and have the same area. Capacitors and antenna patterns 5b connected to the second layer patterns 3b of these capacitors are arranged at predetermined intervals in the direction orthogonal to the line patterns via the insulating film 4, and formed in contact holes formed at the intersections. The line pattern and the antenna pattern are connected to the corresponding line pattern (second layer pattern 3b) through the plug 5P. Characterized in that to constitute a matrix wiring structure and 5b.

  Here, the first layer pattern 3a may be formed integrally, or may be connected to the ground potential by an external connection terminal.

  According to the above configuration, the first layer pattern is connected to the ground potential as the reference potential so that the antenna effect does not occur, so that the charge charge due to the antenna pattern is the one electrode of the two-terminal element. Even when the plasma is distributed only in the layer pattern and the plasma is distributed, the charge is efficiently charged up to the second layer pattern, and the charge breakdown can be detected.

Next, a method for evaluating a semiconductor manufacturing process using this process evaluation device will be described.
First, as shown in FIG. 3, a part of the mask is changed to form a process evaluation device for each shot as shown in FIG.

For example, in the process of forming the solid-state imaging device substrate, the first layer pattern 3a is formed simultaneously with the formation of the first layer electrode pattern.
Then, a capacitor insulating film (4) is formed so as to form a capacitor serving as an inspection region in the step of forming the silicon oxide film 4 formed around the first layer electrode pattern, and the step of forming the second layer electrode pattern At the same time, the second layer pattern 3b is formed.

  Further, plugs 5P are formed on the contacts formed in the interlayer insulating film, and line patterns 5b (line and space patterns) formed at a desired interval so as to have a desired antenna ratio are formed.

In this state, a silicon oxide film is formed on the upper layer by plasma CVD.
A probe is applied to the pad to evaluate the IV characteristics of the capacitor. When the insulating film of the capacitor is broken, current flows at a voltage lower than usual, as shown by the curve a in FIG. At this time, it is determined that a charge-up has occurred in the plasma CVD process and the capacitor is destroyed, a process improvement warning is issued, and the process is adjusted.
On the other hand, when the capacitor is not broken, it changes as shown by a curve b in FIG.

According to the present invention, since the antenna pattern is composed of a plurality of line patterns, even when there is a distribution in plasma, charges are induced in each antenna pattern, and high-precision detection is possible. Become.
Therefore, when a potential difference is actually generated at the antenna end and a dielectric breakdown occurs, it is possible to avoid such a problem that a potential difference does not occur in the test pattern due to the plasma distribution and the breakdown is not detected.

  In the above-described embodiment, the inspection region is constituted by a capacitor. However, the inspection region is not limited to the capacitor, and may be a MOS device.

  (Although the first layer patterns are collectively connected to a constant potential, a predetermined voltage may be applied to each. The first layer pattern may be connected to an antenna pattern having a desired antenna ratio. Good.)

(Embodiment 2)
Next, a second embodiment of the present invention will be described.
In the first embodiment, the first layer pattern is formed as an individual pattern. However, as shown in FIG. 5, an integrally formed first layer pattern 3g may be used. Others are the same as those in the first embodiment, but the potential is constant because of the integrated pattern, and a stable reference potential can be obtained, so that reliable evaluation is possible.

(Embodiment 3)
Next, a third embodiment of the present invention will be described.
In the case of sequentially forming multilayer wiring in the device manufacturing process, in addition to the first embodiment, a line pattern orthogonal to the nearest lower layer is arranged for each conductor layer forming process, By forming a matrix wiring structure connected to each other at one place, it becomes possible to more reliably realize evaluation for each process.

  For example, in the manufacturing process of the solid-state imaging device, as shown in FIG. 6, the first layer pattern 3a is formed in the same process as the first layer electrode, and the second layer pattern is formed in the same process as the second layer electrode. Then, the antenna pattern 5b is formed in the tungsten light shielding film patterning step. Further, an upper antenna pattern 7b made of an aluminum layer is formed in the aluminum wiring forming process so as to be orthogonal to the antenna pattern 5b. 7p is a plug.

  And after forming an interlayer insulation film in this upper layer by plasma CVD method, the IV characteristic between the external connection terminal connected to the 1st layer pattern and the upper layer antenna pattern 7b which consists of an aluminum layer is measured.

As a result, when the curve a shown in FIG. 4 is provided, it is determined that the insulating film sandwiched between the first layer pattern and the second layer pattern as an inspection region is broken.
Due to the antenna effect, charges accumulated in the upper layer antenna pattern 7b are transferred to the second layer pattern via the antenna pattern 5b, and a high voltage is applied between the first layer pattern and the second layer pattern, causing destruction. Will occur.
In this way, the process evaluation can be realized by sequentially adding the mask pattern in the same process as the actual process.

  By using the process evaluation device of the present invention, it is possible to perform a reliable process evaluation even when a plasma distribution is generated with an extremely simple structure. Therefore, an evaluation wafer equipped with a process evaluation device is provided. Alternatively, a defective process can be efficiently detected in a process by using a chip formed appropriately in a desired region in the surface of an actual semiconductor wafer for each chip or shot.

The figure which shows the device for process evaluation which concerns on Embodiment 1 of this invention Top view of device for process evaluation according to Embodiment 1 of the present invention Semiconductor wafer on which device for process evaluation according to Embodiment 1 of the present invention is mounted The figure which shows the test result in the evaluation method using the device for process evaluation of this invention The figure which shows the device for process evaluation which concerns on Embodiment 2 of this invention The figure which shows the device for process evaluation which concerns on Embodiment 3 of this invention Diagram showing a conventional process evaluation device Diagram showing a conventional process evaluation device Diagram showing a conventional process evaluation device Diagram showing a conventional process evaluation device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Gate oxide film 3a 1st layer pattern 3b 2nd layer pattern 5b Antenna pattern

Claims (11)

A plurality of two-terminal elements formed on a semiconductor substrate and made of a wiring layer having inspection areas facing each other across an insulating film;
A plurality of antenna patterns having the same area ratio, each of which comprises a conductor pattern provided as a top layer wiring in a predetermined region of the semiconductor substrate so as to contact at least one terminal of the two-terminal element; Process evaluation device. A process evaluation device according to claim 1, comprising:
A plurality of the two-terminal elements are arranged on the semiconductor substrate at a predetermined interval, and are formed to have a first layer pattern and a region opposite to the first layer pattern with an insulating film interposed therebetween. It consists of a two-layer pattern,
A process evaluation device in which the antenna pattern is connected to the first layer pattern or the second layer pattern and formed as an uppermost layer wiring of the same area provided at a predetermined interval. A process evaluation device according to claim 2, comprising:
The first layer pattern of each of the two terminal elements is connected to an external connection terminal,
The second layer pattern of each of the two terminal elements is composed of a line pattern arranged at a predetermined interval,
The antenna pattern is arranged at a predetermined interval in a direction orthogonal to the line pattern via an insulating film, and is connected to the corresponding line pattern via a contact hole formed at an intersection.
A process evaluation device in which a matrix wiring structure is constituted by the line pattern and the antenna pattern. A process evaluation device according to claim 3, comprising:
A process evaluation device in which the first layer pattern is integrally formed. A process evaluation device according to any one of claims 2 to 4,
The process evaluation device, wherein the antenna pattern is formed of a plurality of conductor patterns, and adjacent layers form a matrix wiring structure. A process evaluation device according to any one of claims 2 to 6,
The process evaluation device, wherein the first layer pattern and the second layer pattern are conductor patterns formed in the same process as the charge transfer electrode of the solid-state imaging device, and the insulating film is an interelectrode insulating film.   A semiconductor device on which the process evaluation apparatus according to claim 1 is mounted. In the manufacturing process of a semiconductor device, using a mask pattern for process evaluation, using the same process,
A plurality of two-terminal elements each comprising a wiring layer having inspection areas facing each other across an insulating film on a semiconductor substrate;
A process evaluation device provided as an uppermost layer wiring in a predetermined region of the semiconductor substrate so as to contact each of the two-terminal elements, and an antenna pattern comprising a plurality of conductor patterns having the same antenna ratio Forming, and
A method for evaluating a semiconductor manufacturing process, comprising: performing a process on the process evaluation device, and determining, in each process, that the two-terminal element is damaged due to an antenna effect and is defective due to plasma charge. A method for evaluating a semiconductor manufacturing process according to claim 8,
Forming the process evaluation device comprises:
Forming a first layer pattern on at least a portion of the semiconductor substrate and connecting the external connection terminals;
Forming a line pattern arranged at a predetermined interval to form a second layer pattern of each of the two terminal elements;
Forming an antenna pattern so as to be connected to the corresponding line pattern via a contact hole formed at an intersection while being arranged at a predetermined interval in a direction orthogonal to the line pattern via an insulating film; Including
An evaluation method of a semiconductor manufacturing process, which is a step of forming a process evaluation device having a process evaluation region in which a matrix wiring structure is configured by the line pattern and the antenna pattern. A method for evaluating a semiconductor manufacturing process according to claim 9,
Using the process evaluation device, including forming a semiconductor device while performing a process similar to the manufacturing process of the semiconductor device in the process evaluation region;
A method for evaluating a semiconductor manufacturing process, comprising a step of determining that a failure occurs when the two-terminal element is broken. A method for evaluating a semiconductor manufacturing process according to claim 10,
The step of forming the semiconductor device includes a step of forming an interlayer insulating film and a step of forming a wiring pattern, and the interlayer insulating film is in contact with one another in close proximity to the lower antenna pattern. A method for evaluating a semiconductor manufacturing process, comprising: a step of forming a contact hole in the semiconductor substrate;

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