JP2007180086A - Integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit device capable of incorporating a regulator circuit while maintaining reliability. <P>SOLUTION: The integrated circuit device comprises: an internal circuit; and at least one regulator circuit 11 for generating a regulation voltage (LVDD, VRG) obtained by stepping down a supply voltage (HVDD) supplied from the outside for supplying to the internal circuit. In the integrated circuit device, a region having a low breakdown voltage in which a transistor having a low breakdown voltage is arranged is formed. A region having a high breakdown voltage where a transistor having a high breakdown voltage is formed outside the region having a low breakdown voltage. The internal circuit is arranged at the region having a low breakdown voltage, and the regulator circuit 11 is formed by a transistor prepared for the region having a high breakdown voltage and is arranged at the region having a high breakdown voltage. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an integrated circuit device.

  Integrated circuit devices such as gate arrays and embedded arrays are manufactured by a high-definition process in order to increase the degree of integration of internal circuits. For this reason, a low-voltage power supply is supplied to the internal circuit. Therefore, it is necessary to supply a high voltage power source and a low voltage power source for internal circuits from the outside, for example, and the system configuration becomes complicated.

In this case, a method of incorporating a power supply circuit that generates a low-voltage power supply for the internal circuit into the integrated circuit device can be considered. I cannot maintain sex.
Japanese Patent Laid-Open No. 60-143012

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an integrated circuit device in which a regulator circuit can be incorporated while maintaining reliability.

  The present invention includes an internal circuit and at least one regulator circuit that generates a regulated voltage obtained by stepping down a power supply voltage supplied from the outside and supplies the regulated voltage to the internal circuit. A low breakdown voltage transistor is disposed in the integrated circuit device. And a high breakdown voltage region in which a high breakdown voltage transistor is disposed is formed outside the low breakdown voltage region, and the internal circuit is disposed in the low breakdown voltage region, and the regulator circuit Are related to an integrated circuit device formed by a high breakdown voltage transistor prepared for the high breakdown voltage region and disposed in the high breakdown voltage region.

  According to the present invention, an integrated circuit device includes an internal circuit and a regulator circuit. The internal circuit is arranged in the low withstand voltage region, while the regulator circuit is formed by the high withstand voltage transistor and arranged in the high withstand voltage region. Therefore, the withstand voltage against electrostatic breakdown can be improved, and the regulator circuit can be incorporated into the integrated circuit device while maintaining reliability.

  In the present invention, the output terminal of the regulator circuit is connected to a first pad which is an external terminal of the integrated circuit device, and is connected to a power supply line of the internal circuit, and against the static electricity to the output terminal of the regulator circuit. As the protection element, an electrostatic protection element arranged in the high withstand voltage region may be used.

  In this way, it is possible to prevent a situation in which the transistors constituting the regulator circuit are electrostatically destroyed.

  In the present invention, a capacitor for stabilizing the adjustment voltage of the regulator circuit may be connected to the first pad.

  This makes it possible to suppress fluctuations in the adjustment voltage even when the response speed of the regulator circuit is low.

  According to the present invention, the regulator circuit has a reference voltage input to the first input terminal, the adjustment voltage of the regulator circuit is input to the second input terminal, and a voltage difference between the reference voltage and the adjustment voltage. And a differential amplifier circuit connected to an output terminal of the differential amplifier circuit and outputting the adjustment voltage, the output circuit comprising: an output terminal of the regulator circuit; and a first power source. Provided between the first output transistor of the first conductivity type whose gate is connected to the output terminal of the differential amplifier circuit, and between the second power supply and the output terminal of the regulator circuit, You may make it include the 2nd conductivity type 2nd output transistor by which the output terminal of the said differential amplifier circuit is connected to a gate.

  In the present invention, the reference voltage and the adjustment voltage are input to the first and second input terminals of the differential amplifier circuit of the regulator circuit. The output circuit of the regulator circuit includes first and second output transistors, and the output terminals of the differential amplifier circuit are connected to the gates of the first and second output transistors. In this way, the regulator circuit operates so that the adjustment voltage and the reference voltage are the same voltage. Further, the first output transistor can function as a variable resistance element, and an efficient current supply to a load circuit (load) connected to the output terminal of the regulator circuit can be realized.

  In the present invention, the differential amplifier circuit includes: a differential unit having the first and second input terminals; a first output unit to which a first output terminal of the differential unit is connected; You may make it include the 2nd output part to which the 2nd output terminal of a differential part is connected.

  Note that the same bias current can be made to flow to the first and second output sections by, for example, a current mirror.

  According to the present invention, the differential section includes a first transistor of a second conductivity type for generating a bias current provided between the second power source and the first node, the first node, and the second node. A second transistor of the second conductivity type whose gate is the first input terminal, and between the first node and the third node, the gate of which is A second transistor of a second conductivity type serving as a second input terminal; a second transistor provided between the second node and the first power supply; and a gate and a drain connected to the second node; A fourth transistor of one conductivity type, and a fifth transistor of the first conductivity type provided between the third node and the first power supply, the gate and drain of which are connected to the third node And the first output unit includes the second power source. A sixth transistor of a second conductivity type provided between the fourth node and a gate thereof connected to the fourth node; and provided between the fourth node and the first power supply; The gate includes a seventh transistor of the first conductivity type connected to the second node, and the second output section is provided between the second power source and the fifth node, and the gate Is provided between the fifth node and the first power supply, and its gate is connected to the third node. A ninth transistor of the first conductivity type may be included.

  With such a configuration, a regulator circuit capable of stable operation with a small number of poles can be realized.

  In the present invention, the differential section is provided between the second node and the first power supply, and is turned on / off based on a control signal. The tenth transistor of the first conductivity type, An eleventh transistor of a first conductivity type provided between a third node and the first power supply and turned on / off based on a control signal may be included.

  In this case, the second and third nodes can be set to the voltage of the first power supply by turning on the tenth and eleventh transistors. As a result, the fourth and fifth transistors are turned off, and the current flowing through the differential portion and the like is cut off, so that the power consumption can be reduced.

  In the present invention, the output circuit is provided between the first output transistor and the first power supply, and is used for first output state control of a first conductivity type that is turned on / off based on a control signal. A transistor may be included.

  In this way, by turning off the first output state control transistor, the current flowing through the output circuit can be cut off and the power consumption can be reduced.

  In the present invention, the output circuit is provided between the second power supply and the output terminal of the differential amplifier circuit, and is turned on / off based on a control signal. A control transistor may be included.

  In this way, the output terminal of the differential amplifier circuit can be set to the voltage of the second power supply by turning on the second output state control transistor. As a result, the second output transistor is turned off, and the current flowing through the output circuit is interrupted to reduce the power consumption.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. FIG. 1 shows an example of an integrated circuit device according to this embodiment. This integrated circuit device includes an internal circuit (core circuit) and a regulator circuit 11. Here, the internal circuit can include a CPU, an RTC, a display driver, a memory, an interface circuit, or various logic circuits. The regulator circuit 11 (voltage stepdown circuit) generates an adjustment voltage (VRG) obtained by stepping down the power supply voltage HVDD (high potential power supply) supplied from the external power supply unit 20 and supplies the generated adjustment voltage to the supply power supply voltage LVDD ( Low-potential power) is supplied to the internal circuit. Although FIG. 1 shows an example in which one regulator circuit 11 is provided, two or more regulator circuits may be provided.

  In the integrated circuit device of FIG. 1, a low breakdown voltage region in which a low breakdown voltage transistor (a transistor whose breakdown voltage is the first voltage) is disposed is formed. In addition, a high breakdown voltage region in which a high breakdown voltage transistor (a transistor having a second breakdown voltage higher than the first voltage) is disposed is formed outside the low breakdown voltage region. Here, the low breakdown voltage transistor is a transistor having a lower maximum rating (absolute maximum rating) than the high breakdown voltage transistor, and the high breakdown voltage transistor is a transistor having a higher maximum rating than the low breakdown voltage transistor. Specifically, the high breakdown voltage transistor is, for example, a transistor having a thicker gate oxide film than the low breakdown voltage transistor.

  In this embodiment, as shown in FIG. 1, the internal circuit is arranged in the low withstand voltage region. On the other hand, the regulator circuit 11 is formed by a high breakdown voltage transistor prepared for the high breakdown voltage region and is disposed in the high breakdown voltage region. That is, the internal circuit is operated by the supply power supply voltage LVDD from the regulator circuit 11 and is therefore disposed in the low withstand voltage region. On the other hand, the regulator circuit 11 is formed in a high withstand voltage region because it needs to operate normally by an external power supply voltage HVDD (high potential power supply).

  That is, the regulator circuit 11 of the present embodiment is a circuit that generates the supply power supply voltage LVDD (adjustment voltage) from the power supply voltage HVDD. Therefore, the transistor constituting the regulator circuit 11 needs to be a transistor that operates normally even when the power supply voltage HVDD is applied. In this sense, the regulator circuit is formed of a high voltage transistor (transistor operating at HVDD). The configuration is advantageous.

  Further, for example, in the comparative example of FIG. 2, external power supply units 910 and 912 supply power HVDD and supply power LVDD to the integrated circuit device. The circuit arranged in the high withstand voltage region operates with the power supply HVDD from the power supply unit 910, and the internal circuit arranged in the low withstand voltage region operates with the supply power LVDD from the power supply unit 912.

  However, in this comparative example, since it is necessary to provide two power supply units 910 and 912 (power supply circuit) outside, the system configuration is complicated.

  In contrast, in the present embodiment, as shown in FIG. 1, the regulator circuit 11 arranged in the high withstand voltage region generates the supply power supply voltage LVDD and supplies it to the internal circuit. Therefore, it is not necessary to provide the power supply unit 912 as shown in FIG. 2, and the system configuration can be simplified.

  Further, in the integrated circuit device, it is desirable that the high breakdown voltage transistors are arranged in one place as much as possible without being dispersed. In this respect, in the present embodiment, the regulator circuit 11 is arranged in the high breakdown voltage region together with other elements (transistors, resistors) formed in the high breakdown voltage region, so that the layout efficiency can be improved.

  In many cases, an electrostatic protection element (an electrostatic protection diode, an electrostatic protection resistance element, or the like) is disposed in the high breakdown voltage region. If the regulator circuit 11 is formed in the high breakdown voltage region as in the present embodiment, the regulator circuit 11 is disposed in the vicinity of the electrostatic protection element, or the electrostatic protection element in the high breakdown voltage region is used as the protection element of the regulator circuit 11. it can. Therefore, the ESD tolerance of the regulator circuit 11 can be increased, and a situation in which the transistors constituting the regulator circuit 11 are electrostatically damaged can be effectively prevented. Thereby, reliability can be improved.

2. Connection of Pad to Output Terminal of Regulator Circuit In FIG. 3, the output terminal RQ of the regulator circuit 11 is connected to the pad 42 which is an external terminal of the integrated circuit device. The output terminal RQ is connected to a power line (supply power LVDD) of the internal circuit in the low withstand voltage region.

  In FIG. 3, as a protection element against ESD (static electricity) to the output terminal RQ of the regulator circuit 11, an electrostatic protection diode DI (an electrostatic protection element in a broad sense) disposed in the high withstand voltage region is used. Here, the diode DI can be realized by, for example, a PN junction formed at the junction surface between the N-type diffusion region and the P-type well.

  In FIG. 3, a capacitor CS for stabilizing the supply power supply voltage LVDD (adjusted voltage VRG) from the regulator circuit 11 is connected to the pad 42.

  For example, when the regulator circuit 11 has a circuit configuration with a slow response speed, it cannot respond immediately to a sudden current consumption in the internal circuit as a load circuit, but responds slowly. Therefore, in FIG. 3, a pad 42 which is an external terminal is provided, and a capacitor CS for stabilizing the supply power supply voltage LVDD (adjusted voltage VRG) can be connected to the pad 42. By connecting such a capacitor CS, it becomes possible to cope with a rapid current consumption in the internal circuit by charge discharge from the CS.

  When the pad 42 as shown in FIG. 3 is provided, a situation occurs in which ESD from the outside is applied to the output terminal RQ of the regulator circuit 11 via the pad 42. When ESD is applied in this way, the transistor constituting the regulator circuit 11 may be electrostatically damaged.

  In this regard, in FIG. 3, an electrostatic protection diode DI disposed in the high breakdown voltage region is used as a protection element against ESD to the output terminal RQ. Therefore, even when the pad 42 for connecting the capacitor CS for stabilizing the power supply is provided, it is possible to effectively prevent a situation in which the transistor constituting the regulator circuit 11 is electrostatically damaged and improve the reliability.

3. Arrangement of Regulator Circuit in I / O Region FIG. 4 shows a layout example of an integrated circuit device. The integrated circuit device of FIG. 4 can be applied to products such as a gate array and an embedded array.

  The integrated circuit device has an internal region (core region) and an I / O region. It also has a pad area. Here, the I / O region is formed outside the inner region. Specifically, the I / O region is formed so as to surround the inner region (four sides). The pad area is formed outside the I / O area. Specifically, the pad region is formed so as to surround the periphery (four sides) of the I / O region. Note that the pads arranged in the pad area may be arranged in the I / O area or the like. In this case, the pad area becomes unnecessary.

  An internal circuit (core circuit) of the integrated circuit device is arranged in the internal region. A plurality of I / O cells (input buffer, output buffer, input / output buffer, power supply cell, etc.) are arranged in the I / O area. Specifically, for example, a plurality of I / O cells are arranged side by side so as to surround the outer periphery (each side) of the internal circuit. Each pad connected to each I / O cell is arranged in the pad area. Note that the arrangement of the internal region, the I / O region, and the pad region, and the arrangement of the I / O cell and the pad are not limited to those shown in FIG. 4, and various modifications can be made.

  In FIG. 4, the regulator circuit 11 (power supply circuit) is disposed (formed) in the I / O region of the integrated circuit device. Specifically, the regulator circuit 11 is formed by a transistor (high voltage transistor) prepared for an I / O cell and disposed in the I / O region. In other words, the regulator circuit 11 is made into a cell in the same manner as the I / O cell and arranged in the I / O region. The cell of the regulator circuit 11 in this case can be made the same size as, for example, an I / O cell (at least one of a plurality of I / O cells).

  For example, as a method of a comparative example in which a power supply circuit such as the regulator circuit 11 is arranged in an integrated circuit device, the power supply circuit is made into a macroblock, and this macroblock is arranged in a corner portion of the integrated circuit device, or in an I / O area. A method of arranging in a region including a part is conceivable.

  However, in the arrangement of this comparative example, the pin arrangement is restricted, and it becomes difficult to secure the degree of freedom of pin arrangement for the customer of the custom product.

  On the other hand, according to the integrated circuit device of FIG. 4, the regulator circuit 11 can be arranged at an arbitrary position in the I / O region. Accordingly, it is possible to secure the degree of freedom of pin arrangement for customers of custom products and improve the product power.

  FIG. 5 shows a layout example of the I / O cell. In this I / O cell, a Zener diode that functions as an electrostatic protection diode is arranged. In the I / O cell, an N-type driver and a P-type driver for driving a signal line connected to the pad are arranged. These N-type drivers and P-type drivers are transistors having a very large transistor size compared to other transistors in the I / O cell. An input buffer and a pre-driver are arranged in the I / O cell. Here, the input buffer includes a pull-up resistor element (pull-up transistor), a pull-down resistor element (pull-down transistor), an electrostatic protection resistor element, and the like. The pre-driver includes a transistor for driving an N-type driver and a P-type driver. Further, control logic is disposed in the I / O cell, and this control logic includes various logic circuits for controlling the pre-driver and the input buffer.

  In FIG. 5, the Zener diode of the I / O cell, the N-type driver, the P-type driver, the P-type input buffer transistor, the N-type input buffer transistor, the P-type pre-driver transistor, and the N-type pre-driver transistor are In the high breakdown voltage region (HVDD region). On the other hand, the N-type control logic transistor and the P-type control logic transistor are formed in a low breakdown voltage region (LVDD region). That is, at least a part of the I / O cell is formed by a high voltage transistor. By configuring the high withstand voltage region and the low withstand voltage region in this way, it is possible to reduce as much as possible the boundary of the structure for forming the high withstand voltage region and the low withstand voltage region (for example, gate oxide film pressure). In addition, it is possible to reduce the boundaries of the structures (well boundaries and the like) for forming the N-type and P-type regions as much as possible, and the present invention can be easily implemented with a simpler structure.

  In this embodiment, as shown in FIG. 5, the regulator circuit 11 is formed by using an element (such as a high breakdown voltage transistor) disposed in the high breakdown voltage region for the I / O cell. For example, a P-type output transistor (TQ2 in FIG. 11) of the regulator circuit 11 to be described later is formed by a P-type driver (high voltage transistor) in FIG. Further, the resistance element (RP in FIG. 11) included in the regulator circuit is formed by the resistance element for electrostatic protection in FIG. The other transistors (TQ1, TA1 to TA9, etc. in FIG. 11) constituting the regulator circuit 11 are formed by transistors (high voltage transistors) arranged in the input buffer, predriver, etc. in FIG. As shown in FIG. 6, a modification in which no Zener diode is arranged is also possible. Further, although there is no distinction between high withstand voltage / low withstand voltage in the transistors in the integrated circuit device, when using the regulator circuit of the present invention, it is not necessary to be arranged in the high withstand voltage region.

  As described above, in this embodiment, the regulator circuit 11 is formed by using elements such as transistors and resistors arranged in the I / O cell. Therefore, as shown in FIG. 4, the regulator is placed at an arbitrary position in the I / O region. The circuit 11 can be arranged. As a result, the degree of freedom of pin arrangement and the like can be improved, the ESD breakdown voltage can be increased, and the reliability can be improved.

  A plurality of regulator circuits may be formed in the I / O region, and the plurality of regulator circuits may supply adjustment voltages to the internal circuits in parallel. Further, when the internal circuit includes a plurality of circuit blocks (CPU, RTC, memory, etc.), at least one regulator circuit among the plurality of regulator circuits supplies a regulated voltage (supply) to each circuit block of the plurality of circuit blocks. A power supply voltage LVDD) may be supplied. Further, when a plurality of well regions are formed in the internal region, at least one regulator circuit of the plurality of regulator circuits is adjusted for each divided region circuit divided into one or a plurality of well regions. A voltage (supply power supply voltage LVDD) may be supplied.

4). Configuration of Regulator Circuit FIG. 7 shows a configuration example of the regulator circuit of this embodiment. This regulator circuit is a circuit that generates a regulated voltage VRG (supply power supply voltage LVDD) obtained by stepping down a power supply voltage HVDD (second power supply in a broad sense), and includes a differential amplifier circuit 30 and an output circuit 40. In the differential amplifier circuit 30, the reference voltage VREF is input to the first input terminal IT1 (one of the non-inverting input terminal and the inverting input terminal). Further, the adjustment voltage VRG output from the regulator circuit is input to the second input terminal IT2 (the other of the non-inverting input terminal and the inverting input terminal). The differential amplifier circuit amplifies the voltage difference between the reference voltage VREF and the adjustment voltage VRG, and outputs the amplified voltage to the output terminal DQ. The output circuit 40 (driver circuit) is connected to the output terminal DQ of the differential amplifier circuit 30, and generates and outputs the adjustment voltage VRG based on the amplified voltage from the differential amplifier circuit 30.

  The output circuit 40 is provided between the output terminal RQ of the regulator circuit and the power supply VSS (first power supply in a broad sense), and has an N-type (connected to the output terminal DQ of the differential amplifier circuit 30 at its gate. In a broad sense, it includes a first output transistor TQ1 (drive transistor) of the first conductivity type. Also, a P-type (second conductivity type in a broad sense) second, which is provided between the power supply HVDD (second power supply) and the output terminal RQ and whose gate is connected to the output terminal DQ of the differential amplifier circuit 30. Output transistor TQ2 (drive transistor).

  More specifically, the differential amplifier circuit 30 includes a first output to which a differential section 32 having first and second input terminals IT1 and IT2 and a first output terminal Q1 of the differential section 32 are connected. And a second output unit 36 to which the second output terminal Q2 of the differential unit 32 is connected. These output units 34 and 36 are controlled so that the same bias current flows, for example, by a current mirror or the like, and the output terminal DQ of the output unit 36 is connected to the output circuit 40. The configuration of the differential amplifier circuit 30 is not limited to the configuration of FIG. 7, and various modifications can be made.

  FIG. 8 shows a regulator circuit of a comparative example. In this regulator circuit, the adjustment voltage VRG at the output terminal RQ is divided by the resistance elements RA and RB. A voltage obtained by dividing the adjustment voltage VRG by the resistance elements RA and RB is input to the non-inverting input terminal of the operational amplifier 900 (differential amplifier circuit), and the reference voltage VREF is input to the inverting input terminal. The operational amplifier 900 controls the gate of the output transistor TR.

  In the comparative example of FIG. 8, in consideration of the characteristics of the differential pair transistor (transistor whose non-inverted / inverted input terminal is connected to its gate) of the operational amplifier 900 and the response time obtained from these characteristics, the reference The voltage VREF is determined, and the voltage division ratio by the resistance values ra and rb of the resistance elements RA and RB is determined based on the reference voltage VREF.

  However, in the configuration of this comparative example, a constant current always flows through the resistance elements RA and RB regardless of the consumption current (operating current) of the load circuit (load) connected to the output terminal RQ of the regulator circuit. , Useless power is consumed.

  In this case, if it is a product group in which the substrate configuration itself can be freely designed, such as a full custom product, for example, by using elements having a high resistance value per unit area as the resistance elements RA and RB, RA, It is also possible to reduce the current flowing through RB.

  However, in a semi-custom product, particularly a gate array, the number of elements that can be provided on the substrate is limited, and the resistance value of the resistance elements that can be used as RA and RB is limited. As a result, current consumption in RA and RB becomes very large.

  In contrast, in the present embodiment of FIG. 7, the voltage obtained by dividing the adjustment voltage VRG (supply power supply voltage LVDD) is not fed back, but the adjustment voltage VRG itself is fed back to the differential amplifier circuit 30. That is, the adjustment voltage VRG is input to the second input terminal IT2 of the differential amplifier circuit 30. As a result, the differential amplifier circuit 30 operates so that the reference voltage VREF and the adjustment voltage VRG become the same voltage.

  In this case, when the current consumption of the load circuit connected to the output terminal RQ of the regulator circuit becomes extremely small, the adjustment voltage VRG is raised to the power supply voltage HVDD. In order to prevent this, in the present embodiment, an N-type output transistor TQ1 that functions as a variable resistance element is provided instead of the resistance elements RA and RB as shown in FIG. 8, so that the adjustment voltage VRG becomes larger than a predetermined voltage. It is preventing. The output terminal DQ of the differential amplifier circuit 30 is commonly connected to the gates of the N-type output transistor TQ1 and the P-type output transistor TQ2.

  Therefore, when the consumption current of the load circuit is reduced and the adjustment voltage VRG is increased, the voltage at the output terminal DQ of the differential amplifier circuit 30 is increased to prevent the adjustment voltage VRG from increasing. As a result, the on-resistance value of the P-type output transistor TQ2 increases and the on-resistance value of the N-type output transistor TQ1 decreases (the current flowing through TQ1 increases).

  On the other hand, when the consumption current of the load circuit increases and the adjustment voltage VRG drops, the voltage at the output terminal DQ of the differential amplifier circuit 30 drops to prevent the voltage drop of the adjustment voltage VRG. As a result, the on-resistance value of the P-type output transistor TQ2 decreases and the on-resistance value of the N-type output transistor TQ1 increases (the current flowing through TQ1 decreases).

  For example, in the comparative example of FIG. 8, since a constant current always flows through the resistance elements RA and RB, useless current is consumed. On the other hand, in this embodiment, an N-type output transistor TQ1 is provided in which the output terminal DQ of the differential amplifier circuit 30 is connected to the gate thereof, and this TQ1 functions as a variable resistance element. Therefore, when the consumption current of the load circuit is large, the on-resistance value of the N-type output transistor TQ1 increases, so that the current flowing to the TQ1 side decreases, and a large amount of current can be supplied to the load circuit side. Efficient current supply to the load circuit can be realized.

  In the comparative example of FIG. 8, since VRG = {(ra + rb) / rb} × VREF, variations in the resistance values ra and rb of the resistance elements RA and RB and temperature characteristics adversely affect the generation of the adjustment voltage VRG. End up.

  On the other hand, in this embodiment, the adjustment voltage VRG itself is fed back to the input terminal IT2 of the differential amplifier circuit 30. That is, the reference voltage VREF and the adjustment voltage VRG are directly compared in the differential amplifier circuit 30. Therefore, there is an advantage that the variation of the resistance element and the temperature characteristic do not adversely affect the adjustment voltage VRG.

  1 and 4, the regulator circuit arranged in the integrated circuit device is preferably a circuit having the configuration shown in FIG. 7, but may be a circuit of a comparative example as shown in FIG.

5. Detailed Configuration of Regulator Circuit FIG. 9 shows a detailed configuration example of the regulator circuit. The regulator circuit is not limited to the configuration shown in FIG. 9, and various modifications such as changing the connection relationship and adding other circuit elements are possible.

  In FIG. 9, the differential section 32 includes a P-type transistor TA1 for generating a bias current provided between the power supply HVDD and the node NA1. A P-type transistor TA2 provided between the nodes NA1 and NA2 whose gate is the input terminal IT1, and a P-type transistor provided between the nodes NA1 and NA3 and whose gate is the input terminal IT2. Contains TA3. Further, an N-type transistor TA4 provided between the node NA2 and the power supply VSS (GND) and having a gate and a drain connected to the node NA2, and provided between the node NA3 and the power supply VSS, and having a gate and a drain connected to the node. N-type transistor TA5 connected to NA3 is included.

  The output unit 34 is provided between the power supply HVDD and the node NA4, and has a gate connected to the node NA4, a P-type transistor TA6 connected between the node NA4 and the power supply VSS, and a gate connected to the node NA2. N-type transistor TA7 connected is included. The output unit 36 is provided between the power supply HVDD and the node NA5, and has a gate connected to the node NA4, a P-type transistor TA8, and is provided between the node NA5 and the power supply VSS. N type transistor TA9 connected is included.

  According to the regulator circuit having the configuration shown in FIG. 9, since the number of poles can be reduced to, for example, one, it is possible to prevent the circuit from oscillating due to external noise or the like and to realize stable operation.

  FIG. 10 shows a simulation result of the regulator circuit of FIG. In FIG. 10, the power supply voltage HVDD is 5 V, and the load circuit (for example, a 4000 gate circuit) connected to the output terminal RQ of the regulator circuit is stopped (stationary) during the period 0 to 1 μs and the period 7 to 13 μs. In 1 to 7 μs, the load circuit operates at 100 MHz.

  In the period 0 to 1 μs, since the load circuit is stopped, the output terminal DQ of the differential amplifier circuit 30 is stabilized at a voltage close to the power supply voltage HVDD. Therefore, since the gate voltage of the N-type output transistor TQ1 is increased, the on-resistance value ron of TQ1 is a small value.

  When time = 1 μs and the load circuit starts operation, rapid power consumption in the load circuit starts, but the regulator circuit cannot follow this. Then, the voltage stabilizing capacitor CS connected to the output terminal RQ of the regulator circuit starts discharging, and tries to maintain the adjustment voltage VRG (supply power supply voltage LVDD).

  When the charge of the capacitor CS continues to be discharged and the adjustment voltage VRG drops as shown by A1 in FIG. 10, the voltage at the output terminal DQ of the differential amplifier circuit 30 becomes slightly delayed from this rapid current consumption as shown by A2. Start to descend. As a result, the on-resistance value of the P-type output transistor TQ2 decreases and the on-resistance value ron of the N-type output transistor TQ1 increases as indicated by A3.

  Thereafter, when the adjustment voltage VRG becomes a specified voltage as shown by A4 in FIG. 10 due to the impedance value of the load circuit and the ON resistance value of the P-type output transistor TQ2, the change in the voltage of the output terminal DQ changes as shown by A5. finish.

  When time = 7 μs and the load circuit is stopped, the impedance value in the load circuit increases rapidly, so that the adjustment voltage VRG increases as indicated by A6. At this time, as indicated by A7, the voltage at the output terminal DQ of the differential amplifier circuit 30 starts to rise. As a result, the on-resistance value of the P-type output transistor TQ2 increases and the on-resistance value ron of the N-type output transistor TQ1 decreases as indicated by A8. Thereby, a rise in the voltage of the output terminal RQ of the regulator circuit is suppressed.

  Thus, in the regulator circuit of the present embodiment, when the operation of the load circuit starts, the on-resistance value ron of the N-type output transistor TQ1 increases as indicated by A3 in FIG. As a result, the current flowing to the N-type output transistor TQ1 side decreases while the current flowing from the power supply HVDD to the load circuit side increases. Therefore, more current can be supplied to the load circuit side.

  When the operation of the load circuit stops, the voltage at the output terminal DQ of the differential amplifier circuit 30 increases as indicated by A7. As a result, the on-resistance value of the P-type output transistor TQ2 increases, and current consumption in the output circuit 40 is suppressed.

  In this embodiment, in order to prevent unnecessary current consumption in the output circuit 40, the transistor size (W / L) of the P-type output transistor TQ2 is increased and the transistor size of the N-type output transistor TQ1 is decreased. Yes. Specifically, the transistor size of TQ1 is set to 1/10 or less, more preferably 1/50 or less, of the transistor size of TQ2. For example, when the transistor size of TQ2 is W / L = 1500, the transistor size of TQ1 is set to, for example, about W / L = 17.

6). Modified Example of Regulator Circuit (1) First Modified Example FIG. 11 shows a first modified example of the regulator circuit. In FIG. 11, the regulator circuit includes a resistance element RP for electrostatic protection provided between the input terminal IT2 and the output terminal RQ. This resistance element RP can be realized by using, for example, a well resistance.

  In FIG. 11, the integrated circuit device includes a regulator circuit according to the present embodiment and an internal circuit 46 (core circuit) that operates by supplying the adjustment voltage VRG from the regulator circuit as the supply power supply voltage (LVDD). The internal circuit 46 can include, for example, a CPU, an RTC (real time clock), a display driver, a memory, an interface circuit, or various logic circuits. The integrated circuit device also includes a pad 42 (external terminal) to which the output terminal of the regulator circuit is connected. The pad 42 is connected to a capacitor CS for stabilizing the adjustment voltage generated by the regulator circuit. The pad 42 is connected to a power line (supply power LVDD) of the internal circuit 46. A modification in which the capacitor CS is built in the integrated circuit device is also possible.

  The regulator circuit having the configuration shown in FIG. 11 has the advantage that the number of poles is small, the oscillation is difficult, and the operation is stable. On the other hand, the response speed is low as indicated by A1, A4, and A6 in FIG. There are advantages. That is, it cannot respond immediately to a sudden current consumption in the internal circuit 46 as a load circuit, but responds slowly.

  For this reason, in FIG. 11, a pad 42 as an external terminal is provided, and a capacitor CS for stabilizing the adjustment voltage VRG can be connected to the pad 42. If such a capacitor CS is connected, it is possible to cope with a rapid current consumption in the internal circuit 46 by charge discharge from the CS. For example, FIG. 12 shows the simulation results of the transient characteristics of the adjustment voltage VRG when the capacitors CS having various capacitance values are used. As shown in FIG. 12, as the capacitance value of the capacitor CS is increased, the transient characteristic of the adjustment voltage VRG is stabilized.

  When the pad 42 as shown in FIG. 11 is provided, a situation occurs in which ESD from the outside is applied to the output terminal RQ of the regulator circuit via the pad 42. In this case, since the P-type output transistor TQ2 has a large transistor size and a large drain size, the ESD resistance is high. Further, the ESD resistance of the N-type output transistor TQ1 having a small transistor size can be improved by providing a diode for electrostatic protection between the output terminal RQ and the power source VSS (GND).

  However, this embodiment employs a configuration in which the adjustment voltage VRG is directly fed back to the input terminal IT2 of the differential amplifier circuit 30. Therefore, there is a possibility that the gate of the transistor TA3, which is the input terminal IT2, is electrostatically damaged by external ESD.

  In this regard, in FIG. 11, since the electrostatic protection resistance element RP is provided between the output terminal RQ and the input terminal IT2 (the gate of the transistor TA3), such electrostatic breakdown can be effectively prevented. .

(2) Second Modification FIG. 13 shows a second modification of the regulator circuit. In FIG. 13, the differential section 32 includes an N-type transistor TA10 that is provided between the node NA2 and the power source VSS and is turned on / off based on a control signal ENX (IENX). Further, it includes an N-type transistor TA11 which is provided between the node NA3 and the power supply VSS and is turned on / off based on a control signal ENX (IENX). “X” means negative logic.

  The output circuit 40 includes an N-type output state control transistor TQC1 which is provided between the output transistor TQ1 and the power supply VSS and is turned on / off based on a control signal ENX (IEN). Further, it includes a P-type output state control transistor TQC2 provided between the power supply HVDD and the output terminal DQ of the differential amplifier circuit 30 and turned on / off based on the control signal ENX (IEN).

  For example, when the control signal ENX becomes L level (active) and the regulator circuit is set to the enable state, the signal IENX becomes L (low) level and the signal IEN becomes H (high) level, so that the transistors TA10, TA11, TQC2 is turned off, and transistor TQC1 is turned on. Therefore, the circuit of FIG. 13 has a circuit configuration equivalent to that of FIG.

  On the other hand, when the signal ENX becomes H level (inactive) and the regulator circuit is set to the disabled state, the transistors TA10, TA11, and TQC2 are turned on, and the transistor TQC1 is turned off. When the transistors TA10 and TA11 are turned on, the nodes NA2 and NA3 (Q1 and Q2) become L level, so that the transistors TA4, TA5, TA7, and TA9 are turned off. Therefore, the current flowing in the differential section 32 and the output sections 34 and 36 can be cut off, and the power consumption can be reduced.

  Further, when the transistor TQC2 is turned on, the node NA5 (DQ) becomes an H level, and the transistor TQ2 is turned off. Therefore, the current flowing from the power supply HVDD via the transistor TQ2 can be cut off. Further, when the transistor TQC1 is turned off, the current flowing from the output terminal RQ to the power source VSS can be cut off. Therefore, the current flowing in the output circuit 40 can be cut off, and the power consumption can be reduced.

  Further, the output terminal RQ of the regulator circuit can be set to the high impedance state by turning off the output state control transistor TQC1.

  For example, in FIG. 14, the power supply voltage HVDD (high voltage power supply) is supplied from the power supply unit 20 outside the integrated circuit device via the pad 43, and the regulator circuit 11 that receives the power supply voltage HVDD (low voltage power supply) A voltage (VRG) is generated and supplied to the internal circuit 46. The output terminal of the regulator circuit 11 is connected to an external capacitor CS through a pad 42.

  In FIG. 14, the state of the output terminal RQ of the regulator circuit 11 is controlled by the control signal ENX. In this case, the control signal ENX may be a signal input from the outside via a pad, or may be input from a control circuit (a circuit operating with a power source other than the supply power source LVDD) provided in the integrated circuit device. May be a signal to be transmitted.

  In FIG. 13, when the control signal ENX becomes H level, the output state control transistor TQC1 is turned off, and the output terminal RQ is in a high impedance state. If the output terminal RQ of the regulator circuit 11 is set to the high impedance state as described above, the supply power LVDD from the external power supply unit 26 is directly supplied to the internal circuit 46 as shown in FIG. The internal circuit 46 can be operated.

  For example, when the integrated circuit device of this embodiment is applied to a custom product, the customer of the custom product desires to supply the supply power supply voltage LVDD from the external power supply unit 26 without generating it by the regulator circuit 11. There is. Specifically, for example, it is assumed that the regulator circuit 11 is a circuit having a specification that steps down the power supply voltage HVDD of 5V to the supply power supply voltage LVDD (adjusted voltage VRG) of 3.3V. However, there are cases in which a customer of a custom product wants to operate the internal circuit 46 at 2.5V instead of 3.3V in order to reduce power consumption. In this case, as shown in FIG. 15A, the control signal ENX is set to the H level, and the output terminal RQ of the regulator circuit 11 is set to the high impedance state. In this way, the supply power supply voltage LVDD from the power supply unit 26 can be directly supplied to the internal circuit 46 via the pad 42, and a wide range of customer demands can be met.

  When the integrated circuit device is set to the test mode and the internal circuit 46 is tested, it is not desirable to supply the supply power supply voltage LVDD generated by the regulator circuit 11 to the internal circuit 46. Therefore, in such a test mode, as shown in FIG. 15B, the control signal ENX is set to the H level, and the output terminal RQ of the regulator circuit 11 is set to the high impedance state. Then, the supply power LVDD from the tester 28 (power supply unit) is supplied directly to the internal circuit 46 via the pad 42. In this way, the internal circuit 46 can be tested without being affected by the voltage error of the power supply voltage LVDD generated by the regulator circuit 11, and the test reliability can be improved.

(3) Third Modification FIG. 16 shows a third modification of the regulator circuit. In FIG. 16, the output state control transistor TQC1 provided in FIG. 13 is not provided.

  In FIG. 16, when the control signal ENX becomes H level, the output state control transistor TQC2 is turned on, and the node NA5 becomes H level. Then, the output transistor TQ2 is turned off, while the output transistor TQ1 is turned on. Thereby, the state (voltage level) of the output terminal RQ of the regulator circuit can be set to L level.

When the signal ENX becomes H level and the output terminal RQ of the regulator circuit is set to L level, no power is supplied to the internal circuit connected to the RQ, and the internal circuit is set in the low power consumption mode. (Sleep mode) can be set. When the signal ENX becomes H level, the transistors TA10 and TA11 in FIG. 16 are turned on, so that the regulator circuit can also be set to the low power consumption mode (sleep mode). Therefore, according to the third modification of FIG. 16, both the regulator circuit and the internal circuit to which power is supplied by the regulator circuit can be set to the low power consumption mode only by controlling the signal ENX. Therefore, the low power consumption mode can be realized with simple control.
(4) Fourth Modification FIG. 17 shows a fourth modification of the regulator circuit. In FIG. 17, in addition to the configuration of FIG. 13, a configuration of a voltage generation circuit 50 (reference voltage generation circuit) that generates the reference voltage VREF is added.

  The configuration and operation of the voltage generation circuit 50 will be described with reference to FIGS. The voltage generating circuit 50 is supplied with power supply voltages HVDD and VSS (first and second power supplies) and outputs a reference voltage VREF (generated voltage in a broad sense) to the output terminal VFQ. This voltage generation circuit 50 includes a P-type (second conductivity type) transistor TB1 (first resistance element in a broad sense) provided between HVDD and the output terminal VFQ. Further, it includes a P-type (second conductivity type) voltage correcting transistor TVC provided between the output terminal VFQ and the intermediate node NB1 and having the gate connected to the intermediate node NB2. In addition, an N-type (first conductivity type) transistor TB2 (second resistance element in a broad sense) provided between the intermediate nodes NB1 and NB2, and an N-type (first resistance) provided between the intermediate node NB2 and the power source VSS. A conductive type transistor TB3 (third resistance element in a broad sense).

  Here, TB2 and TB3 are N-type transistors whose power supply voltage HVDD is input to their gates. TB1 is a P-type transistor whose power supply voltage VSS is input to its gate. As shown in FIG. 17, TB1 may be a transistor whose gate voltage is controlled by a control signal ENX (IENX).

  As shown in FIG. 18B, when the power supply voltage HVDD is 5.00V, the voltages of the reference voltages VREF, NB1, and NB2 are, for example, 3.30V, 2.91V, and 1.46V, respectively. . Therefore, the drain-source voltage (absolute value) of the voltage correcting transistor TVC is VDS = 3.30-2.91 = 0.39 V, and the gate-source voltage (absolute value) is VGS = 3. 30-1.46 = 1.84V.

  As shown in FIG. 18B, when the power supply voltage HVDD drops from 5.00 V to 4.50 V, the voltages of the reference voltages VREF, NB1, and NB2 are, for example, 3.01 V, 2.55 V, and 1.27 V, respectively. become. Therefore, the drain-source voltage of the voltage correcting transistor TVC is VDS = 3.01-2.55 = 0.46V, and the gate-source voltage is VGS = 3.01-1.27 = 1.74V. become.

  For example, FIG. 19 shows the VDS-IDS characteristics of the voltage correcting transistor TVC. When the power supply voltage HVDD drops from 5.00 V to 4.50 V, the operating point of the transistor TVC moves from B1 to B2. That is, assuming that the drain-source current IDS is constant, as shown in FIG. 18B, VDS increases from 0.39 V to 0.46 V, and VGS decreases from 1.84 V to 1.74 V. This means that the operating point has moved from B1 to B2 in FIG.

  When the VGS of the transistor TVC decreases from 1.84V to 1.74V, the on-resistance value of the TVC increases. Then, in FIG. 18A, the resistance value rn that is the sum of the on-resistance values of the transistors TVC, TB2, and TB2 also increases. The increase in the resistance value rn in this way means that the reference voltage VREF that is going to decrease due to the drop in the power supply voltage HVDD returns to the voltage before the drop in the power supply voltage HVDD by the correction. That is, the voltage drop by the transistor TVC makes the voltage drop of the reference voltage VREF smaller than the voltage drop of the power supply voltage HVDD. Therefore, with respect to the voltage fluctuation of the power supply voltage HVDD from 5.00 V to 4.50 V, the voltage fluctuation of the reference voltage VREF can be kept within a range of −30% of 3.30 V.

  As shown in FIG. 18B, when the power supply voltage HVDD increases from 5.00 V to 5.50 V, the voltages of the reference voltages VREF, NB1, and NB2 are, for example, 3.60 V, 3.25 V, and 1.66 V, respectively. become. Therefore, the drain-source voltage (absolute value) of the voltage correction transistor TVC is VDS = 3.60-3.25 = 0.35 V, and the gate-source voltage (absolute value) is VGS = 3. 60-1.66 = 1.94V.

  For example, in FIG. 19, when the power supply voltage HVDD increases from 5.00 V to 5.50 V, the operating point of the transistor TVC moves from B1 to B3. That is, assuming that the drain-source current IDS is constant, VDS decreases from 0.39 V to 0.35 V and VGS increases from 1.84 V to 1.94 V, as shown in FIG. This means that the operating point has moved from B1 to B3 in FIG.

  When the VGS of the transistor TVC increases from 1.84V to 1.94V, the on-resistance value of the TVC decreases. Then, in FIG. 18A, the resistance value rn that is the sum of the on-resistance values of the transistors TVC, TB2, and TB2 also decreases. The decrease of the resistance value rn in this way means that the reference voltage VREF that is going to rise due to the rise of the power supply voltage HVDD returns to the voltage before the rise of the power supply voltage HVDD by correction. That is, the voltage increase by the transistor TVC makes the voltage increase of the reference voltage VREF smaller than the voltage increase of the power supply voltage HVDD. Therefore, the voltage fluctuation of the reference voltage VREF can be kept within a range of + 10% of 3.30V with respect to the voltage fluctuation of the power supply voltage HVDD from 5.00V to 5.50V. Therefore, eventually, the voltage fluctuation of the reference voltage VREF can be kept within the range of +/− 10% of 3.30V.

  As described above, according to FIG. 18A, a voltage generation circuit capable of generating the reference voltage VREF with a certain degree of accuracy can be realized with a simple configuration with a small number of circuit elements.

  Further, according to the voltage generation circuit of FIG. 18A, the reference voltage VREF close to the power supply voltage HVDD can be generated. For example, if the power supply voltage HVDD is 5.0V, the reference voltage VREF of 3.3V can be generated. Therefore, as shown in FIG. 17, it is possible to realize a voltage generation circuit that is an optimal combination with the regulator circuit of the present embodiment.

  That is, in the regulator circuit of FIG. 17, the same voltage as the reference voltage VREF is output as the adjustment voltage VRG. Therefore, when the reference voltage VREF is as low as 1.2 to 1.4 V, the adjustment voltage VRG output from the regulator circuit is also as low as 1.2 to 1.4 V.

  In contrast, the voltage generation circuit of FIG. 18A can generate a reference voltage VREF of, for example, 3.3V. Therefore, when the voltage generation circuit of FIG. 18A is combined with the regulator circuit of this embodiment, the adjustment voltage VRG output from the regulator circuit can be set to 3.3 V, for example, with respect to the internal circuit of the integrated circuit device. A suitable adjustment voltage VRG can be supplied.

  In FIG. 17, the voltage of the gate of the transistor TB1 is controlled by the control signal ENX (IENX). That is, the transistor TB1 is turned on when the control signal ENX is at L level, and is turned off when ENX is at H level. When the transistor TB1 is turned off, the current flowing through the voltage generation circuit 50 can be cut off, and a low power consumption mode (sleep mode) can be realized. In other words, all of the voltage generation circuit, the regulator circuit, and the internal circuit can be set to the low power consumption mode only by setting the control signal ENX to the H level.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are included in the scope of the present invention. For example, in the specification or the drawings, terms (VSS) described at least once together with different terms (first power supply, second power supply, first conductivity type, second conductivity type, generated voltage, etc.) having a broader meaning or the same meaning. , HVDD, N-type, P-type, reference voltage, etc.) can be replaced by the different terms anywhere in the specification or drawings. Further, the configurations and operations of the integrated circuit device and the regulator circuit are not limited to those described in the present embodiment, and various modifications can be made. For example, in the present embodiment, the case where the high breakdown voltage region is the I / O region has been described as an example, but the present invention is not limited to this. Further, the configuration of the regulator circuit disposed in the integrated circuit device is not limited to the circuit having the configuration described in the present embodiment. Moreover, the structure which combined the modification demonstrated by this embodiment can also be included in the scope of the present invention.

2 is an example of an integrated circuit device according to the present embodiment. The example of the integrated circuit device of a comparative example. Explanatory drawing of the method of connecting the output terminal of a regulator circuit to the pad for capacitors. 6 is a layout example of an integrated circuit device. The layout example of an I / O cell. The layout example of an I / O cell. 2 is a configuration example of a regulator circuit. The structural example of the regulator circuit of a comparative example. The detailed structural example of a regulator circuit. Simulation results of the signal at each node of the regulator circuit. The 1st modification of a regulator circuit. Simulation results of the transient characteristics of the adjustment voltage when using capacitors with various capacitance values. The 2nd modification of a regulator circuit. Explanatory drawing of the method of controlling the state of an output terminal. FIGS. 15A and 15B are also explanatory diagrams of a method for controlling the state of the output terminal. The 3rd modification of a regulator circuit. The 4th modification of a regulator circuit. 18A and 18B are diagrams illustrating the configuration and operation of a voltage generation circuit. Explanatory drawing of the operating point of a voltage generation circuit.

Explanation of symbols

VSS first power supply, HVDD second power supply, VREF reference voltage, VRG adjustment voltage,
IT1, IT2 first and second input terminals, DQ, RQ output terminals, ENX control signals,
11 regulator circuit, 20, 26 power supply, 30 differential amplifier circuit,
32 differential part, 34, 36 output part, 40 output circuit, 42, 43, pad,
46 Internal circuit, 50 Voltage generation circuit

Claims (9)

Internal circuitry,
Including at least one regulator circuit that generates a regulated voltage obtained by stepping down a power supply voltage supplied from the outside and supplies the regulated voltage to the internal circuit;
In the integrated circuit device, a low breakdown voltage region in which a low breakdown voltage transistor is disposed is formed, and a high breakdown voltage region in which a high breakdown voltage transistor is disposed is formed outside the low breakdown voltage region,
The internal circuit is disposed in the low withstand voltage region,
The integrated circuit device, wherein the regulator circuit is formed of a high breakdown voltage transistor prepared for the high breakdown voltage region and is disposed in the high breakdown voltage region. In claim 1,
An output terminal of the regulator circuit is connected to a first pad which is an external terminal of the integrated circuit device and is connected to a power supply line of the internal circuit,
An integrated circuit device, wherein an electrostatic protection element disposed in the high withstand voltage region is used as a protection element against static electricity to an output terminal of the regulator circuit. In claim 2,
An integrated circuit device, wherein a capacitor for stabilizing the adjustment voltage of the regulator circuit is connected to the first pad. In any one of Claims 1 thru | or 3,
The regulator circuit is:
A differential amplifier circuit, wherein a reference voltage is input to the first input terminal, the adjustment voltage of the regulator circuit is input to the second input terminal, and a voltage difference between the reference voltage and the adjustment voltage is amplified;
An output terminal to which the output terminal of the differential amplifier circuit is connected and outputs the adjustment voltage;
The output circuit is
A first output transistor of a first conductivity type provided between an output terminal of the regulator circuit and a first power supply, the gate of which is connected to the output terminal of the differential amplifier circuit;
An integrated circuit including a second conductivity type second output transistor provided between a second power supply and an output terminal of the regulator circuit, and having a gate connected to the output terminal of the differential amplifier circuit. Circuit device. In claim 4,
The differential amplifier circuit is:
A differential section having the first and second input terminals;
A first output unit to which a first output terminal of the differential unit is connected;
An integrated circuit device comprising a second output section to which a second output terminal of the differential section is connected. In claim 5,
The differential unit is
A first transistor of a second conductivity type for generating a bias current provided between the second power source and a first node;
A second transistor of a second conductivity type provided between the first node and the second node, the gate of which is the first input terminal;
A third transistor of a second conductivity type provided between the first node and the third node, the gate of which is the second input terminal;
A fourth transistor of a first conductivity type provided between the second node and the first power supply and having a gate and a drain connected to the second node;
A fifth transistor of a first conductivity type provided between the third node and the first power supply and having a gate and a drain connected to the third node;
The first output unit includes:
A second transistor of a second conductivity type provided between the second power supply and a fourth node, the gate of which is connected to the fourth node;
A seventh transistor of a first conductivity type provided between the fourth node and the first power supply and having a gate connected to the second node;
The second output unit includes:
An eighth transistor of the second conductivity type provided between the second power supply and the fifth node, the gate of which is connected to the fourth node;
An integrated circuit device comprising a ninth transistor of a first conductivity type provided between the fifth node and the first power supply and having a gate connected to the third node. In claim 6,
The differential unit is
A tenth transistor of a first conductivity type provided between the second node and the first power supply and turned on / off based on a control signal;
An integrated circuit device comprising an eleventh transistor of a first conductivity type provided between the third node and the first power supply and turned on / off based on a control signal. In any of claims 4 to 7,
The output circuit is
An integrated circuit comprising a first conductivity type first output state control transistor provided between the first output transistor and the first power supply and turned on / off based on a control signal. apparatus. In any of claims 4 to 8,
The output circuit is
And a second output state control transistor of a second conductivity type provided between the second power source and the output terminal of the differential amplifier circuit and turned on / off based on a control signal. Integrated circuit device.

Images