JP2007179572A - Data transfer controller and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer controller and electric apparatus for efficiently transferring data in various formats serially while suppressing an increase in a scale of a circuit. <P>SOLUTION: The data transfer control device includes an interface circuit 92 for performing interface processing with a host device 5 connected through a system bus, and a link controller 90 for analyzing a packet received through a serial bus, and outputting data having data unit of K bits to the interface circuit 92. Packetized data, which is (N×I)-byte data generated by gathering M pieces of (K+L)-bit data obtained by adding L-bit dummy data to the K-bit data, wherein L and M are variably set depending on K, is inserted in a data field of the received packet through the serial bus. The link controller 90 includes a data formatter 300 for extracting the K-bit data from the packetized data and outputting to the interface circuit 92. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data transfer control device and an electronic device.

  In recent years, high-speed serial transfer interfaces such as LVDS (Low Voltage Differential Signaling) have attracted attention as interfaces for the purpose of reducing EMI noise. In this high-speed serial transfer, the transmitter circuit transmits serialized data using differential signals, and the receiver circuit differentially amplifies the differential signal to realize data transfer.

  A general mobile phone has a first device portion provided with buttons for inputting a telephone number and characters, and a second device portion provided with a main LCD (Liquid Crystal Display), a sub LCD and a camera (CCD). And a connecting portion such as a hinge for connecting the first and second device portions. Therefore, if the data transfer between the first board provided in the first device portion and the second board provided in the second device portion is performed by serial transfer using a differential signal, the connection portion It is possible to reduce the number of wires passing through the terminal.

  By the way, there are various formats for camera data output from a camera (imaging device) such as a CCD or a CMOS. Specifically, there are formats such as YUV422, YUV420, RGB888, RGB565, RGB444, RAW6, RAW7, RAW8, RAW10, RAW12, and JPEG8. Here, YUV422 and YUV420 are input as 8-bit data (one data unit is 8-bit data), RGB888 is input as 24 bits, RGB565 is input as 16 bits, and RGB444 is input as 12 bits. RAW6, RAW7, RAW8, RAW10, and RAW12 are input as 6, 7, 8, 10, and 12-bit data, respectively, and JPEG8 is input as 8-bit data. Therefore, when the camera data is packetized and serially transferred from the second device part provided with the camera to the first device part provided with the host device, these various formats are supported. It is desirable to be able to do it.

However, when the camera data of such various formats is packetized, if the number of bits of redundant data increases, the data transfer amount on the serial bus increases. On the other hand, if the number of bits of the redundant data is set to 0 and an attempt is made to deal with the above-mentioned various formats, problems such as an increase in circuit scale are caused.
JP 2001-222249 A

  The present invention has been made in view of the above technical problems, and an object of the present invention is to realize efficient serial transfer of data in various formats while suppressing an increase in circuit scale. A data transfer control device and an electronic device including the same are provided.

  The present invention is a data transfer control device that controls data transfer, an interface circuit to which data in which one data unit is K bits (K is an integer of 2 or more) is input via an interface bus, and a serial bus A link controller that generates a packet to be transmitted via the link controller, and the link controller is obtained by adding dummy data of L bits (L is an integer of 0 or more) to the K bits of data ( A data formatter for generating packed data of (N × I) bytes (N and I are integers of 1 or more) in which M pieces (M is an integer of 1 or more) of data of K + L) bits, and the serial bus A packet generation circuit for generating a packet in which the packed data is inserted into a data field as a packet to be transmitted via The data formatter, the L and M is related to the data transfer control device for generating the packed data are variably set corresponding to the K.

  According to the present invention, (K + L) -bit data obtained by adding L-bit dummy data to K-bit data is (N × I) bytes of data collected by M pieces, Packed data in which L and M are variably set according to K is generated. The packed data is inserted (set) into the data field of a packet transmitted via the serial bus. Thus, by setting L of the packed data variably according to K, it is possible to reduce the data transfer amount on the serial bus. Also, by setting M of the packed data variably according to K, it is possible to suppress the circuit from becoming large. Therefore, according to the present invention, it is possible to realize efficient serial transfer of data in various formats while suppressing the circuit scale.

  In the present invention, the data formatter is L = 0, M = 4, N = 3 when K = 6 and I = 1, or L = when K = 7 and I = 1. 1, M = 2, N = 2, or when K = 8 and I = 1, L = 0, M = 2, N = 2, or when K = 10 and I = 1 If L = 2, M = 2, N = 3, or K = 12, I = 1, then L = 0, M = 2, N = 3, or K = 16, I = 1 If L = 0, M = 1, N = 2, or if K = 24 and I = 1, then packed data with L = 0, M = 1, N = 3 is generated. Also good. A format other than these may be adopted.

  According to the present invention, the data formatter is L = 0, M = 8, N = 3 when K = 6 and I = 2, or L = when K = 7 and I = 2. 1, M = 4, N = 2, or when K = 8 and I = 2, L = 0, M = 4, N = 2, or when K = 10 and I = 2 L = 1, M = 3, N = 2, or if K = 12, I = 2, then L = 0, M = 4, N = 3, or K = 16, I = 2 L = 0, M = 2, N = 2, or if K = 24 and I = 2, the packed data is generated so that L = 0, M = 2, and N = 3. Also good. A format other than these may be adopted.

  In the present invention, N × 8 × I = (K + L) × M may be used. However, there may be a case where N × 8 × I = (K + L) × M is not exceptional.

  In the present invention, the packet generation circuit may insert setting information for setting the M and N into a header of a packet transmitted via the serial bus.

  In this way, the format conversion of the packed data performed by the packet receiving side can be facilitated.

  Further, the present invention may include an internal register that stores setting information for setting the M and N, and the data formatter may insert the dummy data based on the setting information.

  In this way, the dummy data insertion process can be simplified. The data formatter can determine the dummy data insertion position and the like based on the count value in the bit counter and the count value in the byte counter.

  The present invention also relates to an electronic apparatus including any one of the data transfer control devices described above and one or more devices connected to the data transfer control device via the interface bus.

  The present invention also provides a data transfer control device that controls data transfer, an interface circuit that performs interface processing with a host device connected via a system bus, and a packet received via a serial bus. And a link controller that outputs to the interface circuit data in which one data unit is K bits (K is an integer of 2 or more), and the data field of the packet received via the serial bus includes: M pieces of (K + L) -bit data (M is an integer of 1 or more) gathered by adding L bits (L is an integer of 0 or more) dummy data to the K-bit data (M is an integer of 1 or more). N × I) bytes (N and I are integers of 1 or more), and the L and M are variably set according to K. Data is inserted, the link controller is related to the data transfer control device including a data formatter output from the packed data by extracting the data of K bits to said interface circuit.

  According to the present invention, (K + L) -bit data obtained by adding L-bit dummy data to K-bit data is (N × I) bytes of data collected by M pieces, Packed data in which L and M are variably set according to K is inserted into the data field of a packet received via the serial bus. Then, the data formatter extracts K-bit data from the packed data inserted in the data field of the packet and outputs it to the interface circuit. As described above, L of the packed data is variably set according to K, so that the data transfer amount on the serial bus can be reduced. Further, since M of the packed data is variably set according to K, it is possible to suppress an increase in circuit scale. Therefore, according to the present invention, it is possible to realize efficient serial transfer of data in various formats while suppressing the circuit scale.

  In the present invention, the packed data inserted into the packet is L = 0, M = 4, N = 3 when K = 6 and I = 1, or K = 7 and I = 1. In some cases, L = 1, M = 2, N = 2, or K = 8, and in I = 1, L = 0, M = 2, N = 2, or K = 10, I = When L = 1, M = 2, N = 3, or K = 12, when I = 1, L = 0, M = 2, N = 3, or K = 16, When I = 1, L = 0, M = 1, N = 2, or when K = 24, I = 1, L = 0, M = 1, N = 3. May be. A format other than these may be adopted.

  In the present invention, the packed data inserted into the packet is L = 0, M = 8, N = 3 when K = 6 and I = 2, or K = 7 and I = 2. In some cases, L = 1, M = 4, N = 2, or K = 8, and in I = 2, L = 0, M = 4, N = 2, or K = 10, I = 2, L = 1, M = 3, N = 2, or K = 12, if I = 2, L = 0, M = 4, N = 3, or K = 16, When I = 2, L = 0, M = 2, N = 2, or when K = 24, I = 2, L = 0, M = 2, and N = 3. May be. A format other than these may be adopted.

  In the present invention, N × 8 × I = (K + L) × M may be used. However, there may be a case where N × 8 × I = (K + L) × M is not exceptional.

  In the present invention, setting information for setting the M and N is inserted in the header of the packet received via the serial bus, and the link controller analyzes the header of the received packet and sets the setting. A packet analysis circuit that extracts information from a packet header may be included, and the data formatter may extract the K-bit data from the packed data based on the setting information.

  In this way, the process of extracting K-bit data from the packed data can be facilitated.

  In the present invention, setting information for setting the M and N is inserted in the header of the packet received via the serial bus, and the link controller analyzes the header of the received packet and sets the setting. A packet analysis circuit that extracts information from a packet header may be included, and the data formatter may delete the dummy data based on the setting information.

  In this way, the dummy data deletion process can be simplified. The data formatter can determine the deletion position of dummy data based on the count value in the bit counter or the count value in the byte counter.

  The present invention also relates to an electronic apparatus including any of the data transfer control devices described above and the host device connected to the data transfer control device via the system bus.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. System Configuration FIG. 1 shows a data transfer control device (data transfer control circuit) of this embodiment and a system configuration example thereof. In the present embodiment, a so-called bridge function between a system bus and an interface bus is realized by using the host-side and target-side data transfer control devices 10 and 30 in FIG.

  The data transfer control devices 10 and 30 are not limited to the configuration shown in FIG. 1, and some of the circuit blocks shown in FIG. 1 may be omitted, the connection form between the circuit blocks may be changed, May be added. For example, the configuration of the transceiver 20 in the host-side data transfer control device 10 may be omitted, or the configuration of the transceiver 40 in the target-side data transfer control device 30 may be omitted. Further, the data transfer control device 30 and the display driver 6 or the camera 8 (imaging device, camera device) may be configured with two chips (semiconductor chip), but may be configured with one chip. Similarly, the host device 5 (system device) and the data transfer control device 10 can be configured by one chip.

  The host (TX) side data transfer control device 10 and the target (RX) side data transfer control device 30 perform packet transfer via a serial bus of differential signals. More specifically, packets are transmitted / received by current driving or voltage driving differential signal lines of the serial bus.

  The host-side data transfer control device 10 includes an interface circuit 92 that performs interface processing with the host device 5 (CPU, baseband engine, display controller, etc.). The interface circuit 92 is connected to the host device 5 via a system bus (host bus). The system bus can be used as an RGB interface bus, an MPU (Micro Processor Unit) interface bus, a serial interface bus, or a camera interface bus. When used as an RGB interface bus, the system bus can include signal lines such as a horizontal synchronization signal, a vertical synchronization signal, a clock signal, and a data signal. When used as an MPU interface bus, the system bus can include signal lines such as a data signal, a read signal, a write signal, an address 0 signal (command / parameter identification signal), and a chip select signal. When used as a serial interface bus, the system bus can include signal lines for a serial interface chip select signal, read / write signal, address 0 signal, data signal, clock signal, and the like. When used as a camera interface bus, the system bus can include signal lines such as a horizontal synchronization signal, a vertical synchronization signal, a clock signal, and a data signal for the camera interface.

  The host-side data transfer control device 10 includes a link controller 90 (link layer circuit) that performs link layer processing. The link controller 90 generates a packet (request packet, stream packet, etc.) that is transferred to the target-side data transfer control device 30 via the serial bus (LVDS), and performs processing for transmitting the generated packet. Specifically, a transmission transaction is activated to instruct the transceiver 20 to transmit the generated packet.

  The host-side data transfer control device 10 includes a transceiver 20 (PHY) that performs physical layer processing and the like. The transceiver 20 transmits the packet instructed by the link controller 90 to the target-side data transfer control device 30 via the serial bus. The transceiver 20 also receives a packet from the target-side data transfer control device 30. In this case, the link controller 90 analyzes the received packet and performs a link layer (transaction layer) process.

  The target-side data transfer control device 30 includes a transceiver 40 (PHY) that performs physical layer processing and the like. The transceiver 40 receives a packet from the host-side data transfer control device 10 via the serial bus. The transceiver 40 also transmits a packet to the host-side data transfer control device 10. In this case, the link controller 100 generates a packet to be transmitted and instructs transmission of the generated packet.

  The target-side data transfer control device 30 includes a link controller 100 (link layer circuit). The link controller 100 receives a packet from the host-side data transfer control device 10 and performs a link layer (transaction layer) process for analyzing the received packet.

  The target-side data transfer control device 30 includes a display driver 6 that drives the display panel 7 (LCD or the like) and an interface circuit 110 that performs interface processing with the camera 8 (one or a plurality of devices in a broad sense). The interface circuit 110 generates various interface signals and outputs them to the display driver 7 and the like via the interface bus. Various interface signals are received from the camera 8 via the interface bus. The interface circuit 110 can include an RGB interface circuit, an MPU interface circuit, a serial interface circuit, a camera interface circuit (first to Nth interface circuits in a broad sense), and the like.

  When the system bus on the host side (host device 5) is used as the RGB interface bus, the interface bus on the target side (display driver 6) is also used as the RGB interface bus. The interface circuit 110 (RGB interface circuit) generates RGB interface signals and outputs them to the display driver 6 (device in a broad sense). When the host-side system bus is used as the MPU interface bus, the target-side interface bus is also used as the MPU interface bus. The interface circuit 110 (MPU interface circuit) generates an MPU interface signal and outputs it to the display driver 6. When the system bus on the host side is used as the camera interface bus, the interface bus on the target side is also used as the camera interface bus. The target-side interface circuit 110 (camera interface circuit) receives an interface signal from the camera 8. On the other hand, the host-side interface circuit 92 (camera interface circuit) generates a camera interface signal and outputs it to the host device 5. The interface form of the system bus and interface bus may be different.

  By providing the interface circuits 92 and 110 as described above, in this embodiment, a bus bridge function between the system bus on the host side and the interface bus on the target side is realized.

  That is, when the system bus is used as an RGB interface bus, the RGB interface signal output from the host device 5 is transmitted to the target side by packet transfer via the differential signal serial bus. Then, the target-side interface circuit 110 outputs an RGB interface signal corresponding to the RGB interface signal from the host side to the display driver 6. When the system bus is used as an MPU interface bus, the MPU interface signal output from the host device 5 is transmitted to the target side by packet transfer via the differential signal serial bus. Then, the target-side interface circuit 110 outputs an MPU interface signal corresponding to the MPU interface signal from the host side to the display driver 6.

  Further, when the system bus is used as a camera interface bus, the target side transmits the camera interface signals (data signal, vertical synchronization signal, horizontal synchronization signal) output from the camera 8 by packet transfer via the differential signal serial bus. Tell the host. Then, the host-side interface circuit 92 outputs a camera interface signal corresponding to the camera interface signal from the target side to the host device 5.

  In FIG. 1, the data transfer control device 10 to which the host device 5 is connected is the host side (TX), and the data transfer control device 30 to which the camera 8 is connected is the target side (RX). The form is not limited to this. For example, as shown in FIG. 2, the data transfer control device 10 to which the camera 8 is connected may be on the host side (TX), and the data transfer control device 30 to which the host device 5 is connected may be on the target side (RX). .

  That is, in this embodiment, the host-side data transfer control device has a clock generation circuit (PLL circuit), and outputs the generated clock to the target-side data transfer control device. In the case of FIG. 1, the data transfer control device 10 on the host side outputs the differential clock signal CLK +/− generated by the clock generation circuit to the data transfer control device 30 on the target side. Then, the target-side data transfer control device 30 generates a differential strobe signal STB +/− based on this CLK +/−. Then, the data transfer control device 30 on the target side synchronizes with the edge (rising edge or falling edge) of STB +/− to send the differential data signal DTI +/− (camera data) to the data transfer control device on the host side. 10 is output.

  On the other hand, in the case of FIG. 2, the host-side data transfer control device 30 generates a differential clock signal CLK +/− by a clock generation circuit. Then, the host-side data transfer control device 30 outputs a differential data signal DTO +/− (camera data) to the target-side data transfer control device 10 in synchronization with the CLK +/− edge.

  A serial transfer method using differential signals DTO +/−, CLK +/−, DTI +/−, and STB +/− will be described in detail later with reference to FIG.

2. Camera Data Format Conversion Camera data output from a camera such as a CCD or CMOS has various formats such as YUV422, YUV420, RGB888, RGB565, RGB444, RAW6, RAW7, RAW8, RAW10, RAW12, and JPEG8. In these formats, the number of bits of data units of input data is different such as 6, 7, 8, 10, 12, 16, 24 bits (K bits in a broad sense).

  However, a packet transferred via the serial bus is composed of data in byte units or word units (in a broad sense, I byte units). Therefore, in order to packetize camera data and transfer it serially, it is necessary to convert the format of camera data of 6, 7, 8, 10, 12, 16 or 24 bits to data in byte units or word units (I byte units). There is.

  FIGS. 3A and 3B and FIGS. 4A and 4B show methods of the first and second comparative examples for realizing such format conversion. FIGS. 3A to 4B are examples in the case where the data (camera data) to be subjected to format conversion is 10 bits (RAW10). FIGS. 3A and 3B show an example of converting this 10-bit unit data into byte-unit data. FIGS. 4A and 4B show 10-bit unit data in 2-byte units ( This is an example in the case of conversion to data in word units.

  In FIG. 3A and the like, (101) means the first bit of the first data (10-bit data), and (102) means the second bit of the first data. (201) means the first bit of the second data, and (202) means the second bit of the second data. Therefore, (101) to (110) represent 1 to 10 bits of the first data, and (201) to (210) represent 1 to 10 bits of the second data. The same applies to (301) to (310), (301) to (410), and the like.

In the first comparative example, as shown in FIGS. 3A and 4A, unpacked format conversion in which redundant data is inserted is performed. That is, in FIG.
) To (108) are set as the first byte data, and (109) and (110) and 6-bit redundant data (×) are set as the second byte data. Also, (201) to (208) are set as the third byte data, and (209) and (210) and 6-bit redundant data are set as the fourth byte data.

  Thus, in the first comparative example, it is necessary to transfer 6-bit redundant data every time two pieces of byte data are transferred. Therefore, every time VGA screen data is transferred, redundant data of 640 × 480 × 6/8/1024 = 225 Kbytes must be transferred. For this reason, the data transfer amount (traffic amount) of the serial bus becomes excessive, and the data transfer becomes inefficient.

  On the other hand, in the second comparative example, as shown in FIGS. 3B and 4B, packed format conversion in which no redundant data is inserted is performed. In the second comparative example, redundant data is not inserted, so that the data transfer amount of the serial bus can be reduced as compared with the first comparative example. However, in the second comparative example, the circuit scale of the data formatter (decode circuit) and the counter becomes large, which causes problems such as an increase in the scale of the data transfer control device and a complicated process. In particular, if all of the above-mentioned various formats are to be supported, the problem of a large data transfer control device and complicated processing becomes more serious.

3. Configuration Example of Data Transfer Control Device FIG. 5 and FIG. 6 show a configuration example of the data transfer control device of this embodiment that solves the above problems. 5 and 6 may be omitted, the connection form between the circuit blocks may be changed, or other circuit blocks different from those in FIGS. 5 and 6 may be added.

  FIG. 5 is a configuration example of the data transfer control device 30 on the target side (host side in the case of FIG. 2). In FIG. 5, an interface circuit 110 performs interface processing with the camera 8 (device in a broad sense). The interface circuit 110 receives data through which one data unit is K bits via the interface bus. K is an integer of 2 (or 6) or more.

  Specifically, the interface circuit 110 has camera data CMDAT in which the number of bits of one data unit is 6, 7, 8, 10, 12, 16 or 24 bits (hereinafter, appropriately expressed as 6 to 24 bits). Is entered. Further, CMVREF and CMHREF corresponding to a vertical synchronization signal and a horizontal synchronization signal, and a clock signal CMCLKIN for capturing CMDAT are input.

  7A and 7B show signal waveform examples of CMDAT, CMVREF, CMHREF, and CMCLKIN when the camera data is in the 8-bit YUV format. As shown in FIG. 7A, after CMVREF becomes active (high level), CMDAT for one line is input to the interface circuit 110 every time CMHREF becomes active. As shown in FIG. 7B, CMDAT can be sampled by, for example, the rising edge of CMCLKIN. The interface circuit 110 outputs the data (camera data) sampled and taken in this way to the link controller 100. 7C and 7D are signal waveform examples when the camera data is in the JPEG format.

  The link controller 100 includes a data formatter 300, a bit counter 310, a byte counter 312, a packet generation circuit 320, a packet buffer 330, and an internal register 350. Note that some of these may be omitted.

The data formatter 300 performs data format conversion. For example, K bit (6 to 24 bits) data sequentially input from the interface circuit 110 is received, format conversion is performed, and packed data is generated. The generated packed data is output to the packet generation circuit 320 in units of 8 bits or 16 bits (I byte in a broad sense), for example.

  More specifically, the data formatter 300 collects M pieces of (K + L) -bit data obtained by adding L-bit dummy data to K-bit data (K-bit unit data). N × I) bytes of packed data are generated. L is an integer of 0 or more, M is an integer of 1 or more, and N is an integer of 1 (or 2) or more. I is an integer of 1 or more.

  In this case, in this embodiment, the data formatter 300 generates packed data in which L and M are variably set according to K (L and M change according to K). In addition, the data formatter 300 performs processing for inserting dummy data at bit positions determined based on setting information of PCS and PW (M, N) stored in the internal register 350.

  8 and 9 show examples of packed data generated by the data formatter 300. FIG. FIG. 8 shows an example in which the generated packed data is output every 1 byte (8 bits), and FIG. 9 shows an example in which it is output every 2 bytes (16 bits).

  8 and 9, DATA represents data (camera data) input in units of K bits. PW is the pack width (size of packed data). This pack width PW can be expressed as N × I bytes. In FIG. 8, PW is N bytes, and in FIG. 9, PW is N × 2 bytes (N words). PCS is the number of data in the pack (the number of K-bit data in the packed data), and can be expressed as PCS = M. The number of bits (number) of dummy data (redundant data) in FIGS. 8 and 9 can be expressed as L.

  In FIG. 8, when input data (camera data) is K = 6, 7, 8, 10, 12, 16, 24 bits, as shown by A1, A2, A3, A4, A5, A6, A7, respectively. Packed data is generated. In FIG. 9, when the input data is K = 6, 7, 8, 10, 12, 16, 24 bits, packed data as shown by B1, B2, B3, B4, B5, B6, B7, respectively. Is generated. In FIGS. 8 and 9, the bit number L of dummy data and M corresponding to the number of data in pack PCS (or N corresponding to pack width PW) change variably according to the number of bits K of input data. ing. Details of FIGS. 8 and 9 will be described later.

  The data formatter 300 includes a data buffer 302 and a dummy data insertion circuit 304. The data buffer 302 is input with data in units of K bits (8 to 24 bits), and outputs packed data in units of 8 bits or 16 bits. The dummy data insertion circuit 304 performs dummy data insertion processing that is redundant data. Specifically, based on the setting information of PCS and PW (M, N) stored in the internal register 350, the bit position (bit position on the data buffer 302) of the dummy data is determined (set), and the bit position is set. Processing for inserting dummy data (data of 0 or 1) is performed.

  The bit counter 310 (pixel counter) counts the number of data bits. The byte counter 312 counts the number of data bytes. The data formatter 300 (dummy data insertion circuit 304) then counts the number of bits from the bit counter 310, counts of the number of bytes from the byte counter 312, and PCS, PW (M, N) decoding processing is performed based on the setting information and the like, and the bit position where the dummy data is inserted is determined.

  The packet generation circuit 320 generates a packet to be transmitted via the serial bus. Specifically, a header of a packet to be transmitted is generated, and the packet is assembled by combining the header and data. The generated packet is written into the packet buffer 330 and transferred to the transceiver 40. In this case, the header generation circuit 322 generates the packet header.

  In this embodiment, as shown in FIG. 10A, the packet generation circuit 320 inserts (sets) the packed data generated by the data formatter 300 into the data field as a packet to be transmitted via the serial bus. Packet is generated. FIG. 10A shows an example in which the number of bits of input data is K = 10 and the packed data indicated by A4 in FIG. 8 is inserted into the data field.

  Note that only one piece of packed data may be inserted into the data field of the packet, or a plurality of pieces of packed data may be inserted. 10A shows an example in which the data width of the packet is 1 byte, the data width of the packet may be 2 bytes or more (I byte). When the data width of the packet is 1 byte, the packed data may be output from the data formatter 300 to the packet generation circuit 320 in units of 1 byte (8 bits). In this case, packed data as shown in A1 to A7 of FIG. 8 is used. On the other hand, when the packet data width is set to 2 bytes, the packed data may be output from the data formatter 300 to the packet generation circuit 320 in units of 2 bytes (16 bits). In this case, packed data as shown in B1 to B7 of FIG. 9 is used.

  As shown in FIG. 10B, the packet generation circuit 320 may insert setting information for setting PCS and PW (M, N) in the header of the packet. Specifically, a field for the number of in-pack data PCS and a field for the pack width PW are provided in the header of the packet. Then, PCS setting information and PW setting information are inserted into these PCS field and PW field. For example, in the case of A1 in FIG. 8, setting information of PCS = 4 and PW = 24 is inserted into the PCS field and the PW field. In the case of A2, setting information of PCS = 2 and PW = 16 is inserted into the PCS field and the PW field.

  The setting information inserted in the header of the packet does not have to be the value of the in-pack data count PCS or the pack width PW, but may be information that can set (specify) at least M and N. For example, instead of the PW value itself, a value of N (or N × I) may be used as setting information. Alternatively, L may be used as setting information instead of N, and N may be specified by M and L.

  The packet buffer 330 is a transmission packet buffer in which packets to be transmitted via the serial bus are written. That is, a packet to be transmitted via the serial bus is generated by the packet generation circuit 320, written in the packet buffer 330, and transferred to the transceiver 40. The packet buffer 330 can be configured by, for example, a FIFO (First In First Out) or a RAM. Note that the packet buffer 330 may have a ring buffer structure. A packet buffer for reception may be further provided in the link controller 100.

  The internal register 350 includes various control registers and status registers. The internal register 350 stores setting information for setting PCS and PW (M, N). Specifically, the internal register 350 includes a PCS register 352 and a PW register 354, and PCS and PW setting information is stored in each of these registers. The data formatter 300 determines the insertion bit position of the dummy data based on these PCS and PW. The packet generation circuit 320 inserts these PCS and PW into the PCS and PW fields of the packet. The setting information of PCS and PW (M, N) can be transferred from the counterpart device (host device) to the local device via the serial bus and written to the internal register 350.

  FIG. 6 shows a configuration example of the data transfer control device 10 on the host side (target side in the case of FIG. 2). As shown in FIG. 6, the link controller 90 included in the data transfer control device 10 includes a data formatter 200, a bit counter 210, a byte counter 212, a packet buffer 230, a packet analysis circuit 240, and an internal register 250. Note that some of these may be omitted.

  The packet buffer 230 is a reception packet buffer into which packets received via the serial bus are written. That is, the packet received by the transceiver 20 via the serial bus is written into the packet buffer 230. The packed data (see FIGS. 10A and 10B) set in the data field of the written packet is output to the data formatter 200. In this case, the packed data is output to the data formatter 200 in units of 8 bits or 16 bits (I bytes), for example.

  The packet buffer 230 can be configured by, for example, a FIFO or a RAM. Note that the packet buffer 230 may have a ring buffer structure. Further, the packet buffer 230 may have a double buffer configuration, or a transmission packet buffer may be further provided in the link controller 90.

  The packet analysis circuit 240 analyzes a packet received via the serial bus. Specifically, the header and data of the received packet are separated and the header is extracted. This header extraction is performed by the header extraction circuit 242.

  For example, the packet analysis circuit 240 analyzes the packet type field of the header and determines the type of the received packet (request packet, response packet, acknowledge packet) and the like. Further, the synchronization signal code field of the header is analyzed to determine whether or not the received packet includes a synchronization signal code that instructs the interface circuit 92 to generate a synchronization signal (vertical synchronization signal, horizontal synchronization signal).

  For example, in FIG. 5, when the camera 8 outputs the vertical synchronization signal CMVREF, the packet generation circuit 320 generates a packet including a synchronization signal code instructing generation of the vertical synchronization signal. When the camera 8 outputs the horizontal synchronization signal CMHREF, a packet including a synchronization signal code for instructing generation of the horizontal synchronization signal is generated. The generated packet is transferred via a serial bus. When the packet analysis circuit 240 analyzes the transferred packet and detects the code of the vertical synchronization signal, the packet analysis circuit 240 instructs the interface circuit 92 to generate and output the vertical synchronization signal SCMVREF. When the horizontal sync signal code is detected, generation and output of the horizontal sync signal SCMHREF is instructed. In this way, a bus bridge function between the interface bus and the system bus is realized.

  The packet analysis circuit 240 analyzes the header of the received packet and extracts setting information of PCS and PW (M, N). Specifically, as shown in FIG. 10B, when PCS and PW are set in the PCS field and PW field, the information of these PCS and PW is extracted.

  The internal register 250 includes various control registers and status registers. The internal register 250 stores setting information of PCS and PW (M, N) extracted by the packet analysis circuit 240. Specifically, the PCS register 252 and the PW register 254 included in the internal register 250 store PCS and PW information.

  As shown in FIGS. 10A and 10B, packed data is inserted in the data field of a packet received via the serial bus. This packed data is (N × I) byte data in which M pieces of (K + L) -bit data obtained by adding L-bit dummy data to K-bit data. The data is such that L and M (or N) are variably set according to K.

  The data formatter 200 (link controller 90) extracts K-bit (6 to 24 bits) data (camera data) from the packed data and outputs the data to the interface circuit 92. In addition, the data formatter 200 performs processing for deleting dummy data from bit positions determined based on setting information of PCS and PW (M, N) stored in the internal register 250.

  For example, when the packed data indicated by A1 in FIG. 8 is inserted in the data field, the data formatter 200 reads the data (11) to (16), (21) to (26), (31) of K = 6 bits. ) To (36) and (41) to (46) are extracted from the packed data and sequentially output to the interface circuit 92. Similarly, when the packed data shown in A2, A3, A4, A5, A6, and A7 in FIG. 8 is inserted, K = 7, 8, 10, 12, 16, and 24 bit data are extracted, respectively. Then, the data is sequentially output to the interface circuit 92. When the packed data shown in B1, B2, B3, B4, B5, B6, and B7 in FIG. 9 is inserted, K = 6, 7, 8, 10, 12, 16, and 24-bit data, respectively. Are extracted and sequentially output to the interface circuit 92.

  The data formatter 200 includes a data buffer 202 and a dummy data deletion circuit 204. The packed data is input to the data buffer 202 in units of 8 bits or 16 bits, and data in units of K bits (8 to 24 bits) is output. The dummy data deletion circuit 204 performs a deletion process of dummy data that is redundant data. Specifically, based on the setting information of PCS and PW (M, N) stored in the internal register 250, the bit position of the dummy data (bit position on the data buffer 202) is determined (set), and from the bit position Processing for deleting dummy data (data of 0 or 1) is performed.

  The bit counter 210 counts the number of data bits. The byte counter 212 counts the number of data bytes. The data formatter 200 (dummy data deletion circuit 204) then counts the number of bits from the bit counter 210, count value of the number of bytes from the byte counter 212, and PCS, PW (M, N) decoding processing is performed based on the setting information, and the bit position from which the dummy data is deleted is determined.

  The interface circuit 92 receives K-bit (6 to 24 bits) data (camera data) from the data formatter 200. Then, this data is output to the host device 5 as SCMDAT. At this time, the vertical synchronization signal SCMVREF, the horizontal synchronization signal SCMHREF, and the clock signal SCCMCLKIN having the same waveforms as those in FIGS. 7A to 7D are output to the host device 5. In this way, it is possible to perform playback processing such as CMDAT, CMVREF, and CMHREF output from the camera 8.

4). Format Conversion Method Next, the format conversion method of this embodiment will be described in detail. For example, in A1 of FIG. 8, the format of the input camera data is RAW6, and K = 6-bit data (11) to (16), (21) to (26), (31) to (36), ( 41) to (46) are input. Note that (11) means the first bit of the first data (6-bit data), and (12) means the second bit of the first data. (21) means the first bit of the second data, and (22) means the second bit of the second data. Moreover, (x) means dummy data (redundant data).

  When the number of bits K = 6 as in A1 of FIG. 8, the pack width PW = 24 and the number of data in pack PCS = 4 are set. Further, the number of bits of dummy data L = 0. Therefore, in this case, packed data of PW = 24 bits (N = 3) is generated by collecting PCS = 4 (M) pieces of 6-bit (K + L bits) data.

  In A2 of FIG. 8, the camera data format is RAW7, and K = 7-bit data (11) to (17) and (21) to (27) are input. When K = 7 as described above, PW = 16 and PCS = 2 are set. Also, the number of bits of dummy data L = 1. Therefore, in this case, packed data of PW = 16 bits (N = 2) is generated by collecting PCS = 2 (M) data of 8 bits (K + L bits).

  In the case of A2 in FIG. 8, the byte counter count value = 1 and the bit counter count value = 8, and the byte counter count value = 2 and the bit counter count value = 8. In this case, dummy data may be inserted.

  In A3 of FIG. 8, the camera data format is YUV422, YUV420, RAW8, or JPEG8, and K = 8-bit data (11) to (18) and (21) to (28) are input. If K = 8, PW = 16 and PCS = 2 are set. Further, the number of bits of dummy data L = 0. Therefore, in this case, packed data of PW = 16 bits (N = 2) is generated by collecting PCS = 2 (M) data of 8 bits (K + L bits).

  In the case of A3 in FIG. 8, the count value of the byte counter = 2 and the count value of the bit counter = 3 and 4, and the count value of the byte counter = 3 and the count value of the bit counter = 7, In the case of 8, dummy data may be inserted.

  In A4 of FIG. 8, the camera data format is RAW10, and K = 10-bit data (101) to (110) and (201) to (210) are input. When K = 10 as described above, PW = 24 and PCS = 2 are set. Further, the number of bits of dummy data L = 2. Therefore, in this case, packed data of PW = 24 bits (N = 3 bytes) is generated by collecting PCS = 2 pieces (M pieces) of 12-bit (K + L bits) data. In the case of A5 to A7 in FIG. 8 and B1 to B7 in FIG.

  In the first comparative example shown in FIGS. 3A and 4A, the number of bits of redundant data is large. For this reason, there is a problem that the data transfer amount on the serial bus becomes large. On the other hand, in the second comparative example of FIGS. 3B and 4B, there is no redundant data. However, if it is attempted to support camera data of all formats, the data formatter and the counter become large. There is.

  On the other hand, in the method of this embodiment, redundant data exists, but the number of bits is sufficiently smaller than that of the first comparative example. Therefore, the amount of data transferred on the serial bus is not so large, and data transfer can be made efficient. Also, as shown in FIGS. 8 and 9, even when trying to support camera data of all formats, the circuit scale of the data formatter and the counter is not so large as compared with the second comparative example.

  Next, the advantages of the method of this embodiment over the first and second comparative examples will be described with reference to FIGS. 11A to 11C are examples in the case where the packet width (bus width) in which the packed data of FIG. 8 is set is 8 bits (I = 1), and FIGS. (C) is an example when the width of the packet in which the packed data of FIG. 9 is set is 16 bits (I = 2).

  11A to 12C, N is the number of bytes or words of packed data, and L is the number of bits of redundant data (dummy data). K is the number of bits of input data, and M is the number of (K + L) bit data in the packed data.

  In order to perform the format conversion, a counter (a byte counter, a bit counter, or the like) that counts each of N, M, and K in FIGS. 11A to 12C is necessary. Here, the condition for K is the same in the first and second comparative examples and the present embodiment. Therefore, the circuit scale depends on the counter that counts N and M, the circuit that multiplexes and decodes the count value from the counter, and the like. Therefore, it is necessary to reduce N × M as much as possible in order to reduce the circuit scale. Note that the number of N / M combinations corresponds to the number of circuits.

  On the other hand, in order to reduce the data transfer amount of the serial bus, it is necessary to reduce L which is the number of bits of redundant data.

  Therefore, in order to achieve both a reduction in the amount of data transfer and a reduction in circuit scale, it is desired that both N × M minimization and L minimization can be achieved.

  In this regard, in the first comparative example shown in FIGS. 11A and 12A, M = 1 is fixed. Therefore, N × M (circuit scale) can be reduced. For example, if the sum of N × M is calculated, it becomes 12 points in FIG. 11A and 8 points in FIG.

  However, in this first comparative example, the number of redundant data bits L (data transfer amount) becomes large. For example, when the total of L is calculated, it becomes 13 bits in FIG. 11A and 45 bits in FIG.

  In the second comparative example shown in FIGS. 11B and 12B, L = 1 is fixed. Therefore, L (data transfer amount) can be reduced. For example, when the total of L is calculated, both bits become 0 bits in FIGS. 11B and 12B.

  However, in the second comparative example, since N and M are large, N × M (circuit scale) becomes large. For example, if the sum of N × M is calculated, it becomes 100 points in FIG. 11B and 197 points in FIG. 12B, which becomes very large.

  On the other hand, in the method of the present embodiment shown in FIGS. 11C and 12C, L and M are set variably according to K. That is, L and M are changed to appropriate values according to K.

More specifically, in FIG. 11C where I = 1,
(1) When K = 6, L = 0, M = 4, N = 3
(2) When K = 7, L = 1, M = 2, N = 2
(3) When K = 8, L = 0, M = 2, N = 2
(4) When K = 10, L = 2, M = 2, N = 3
(5) When K = 12, L = 0, M = 2, N = 3
(6) When K = 16, L = 0, M = 1, N = 2, or (7) When K = 24, L = 0, M = 1, N = 3 ,
Packed data has been generated.

In FIG. 12C where I = 2,
(11) When K = 6 and I = 2, L = 0, M = 8, N = 3
(12) When K = 7 and I = 2, L = 1, M = 4, N = 2
(13) When K = 8 and I = 2, L = 0, M = 4, N = 2
(14) When K = 10 and I = 2, L = 1, M = 3, N = 2
(15) When K = 12, I = 2, L = 0, M = 4, N = 3
(16) L = 0, M = 2, N = 2 when K = 16, I = 2, or (17) L = 0, M = 2 when K = 24, I = 2 , So that N = 3.
Packed data has been generated.

  In this case, in the method of the present embodiment, the formula of N × 8 × I = (K + L) × M is established. For example, in FIG. 11C where I = 1, the formula of N × 8 = (K + L) × M is established. In FIG. 12C where I = 2, the equation N × 8 × 2 = (K + L) × M is established. However, there is an exception only when K = 10 in FIG. 12C (in the case of (14) described above).

  In addition, even if not satisfying all of the above-mentioned (1) to (7) and (11) to (17), it is packed so that only a part of (1) to (7) and (11) to (17) is satisfied Data may be generated. That is, only a part of the formats of YUV422, YUV420, RGB888, RGB565, RGB444, RAW6, RAW7, RAW8, RAW10, RAW12, and JPEG8 may be supported.

  According to the method of the present embodiment described above, as is apparent from FIGS. 11C and 12C, N × M (circuit scale) can be reduced as compared with the second comparative example. For example, calculating the total of N × M gives 37 points in FIG. 11C and 68 points in FIG. Therefore, the circuit scale can be sufficiently reduced as compared with the second comparative example in which the total of N × M is 100 and 197 points.

  In the method of the present embodiment, the number of bits of redundant data is smaller than that in the first comparative example, so that L (data transfer amount) can be reduced. For example, the total of L is 3 bits in FIG. 11C and 2 bits in FIG. 12C. Therefore, the data transfer amount can be sufficiently reduced as compared with the first comparative example in which the total of L is 13 or 45 bits.

  Thus, according to the method of the present embodiment, N × M minimization and L minimization can be achieved at the same time. Therefore, there is an effect that efficient serial transfer of data of various formats can be realized without enlarging the circuit scale so much.

5. Data Transfer Method Using Differential Signal Next, the serial transfer method of this embodiment will be described with reference to FIG. In FIG. 13, DTO + and DTO- are data (OUT data) output from the host side (data transfer control device 10) to the target side (data transfer control device 30). CLK + and CLK− are clocks supplied from the host side to the target side. The host side outputs DTO +/− in synchronization with the edge of CLK +/− (for example, a rising edge or a falling edge). Therefore, the target side can sample and capture DTO +/− using CLK +/−. Further, in FIG. 13, the target side operates based on the clock CLK +/− supplied from the host side. That is, CLK +/− becomes the system clock on the target side. Therefore, the PLL (Phase Locked Loop) circuit 12 (clock generation circuit in a broad sense) is provided on the host side, and is not provided on the target side.

  DTI + and DTI- are data (IN data) output from the target side to the host side. STB + and STB- are strobes (clocks in a broad sense) supplied from the target side to the host side. The target side generates and outputs STB +/− based on CLK +/− supplied from the host side. The target side outputs DTI +/− in synchronization with the STB +/− edge (for example, a rising edge or a falling edge). Therefore, the host side can sample and capture DTI +/− using STB +/−.

  In each of DTO +/−, CLK +/−, DTI +/−, and STB +/−, a transmitter circuit (driver circuit), for example, drives differential signal lines (Differential Signal Lines) corresponding to each of these, for example, current drive (or voltage drive) To be transmitted. In order to realize faster transfer, two or more pairs of DTO +/− and DTI +/− differential signal lines may be provided.

  The transceiver 20 on the host side includes transmitter circuits 22 and 24 for OUT transfer (data transfer in a broad sense) and clock transfer, IN transfer (data transfer in a broad sense), and strobe transfer (clock in a broad sense). (Receiver) receiver circuits 26 and 28 are included. The target-side transceiver 40 includes receiver circuits 42 and 44 for OUT transfer and clock transfer, and transmitter circuits 46 and 48 for IN transfer and strobe transfer. Note that a configuration in which some of these circuit blocks are not included may be employed.

  The transmitter circuits 22 and 24 for OUT transfer and clock transfer transmit DTO +/− and CLK +/− by driving the differential signal lines of DTO +/− and CLK +/−, respectively. The receiver circuits 42 and 44 for OUT transfer and clock transfer perform current / voltage conversion based on the current flowing through the differential signal lines of DTO +/− and CLK +/−, respectively, and are obtained by current / voltage conversion. By performing a comparison process (differential amplification process) of the differential voltage signals (first and second voltage signals), DTO +/− and CLK +/− are received.

  The IN transfer and clock transfer transmitter circuits 46 and 48 transmit DTI +/− and STB +/− by driving the differential signal lines of DTI +/− and STB +/−, respectively. The IN transfer and strobe transfer receiver circuits 26 and 28 perform current / voltage conversion based on currents flowing through the differential signal lines of DTI +/− and STB +/−, respectively, and are obtained by current / voltage conversion. By performing a comparison process (differential amplification process) of the differential voltage signals (first and second voltage signals), DTI +/− and STB +/− are received.

6). Electronic Device FIG. 14 shows a configuration example of the electronic device of the present embodiment. This electronic device includes the data transfer control devices 502, 512, 514, 520, and 530 described in the present embodiment. Further, it includes a baseband engine 500 (a communication device in a broad sense), an application engine 510 (a processor in a broad sense), a camera 540 (an imaging device in a broad sense), or an LCD 550 (a display device in a broad sense). Note that some of these may be omitted. According to this configuration, a mobile phone having a camera function and an LCD (Liquid Crystal Display) display function can be realized. However, the electronic device of the present embodiment is not limited to a mobile phone, and can be applied to various electronic devices such as a digital camera, a PDA, an electronic notebook, an electronic dictionary, or a portable information terminal.

  As shown in FIG. 14, the present embodiment is implemented between a host-side data transfer control device 502 provided in the baseband engine 500 and a target-side data transfer control device 512 provided in the application engine 510 (graphic engine). The serial transfer described in the embodiment is performed. The present embodiment also includes a host-side data transfer control device 514 provided in the application engine 510, a data transfer control device 520 including a camera interface circuit 522, and a data transfer control device 530 including an LCD interface circuit 532. The serial transfer described in (1) is performed. Note that the baseband engine 500 and the application engine 510 may be realized by the same hardware (CPU or the like).

  According to the configuration of FIG. 14, EMI noise can be reduced as compared with a conventional electronic device. Further, by realizing a reduction in the size and power consumption of the data transfer control device, it is possible to further reduce the power consumption of the electronic device. In the case where the electronic device is a mobile phone, the signal line passing through the connection portion (hinge portion) of the mobile phone can be a serial signal line, and the mounting can be facilitated.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are included in the scope of the present invention. For example, a term (camera / display driver, 8.16 bit, etc.) described together with a different term (device, I byte, etc.) in a broader sense or the same meaning at least once in the specification or the drawing It can also be replaced with the different terminology.

  Further, the configuration and operation of the data transfer control device and the electronic device are not limited to the configuration and operation described in this embodiment, and various modifications can be made. Further, the format conversion method is not limited to that described with reference to FIGS. For example, K is not limited to 6, 7, 8, 10, 12, 16, 24, and I is not limited to 1, 2. It is also possible to use the method of the present invention for format conversion other than camera data.

The data transfer control apparatus of this embodiment, and its system structural example. The data transfer control apparatus of this embodiment, and its system structural example. 3A and 3B are explanatory diagrams of the method of the comparative example. 4A and 4B are explanatory diagrams of the method of the comparative example. 1 is a configuration example of a data transfer control device according to the present embodiment. 1 is a configuration example of a data transfer control device according to the present embodiment. 7A to 7D show waveform examples of camera interface signals. Explanatory drawing of the format conversion method of this embodiment. Explanatory drawing of the format conversion method of this embodiment. 10A and 10B are explanatory diagrams of packets used in the present embodiment. FIGS. 11A, 11B, and 11C are views for explaining advantages of the present embodiment. 12A, 12B, and 12C are views for explaining advantages of the present embodiment. Explanatory drawing of the serial transfer of this embodiment. Configuration example of an electronic device.

Explanation of symbols

5 Host device, 6 Display driver, 7 Display panel, 8 Camera,
10 data transfer control device (host side), 20 transceiver,
30 data transfer control device (target side), 40 transceiver,
90, 100 link controller, 92, 110 interface circuit,
200 data formatter, 202 data buffer,
204 Dummy data deletion circuit, 210-bit counter, 212-byte counter,
230 packet buffer, 240 packet analysis circuit, 242 header extraction circuit,
250 internal registers, 252 PCS registers, 254 PW registers,
300 data formatter, 302 data buffer,
304 dummy data insertion circuit, 310 bit counter, 312 byte counter,
320 packet generation circuit, 322 header generation circuit, 330 packet buffer,
350 Internal register, 352 PCS register, 354 PW register

Claims (7)

A data transfer control device for controlling data transfer,
An interface circuit for performing interface processing with a host device connected via a system bus;
A link controller that analyzes a packet received via the serial bus and outputs data in which one data unit is K bits (K is an integer of 2 or more) to the interface circuit;
In the data field of the packet received via the serial bus,
M pieces (M is an integer of 1 or more) of (K + L) bits of data obtained by adding L bits (L is an integer of 0 or more) of dummy data to the K bits of data are collected ( N × I) bytes (N and I are integers of 1 or more), and packed data in which L and M are variably set according to K is inserted,
The link controller
A data transfer control device comprising: a data formatter that extracts the K-bit data from the packed data and outputs the data to the interface circuit. In claim 1,
The packed data inserted into the packet is
When K = 6 and I = 1, L = 0, M = 4 and N = 3, or when K = 7 and I = 1, L = 1, M = 2 and N = 2 Or, if K = 8 and I = 1, then L = 0, M = 2, N = 2, or if K = 10, I = 1, L = 2, M = 2, N = 3 or when K = 12, I = 1, L = 0, M = 2, N = 3, or when K = 16, I = 1, L = 0, M = 1, A data transfer control device, wherein N = 2, or if K = 24 and I = 1, the data is L = 0, M = 1, and N = 3. In claim 1 or 2,
The packed data inserted into the packet is
When K = 6 and I = 2, L = 0, M = 8, and N = 3, or when K = 7 and I = 2, L = 1, M = 4, and N = 2 Or, if K = 8 and I = 2, then L = 0, M = 4, N = 2, or if K = 10 and I = 2, L = 1, M = 3, N = 2 or when K = 12, I = 2, L = 0, M = 4, N = 3, or when K = 16, I = 2, L = 0, M = 2, A data transfer control device, wherein N = 2, or if K = 24 and I = 2, the data is L = 0, M = 2, and N = 3. In claim 1,
N × 8 × I = (K + L) × M In any one of Claims 1 thru | or 4,
Setting information for setting the M and N is inserted in the header of the packet received via the serial bus,
The link controller
A packet analysis circuit that analyzes a header of the received packet and extracts the setting information from the packet header;
The data formatter is:
A data transfer control device, wherein the data of K bits is extracted from the packed data based on the setting information. In any one of Claims 1 thru | or 5,
Setting information for setting the M and N is inserted in the header of the packet received via the serial bus,
The link controller
A packet analysis circuit that analyzes a header of the received packet and extracts the setting information from the packet header;
The data formatter is:
A data transfer control device, wherein the dummy data is deleted based on the setting information. A data transfer control device according to any one of claims 1 to 6;
An electronic apparatus comprising: the host device connected to the data transfer control device via the system bus.

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