JP2007178231A - Logic verification system substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for performing early prototyping verification of a plurality of logics at high speed with the same system substrate. <P>SOLUTION: By realizing high-speed wiring path switching by using an FET switch 903, and performing its on/off control with a programmable switch (FPGA or the like), the control of the FET switch 903 is determined by adjusting it to a target logic to be programmed in FPGAs 901, when logic partitioning and wiring processing among FPGAs are performed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a logic verification technique in the development and design process of a large-scale integrated circuit (LSI), and particularly to a structure for operating an early prototyping board equipped with a plurality of FPGAs (field programmable gate arrays) at high speed. And effective technology.

  As a technique examined by the present inventor, for example, the following techniques can be considered in the logic verification in the LSI development / design process.

  The logical scale of LSI is increasing year by year with high integration, and the complexity is increased in terms of function. Therefore, a solution that can shorten the development period while ensuring quality has become important. One solution to this problem is early prototyping technology using FPGA. Early prototyping technology is an early stage of LSI design, in which the logic to be verified is built into a programmable device such as an FPGA, and the FPGA or the like is incorporated into a real system as a pseudo LSI to perform logic emulation and software debugging This is a technology for confirming the operation of the entire system including the above.

  When this technology is applied, I / F (interface) operation confirmation with peripheral actual parts, confirmation of mounting board, extraction of defects that are difficult to detect by logic simulation, etc., which could not be detected without actually creating an actual LSI, etc. It is possible to reduce the design period and cost. In this technology, how to allocate large-scale logic that does not fit in one FPGA to multiple FPGAs and how to operate them at high speed is ensured for verification speed and connected to external I / F with limited operating speed range It is very important to do.

As technical documents related to the present invention, there are Patent Documents 1 and 2, for example.
JP 11-352190 A JP-A-8-194725

  By the way, as a result of the inventor's investigation on the early prototyping technology using the FPGA as described above, the following has been clarified.

  For example, the following three techniques can be considered as a method of dividing the logic to be verified into a plurality of FPGAs and connecting them.

  FIG. 1 shows a schematic configuration of a logic verification system board according to a first technique examined by the inventor as a premise of the present invention.

  The logic verification system board according to the first technique includes, for example, a plurality of FPGAs or FPGA modules (Logic), programmable switches (SW), connectors (Connectors), and the like. As shown in FIG. 1, the first technique is that a plurality of programmable switches (switch devices) are arranged on a system board, and the FPGA or FPGA module on the board and the programmable switch are fixedly wired. Connection between FPGA modules is performed via a programmable switch.

  In this technique, since all the wirings between the divided logics are connected via switches, wiring between FPGAs can be performed relatively easily even if the number of connections at each dividing boundary is biased.

  However, there is a drawback that the operation speed is reduced due to the switch-passing wiring delay.

  FIG. 2 shows a schematic configuration of a logic verification system board according to the second technique examined by the inventor as a premise of the present invention.

  The logic verification system board according to the second technique includes, for example, a plurality of FPGAs or FPGA modules (Logic), connectors (Connectors), and the like. As shown in Fig. 2, the second technology prepares a connector that can mount an FPGA module on the system board, or directly mounts an FPGA, and directly connects between each FPGA / FPGA module by board wiring or cabling. To do.

  This technology can transfer signals between the FPGAs at high speed.

  However, since the connection between FPGAs is fixed, depending on the number of connections at each division boundary, even if the number of pins is within the FPGA limit, wiring may not be possible. Inevitably passes, and the operation speed deteriorates due to the delay. The delay in this case tends to be larger than the switch device passage delay because the logic occupies approximately the inside of the FPGA, and extra FPGA pins are used. Furthermore, for bus connections (directly connected wiring to all FPGAs), it is advantageous if there are more than the same number of branch logical nets, but if not, less logical signal connections are used in the wiring path than physical connections. As a result, there is a problem that unconnected FPGA pins become unusable (see FIG. 6).

  FIG. 3 shows a schematic configuration of a logic verification system board according to the third technique examined by the inventor as a premise of the present invention.

  The logic verification system board according to the third technique includes, for example, a plurality of FPGAs or FPGA modules (Logic), programmable switches (SW), connectors (Connectors), and the like. In the third technique, as shown in FIG. 3, a module on which a plurality of FPGAs are mounted, an FPGA on which logic is mounted, and a switch device (FPGA, etc.) are directly mounted on the module, and fixed wiring is provided between them. This technique is characterized by having a wiring directly connecting FPGAs and a wiring including a switch device.

  With this technology, it is possible to prevent a decrease in operation speed by using a direct connection for a logical connection that requires a high speed operation while maintaining a degree of freedom of wiring. The problems of the first and second techniques can be solved to some extent.

  However, since there is no bus connection, it is difficult to realize a multi-pin bidirectional bus. Depending on the division boundary, a critical path (logical connection that requires high-speed operation) due to a shortage of paths may pass through the switch, although not as much as in the first and second technologies.

  The third technique is a configuration for eliminating the disadvantages while taking advantage of the respective merits of the first and second techniques, but has the following two problems.

  Problem 1: A bidirectional signal connected to a bus has a route only through a switch, and high-speed operation of a logic having an internal bus becomes difficult (see FIG. 4). That is, switch devices with I / O (input / output) buffers (FPGA, etc.) require enable control within the switch when passing bidirectional wiring. Is required.

  Problem 2: As shown in FIG. 5, there are two methods for expanding the scale of the FPGA module (stacking method and parallel placement method), but it becomes difficult to secure the wiring path between the modules according to the scale expansion. That is, in the case of the stacking method, the passing wiring in the intermediate portion increases as the number of stacks increases ((N−1) × 2). In the case of the parallel arrangement method, the number of connections between two modules decreases with the number of parallel connections (1 / N). In FIG. 5, S is a switch device (Switch-Device), C is a connector, and F is an FPGA.

  Problem 1 can be avoided by preparing bus wiring for direct connection between all FPGAs as described above, for example. However, when the divided target logic has many one-to-one connections, as shown in FIG. An unusable pin is generated, and the FPGA pin number cannot be fully used.

  Further, if a crossbar switch device without an I / O buffer as shown in FIG. 7 is used, bidirectional wiring can be passed without control, but the load on the wiring driven by the FPGA is substantially increased. In many cases, the passing delay is larger than that of a switch device with a normal I / O buffer.

  As for the problem 2, there is a technique for expanding the scale by increasing the number of FPGAs by embedding a system-specific bus I / F logic at the time of division by using bus connection as shown in FIG. Although this technique is effective when the division boundary is a logical bus or when the number of connections at the division boundary is very large, generally, signals passing through the bus are all I / F signals between the FPGAs. For this reason, there is a problem that the overall operation speed is reduced as compared with the one-to-one connection. In FIG. 8, Logic is an FPGA or FPGA module, and Connector is a connector.

  Accordingly, an object of the present invention is to provide a technique capable of solving the problems 1 and 2 in a logic verification system board.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In other words, the logic verification system board according to the present invention uses FET (Field Effect Transistor) switches to realize high-speed wiring path switching and perform on / off control with programmable elements (FPGA or the like). The control of the FET switch is determined in accordance with the target logic at the time of logical division and wiring between FPGAs.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) The architecture of the FPGA module can be selected according to the logical signal connection at the division boundary by switching the wiring path of the logical signal at the division boundary at the time of wiring in accordance with the logic cut point divided into a plurality of FPGAs. As a result, early prototyping verification of multiple logics can be performed at high speed with the same module.

  (2) By allowing external I / F and internal wiring resources to be selected when wiring in the FPGA module according to the logic of the division into multiple FPGAs, signals can be directly input to the top module when stacking Can be switched to a different configuration. In addition, the wiring route can be selected according to the installed system.

  (3) Since the route setting information is included as a wiring result, the data and the hardware setting do not become inconsistent.

  (4) It is possible to facilitate the application of a design flow that drops hardware from verified ones to hardware.

  (5) By increasing the verification speed, a large number of tests can be performed in a short period of time.

  (6) Software debugging and system verification including the actual board can be performed before manufacturing the actual chip.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 9 is a diagram showing a schematic configuration of the logic verification system board according to the first embodiment of the present invention.

  First, an example of the configuration of the logic verification system board according to the first embodiment will be described with reference to FIG. The logic verification system board according to the first embodiment includes, for example, a plurality of FPGAs 901, programmable switches (FPGAs, etc.) 902, FET switches 903, and the like. The plurality of FPGAs 901 are connected by direct connection wiring.

  In the first embodiment, as shown in FIG. 9, an FET switch 903 is inserted between directly connected FPGA wires, and the control signal is connected to a programmable switch 902 (a programmable device such as an FPGA).

  Generally, a programmable switch can determine the connection between pins relatively freely, but on the other hand, it has a complicated internal structure (consisting of a large number of wiring resources and switches), resulting in a large passing wiring delay. (About 10ns). On the other hand, since the FET switch 903 realizes simple ON / OFF (OFF), the passing delay becomes high speed (about 100 ps).

  In the case of the connection configuration as shown in FIG. 9, the multi-branch bidirectional wiring can secure a directly connected wiring resource by turning on the FET switch 903. Further, it is possible to cope with a logical division result with many one-to-one connections by turning off the FET switch 903. Furthermore, by installing logic in the programmable switch 902, the path can be switched during the logic operation.

(Embodiment 2)
FIG. 10 is a diagram showing a schematic configuration of a logic verification system board according to the second embodiment of the present invention.

  An example of the configuration of the logic verification system board according to the second embodiment will be described with reference to FIG. The logic verification system board according to the second embodiment includes, for example, a plurality of FPGAs 901, a plurality of programmable switches 902, a FET switch 904, and the like.

  In the second embodiment, an FET switch 904 having a configuration as shown in FIG. 11 is inserted between the FPGA 901 and the programmable switch 902.

  With such a configuration, the divided logical I / F has many one-to-one connections, and high-speed operation can be realized even when there is a bias.

  For comparison, FIG. 12 shows (a) a conventional configuration and (b) a configuration of the second embodiment. (A) Since the conventional configuration uses a switch to perform wiring, the number of connections is large and a shortage of wiring resources occurs. However, in (b) the second embodiment, a shortage of wiring resources does not occur.

(Embodiment 3)
The first and second embodiments are intended to realize wiring switching inside the module, but can also be applied to an interface with the outside of the module.

  FIG. 13 is an explanatory diagram showing an internal utilization method of the connector wiring used at the time of expansion.

  For example, by connecting the FET switch 903 to the wiring between the expansion connector 905 and the FPGA 901, it is possible to increase the number of connections between FPGAs inside the module when the connector is not used. That is, when the connector 905 is not used, the FET switch 903 can be used as an internal wiring.

  FIG. 14 is an explanatory diagram showing a bus line external connection method.

  As shown in FIG. 14, by adding the FET switch 903 to the direct connection wiring between the connector 905 and the FPGA 901 and between the FPGA 901, a bus line that can be connected from the outside can be realized inside the module. As a result of this switching, a normal wiring route can be secured when a single module is used or when an external access as shown in FIG. 8 is performed but a plurality of FPGAs in the module realize one function (one group). In the case where one function is realized by each FPGA in the module, the system bus shown in FIG. 8 can be connected to each FPGA.

  Furthermore, by connecting the lines to the upper and lower (or left and right) connectors, even when the modules are connected in a stack type, it is possible to connect the bus to the in-module FPGA far from the I / O side. That is, the hardware architecture can be selected according to the hardware configuration such as the stack and the verification method by connecting the bus connection lines to the connectors on both sides of the logic verification system board.

  As shown in FIG. 15, by mounting the FET switch 903 not on the FPGA module 906 but on the board on which the FPGA is mounted, the first, second, and third embodiments have the substrate wiring on which a plurality of FPGA modules 906 can be mounted. But it can be applied.

  Further, by adopting such a configuration, it becomes easy to construct a logic verification environment in which an arbitrary CPU 907 or IP 908 is connected to the bus 909 as shown in FIG. That is, as shown in FIG. 16, the fixed bus I / F logic may be mounted on one version of the FPGA module 910. In addition, in the simulation accelerator connection, it is possible to easily apply a design flow in which the fixed bus is a cut surface and the verified bus is dropped to hardware.

  Therefore, in the logic verification system boards of the first to third embodiments, an FET switch that can be turned on / off at high speed is mounted on the FPGA module, and two or more types of wiring path configurations can be selected. It is divided by having a configuration in which the programmable / off means is controlled by a programmable device, turning on / off of the switch at the time of wiring processing after logical division, and outputting the setting as part of logical data. The wiring path can be switched according to the logic state.

  Further, according to the third embodiment, by adding an FET switch between the connector-FPGA wiring and the FPGA-FPGA wiring, it is possible to configure a wiring path that is connected to all the FPGAs in the module and penetrates the connector. Since signals can be transmitted via the path no matter how many stages are stacked, the same module can be used in different connection configurations according to the verification target and the hardware configuration.

  For example, when one module is used and the entire verification target is used, it is turned off. When one module is used, it is turned on when it is a part of the verification target. Is turned off (bottom) and turned on (upper), and is turned on when a plurality of modules are used and are part of the verification target.

  Next, examples of the first to third embodiments will be described in detail.

  First, a design and verification process in an LSI will be described with reference to FIG. FIG. 17 is a flowchart showing an LSI design / verification process.

  First, specification design for determining the specification of a circuit to be realized is performed (step S1701).

  Next, based on the determined specification, the logic circuit is described at the register transfer level using HDL (hardware description language), and logic design is performed (step S1702).

  Thereafter, the designed logic circuit is verified using a system called a logic simulator having a function of verifying the operation of the logic circuit on a general-purpose processor in a pseudo manner (step S1703). This verification is generally called logic simulation. Here, it is verified whether the logical function is as specified.

  When the logic function is confirmed, logic synthesis processing is performed, and processing for converting a circuit described at the register transfer level into a target ASIC gate circuit is performed (step S1704).

  After the logic synthesis, a circuit composed of the actual ASIC gates is obtained as an output, and therefore, it is generally performed at this point to verify whether the timing satisfies the specification (step S1705). .

  Further, as shown in step S1706, logic using a reconfigurable device such as an FPGA (Field programmable Gate Array) in parallel with verification by logic simulation, logic synthesis, and layout from the end of verification by logic simulation. It is common to perform emulation. This verification is performed by programming the logic designed in the reconfigurable device to operate the logic at a speed close to the actual operation in combination with the actual peripheral components, and the misunderstanding of the specifications of the actual components and the test pattern are long. The purpose is to extract defects and the like in cases that cannot be executed by logic simulation before LSI manufacturing.

  In addition, programming logic designed in a reconfigurable device makes it possible to operate the logic at a speed close to actual operation, so software that operates in combination with the designed logic can be used, such as in the development of embedded systems. When designing at the same time, as in step S1707, software debugging can be performed before LSI sample manufacture. As a result, the design period can be shortened.

  If there is no problem in the timing after logic synthesis, the logic converted to the target ASIC gate circuit by logic synthesis is input, the cell is arranged on the chip, and the cell pins are wired according to the logic connection between the cells. A layout process is performed (step S1708).

  Thereafter, final verification is performed to determine whether the timing in the layout result satisfies the specification (step S1709).

  When this verification and prototyping verification are finished, an LSI is actually manufactured (step S1710).

  After this, actual machine verification is performed for final confirmation (step S1711). However, when prototyping verification is performed, common test data and environment can be used, and can be extracted only at this time. Since the defect which did not exist is detected at an early stage, the actual machine verification period can be greatly shortened. In general, LSI development is performed in such a flow.

  The present invention mainly relates to a logic simulation acceleration method using FPGA which is a reconfigurable device in logic emulation (step S1706), software debugging (step S1707), and logic verification.

  Next, a method for programming logic to be verified in the FPGA module in prototyping using an FPGA module equipped with a plurality of FPGAs will be described with reference to FIG. FIG. 18 is a flowchart showing processing steps for programming logic in the FPGA module.

  First, the verification target logic realized in the FPGA module is cut out from the LSI under design (step S1801). Eventually, the verification target logic is the entire LSI under design, but by implementing the designed function in the FPGA module, logic simulation can be accelerated and logic emulation can be executed. In this description, a reconfigurable device is referred to as FPGA.

  Next, the logic to be verified is assigned to a plurality of FPGAs on the FPGA module (step S1802). This step is usually called logical partitioning. An example of this processing is shown in FIG. Although logical division is generally performed in units of functional blocks (see, for example, JP-A-8-194725), assignment to a plurality of FPGAs may be performed across functional blocks. In FIG. 19, for the functional blocks A, B, C, D, and E of the verification target logic, the functional block A is the FPGA 901a, the functional block B is the FPGA 901b, the functional block C is the FPGA 901c, and the functional blocks D and E are the FPGA 901d. Have assigned.

  Next, the ports of the logic to be verified are assigned to the pins of the connector 905 of the FPGA module 906, and the logical connections between the logics assigned to the plurality of FPGAs 901 on the FPGA module 906 and between the logics and the ports are actually set. A process of assigning to the wire of the FPGA module 906 is performed (step S1803).

  FIG. 20 shows an example of the architecture of the FPGA module 906, and FIG. 21 shows an example of this processing.

  The mounted components such as the connector 905 and the FPGA 901 are connected by substrate wiring (wires). Usually, each part is composed of a plurality of wires. The connector 905 is connected to the outside of the FPGA module 906 in units of pins. A logical connection (net) between the divided logics is assigned to a wire of the FPGA module 906 to determine a wiring path. Usually, in the FPGA module 906, a plurality of wires are connected between components, but in this processing, up to which wire is determined. A logical port is assigned to a pin of the connector 905. Usually, it is often determined in accordance with the wiring assignment on the mounting board side. Note that the process of assigning the port of the verification target logic to the pin of the connector 905 of the FPGA module 906 is generally performed according to the wiring on the board side on which the FPGA module 906 is mounted. At this time, the connection in the switching device mounted on the FPGA module 906 is also determined.

  Thereafter, each divided logic is converted (logic synthesis) into a circuit described by the gate of the target reconfigurable device (step S1804).

  Further, for each division result logic assigned to each FPGA 901, the wire assignment result of the inter-connection determined in the inter-FPGA wiring process is input as the pin arrangement constraint of the FPGA 901, and the arrangement / wiring process in the FPGA 901 is performed (step S1805). .

  When this process ends, a process of programming (configuring) the connection in the switching device determined in the inter-FPGA wiring process and the placement and wiring process in the FPGA into the FPGA 901 is performed (step S1806). By performing this process, the programmed logic can be operated by the FPGA module 906. Various methods for programming (configuring) logic in the FPGA and switching device are provided and presented by FPGA manufacturers and switching device manufacturers. In general, configuration data is stored in memory. A method of programming configuration data in an FPGA or a switching device directly or via an LSI that controls the configuration is used.

  Next, FIG. 22 shows an example of a process for performing on / off determination of the FET switch in the inter-FPGA wiring process in step S1803 in accordance with the logical division result in step S1802.

  FIG. 23 shows the division processing result. According to the flow example of FIG. 22, it is assumed that the result of step S1802 is a connection as shown in FIG. 23, and an FPGA module (number of connections) having an architecture as shown in FIG. 24 and an FET switch mounted as shown in FIG. Is assumed to be a target). When the placement and routing process (the process of step S1803) is performed, since a branch wiring exists, it is determined whether the branch wiring is bidirectional or timing critical. If all of the branch nets are timing critical, the FET switch is turned on and wiring processing is performed until no FET switch is turned off.

  In the case of FIG. 24, when the FET switch is turned on, the number of wires connected to all the FPGAs 901 is 60, so 30/60 is turned on and the rest is turned off. In such a case, it is necessary to determine which FET switch is turned on and which FET switch is turned off. For example, the number of connections between the FPGAs is evaluated, and the FPGA on the target FPGA module is evaluated. Processing such as selecting from the ones having a large difference between the number of inter-wires and the number of connections in the division result can be considered. In the case of FIG. 23, if the number of wires between FPGAs is uniform, there is no logical connection between the division results (1)-(4) and the division results (2)-(3). Set it on.

  Next, the division result (1)-(2) and the division result (3)-(4) are selected, and the connection of the FPGA module at this point is as shown in FIG.

  Next, it is determined whether or not the direct connection wiring between FPGAs is insufficient. However, the division result (1) to (3) corresponds to 60 resources for 70 resources and 70 connections. The 10 overflows can be absorbed by turning on the FET switch between the division results (1)-(2) and the division results (3)-(4). The division result (1) even if this switch is turned on. -Between (2) and division results (3)-(4), there are 20 and 10 margins for 40 wire resources, so division results (1)-(2), division results (3)- The remaining 10 FET switches during (4) are set to ON, and final FET switch settings and wiring assignments are as shown in FIG.

  Unlike the present invention, when the FET switch is not mounted, the result of the inter-FPGA wiring processing in step S1803 in FIG. 18 is that all nets that have passed through the FET switch go through the programmable switch with a large delay, and the entire FPGA module. This causes the operating frequency to decrease. Further, the occurrence of problem 1 in FIG. 4 cannot be suppressed.

  Furthermore, by connecting the FET switch control signal to the programmable device, the result of determining the control of the FET switch in accordance with the target logic at the time of logic division and inter-FPGA wiring processing can be included in the configuration data. Malfunctions due to setting errors can be suppressed without mismatching hardware settings, and multiple logics with different wiring path settings can be programmed without changing hardware settings such as switch switching while the same FPGA module is installed. It is also possible to do. Furthermore, since the control signal of this switch is connected to the programmable device, switching during operation of the wiring path is also possible. An example of this will be described later.

  Although the above embodiment is described on the assumption that the FET switch of FIG. 9 is inserted, the ON / OFF setting can be determined in the same way for FIGS. 10, 13 and 14 as well. FIGS. 10 and 13 are effective when the number of one-to-one connections is locally large, and FIG. 14 is effective for interface (port) branching and bidirectional connection. Further, FIG. 14 can be effective even when the FPGA modules are stacked (stacked).

  FIG. 28 shows an example of bus connection, and FIG. 29 shows an example of individual connection.

  When the number of connections between the FPGAs can be secured to some extent, the signal transmission / reception between the plurality of FPGAs is performed by the individual connection as shown in FIG. 29 rather than the connection of the plurality of FPGAs by the common bus connection as shown in FIG. Even if time-sequential multiplexing (FIG. 30) is performed due to insufficient resources, the operation speed does not decrease. FIG. 30 shows a system in which a parallel-serial conversion and a serial-parallel conversion circuit are added and a plurality of logic signals are transferred with one wire.

  When FPGA modules are connected in a stack configuration, as the number of stacks increases as shown in FIG. 5, the number of nets that pass through the connector connection in the intermediate portion increases, so the wiring resources that can be used between the modules are greatly reduced. For this reason, depending on the result of logical partitioning, there is a possibility that FIG. 28 operates faster than FIG.

  In addition, FIG. 28 has an advantage that the signal transmission / reception circuit can be configured and connected relatively easily because FIG. 28 does not pass unrelated modules. If the configuration of FIG. 14 of the present invention is taken, it is possible to select either the configuration of FIG. 28 or FIG. 29 without changing the hardware in accordance with the division result and the module configuration during the processing of step S1803 of FIG. It becomes possible. This concept is the same for the scale expansion by the parallel arrangement method of FIG. Further, by configuring the FPGA module as shown in FIG. 14, it becomes easy to verify logic such that an arbitrary CPU or IP is connected to the bus.

  FIG. 31 shows a configuration example of a simulation accelerator using FPGA. A simulation accelerator using an FPGA includes a personal computer (PC) 3101 (or workstation) having a storage device such as a disk 3104 with input / output data and software for transmitting / receiving the data to / from the FPGA module 906 as in this configuration example. , A general-purpose interface (such as PCI) connectable to the PC 3101 and a motherboard 3103 on which a device that implements a bridge circuit 3102 for transferring data between the FPGA module 906 and an FPGA module 906 mounted on the motherboard are included. .

  Next, FIG. 32 shows a conceptual diagram of a logic verification method in which an arbitrary CPU 907 or IP 908 is connected to the bus. In FIG. 32, reference numeral 3201 denotes a designed (verified) IP.

  For undesigned ones, a function model on a PC is used to program the designed ones into hardware (FPGA). Even if it has been designed, if it is a verification target, placing it on the PC is advantageous in terms of debuggerability, so it may be placed on the PC. In that case, the entire simulation speed is improved by programming the FPGA from the designed and verified one.

  When such a verification method is implemented, when the configuration shown in FIG. 29 is adopted, program data creation processing is performed again for the entire target logic every time a new FPGA-target logic is added as shown in FIG. Is required. Since this redo becomes difficult in proportion to the logical scale of the target, it takes a long time to recreate the data. On the other hand, in the case of the configuration of FIG. 28, it is necessary to create and insert a bridge circuit between the target logic and the interface bus of the hardware (FPGA module), but only the verification target to be added is processed as shown in FIG. Therefore, program data can be prepared earlier than in FIG. In FIG. 34, when the bus bridge circuit is inserted, a circuit for connecting the logical bus to a bus prepared for hardware connection is inserted. Create according to the bus configuration.

  Therefore, if the FPGA module is configured as shown in FIG. 14, the architecture based on the one-to-one connection such as the case where the bus connection is more advantageous as in the present example or the stack configuration example and the case where the number of wirings is relatively small. Both the advantageous case and the advantageous case can be realized by the same FPGA module, and it is not necessary to prepare the FPGA module individually according to the target logic and the verification method.

  As an application example of the present invention, in FIG. 35, by utilizing the feature that the on / off of the FET switch is controlled by a programmable device, and dynamically switching the logic when the logic to be programmed in the FPGA module is operating, FIG. 36 is a time chart showing an implementation example in which the wiring inside the FPGA module can be used as a probe while using the wiring inside the FPGA module. In this case, the FET switch insertion location is based on FIG. The probe means a process of drawing a logic internal signal to its interface (connector) in order to connect to a waveform observation means such as a logic analyzer. By supplying the control signal of the FET switch from the programmable device, the same wiring path can be used while switching in accordance with the logical operation in individual applications while maintaining high speed.

  In this application example, the signal of the internal waveform can be observed without reducing the internal wiring resources.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be used for large-scale LSIs, IP components mounted on large-scale LSIs, and the like.

It is a figure which shows schematic structure of the logic verification system board | substrate by the 1st technique which this inventor examined as a premise of this invention. It is a figure which shows schematic structure of the logic verification system board | substrate by the 2nd technique which this inventor examined as a premise of this invention. It is a figure which shows schematic structure of the logic verification system board | substrate by the 3rd technique which this inventor examined as a premise of this invention. It is explanatory drawing of the problem 1 which this inventor examined as a premise of this invention. It is explanatory drawing of the problem 2 which this inventor examined as a premise of this invention. It is explanatory drawing of the problem 1 which this inventor examined as a premise of this invention. FIG. 10 is a diagram illustrating a crossbar switch device without an I / O buffer in Problem 1; In Problem 2, it is explanatory drawing which shows the technique which aims at the scale expansion by increasing the number of FPGAs using a bus connection. It is a figure which shows schematic structure of the logic verification system board | substrate by Embodiment 1 of this invention. It is a figure which shows schematic structure of the logic verification system board | substrate by Embodiment 2 of this invention. It is explanatory drawing which shows the structure of FET switch of FIG. (A) It is the figure which compared the structure of the conventional type and the structure of (b) Embodiment 2. FIG. In Embodiment 3 of this invention, it is explanatory drawing which shows the internal utilization method of the wiring for connectors used at the time of expansion. In Embodiment 3 of this invention, it is explanatory drawing which shows the external connection method of a bus line. In Embodiment 3 of this invention, it is a figure which shows the example applied to the board | substrate wiring which can mount two or more FPGA modules. In Embodiment 3 of this invention, it is a figure which shows the construction example of the verification environment of logic in which arbitrary CPU and IP are connected to a bus | bath. 5 is a flowchart showing an LSI design / verification process in the embodiment of the present invention. 4 is a flowchart illustrating processing steps for programming logic in an FPGA module in an embodiment of the present invention. It is a figure which shows the process example of the logic division | segmentation of the flow of FIG. In the Example of this invention, it is a figure which shows the architecture example of an FPGA module. It is a figure which shows the process example of the wiring between FPGAs of the flow of FIG. FIG. 19 is a flowchart illustrating an example of a process for performing on / off determination of an FET switch in the inter-FPGA wiring process of the flow of FIG. 18. It is a figure which shows the division | segmentation process result of the flow of FIG. It is a figure which shows the process example of the wiring between FPGAs of the flow of FIG. It is a figure which shows the process example of the wiring between FPGAs of the flow of FIG. It is a figure which shows the process example of the wiring between FPGAs of the flow of FIG. It is a figure which shows the process example of the wiring between FPGAs of the flow of FIG. In the Example of this invention, it is a figure which shows the bus connection example of the wiring between FPGAs. In the Example of this invention, it is a figure which shows the example of an individual connection of wiring between FPGAs. In the Example of this invention, it is a figure which shows the system which transfers several logic signals with one wire. In the Example of this invention, it is a figure which shows the structural example of the simulation accelerator using FPGA. In the Example of this invention, it is a conceptual diagram about the verification method of the logic by which arbitrary CPU, IP, etc. are connected to a bus | bath. 4 is a flowchart illustrating processing steps for programming logic in an FPGA module in an embodiment of the present invention. 4 is a flowchart illustrating processing steps for programming logic in an FPGA module in an embodiment of the present invention. It is a figure which shows the example of application of this invention. 36 is a time chart showing the operation of the application example of FIG. 35.

Explanation of symbols

901 FPGA
902 Programmable switch 903, 904 FET switch 905 Connector 906, 910 FPGA module 907 CPU
908 IP
909 Bus 3101 Personal computer (PC)
3102 Bridge circuit 3103 Motherboard 3104 Disk

Claims (5)

A plurality of FPGAs in which logic data to be verified is programmed;
First and second connection lines directly connecting the plurality of FPGAs;
FET for connecting the first connection line and the second connection line;
A logic verification system board comprising: a programmable element for performing on / off control of the FET. The logic verification system board according to claim 1,
A logic verification system board, wherein the programmable element is an FPGA. The logic verification system board according to claim 1,
A logic verification system board, wherein on / off control of the FET dynamically changes in accordance with logic data to be verified. The logic verification system board according to claim 1,
The logic verification system board, wherein the first and second connection lines are buses. The logic verification system board according to claim 4,
The logic verification system board according to claim 1, wherein the bus connection line penetrates and is connected to connectors on both sides of the logic verification system board.

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