JP2007173388A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of wiring layers of an interposer for drawing out a wiring connected to a plurality of pads formed in a semiconductor chip. <P>SOLUTION: The semiconductor integrated circuit device comprises a substrate 11 of a semiconductor of which a plurality of elements 12 are formed on a main surface, and a plurality of pads 15 arranged on the lattice points of a quadrilateral grid or triangular lattice, on the upper side of the plurality of elements 12 of the substrate 11 to be electrically connected to the plurality of elements 12. At least one of a plurality of virtual lines 16A connecting the lattice points together is non-parallel to the outside side of a semiconductor chip 10. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device having a pad electrode disposed on an upper surface of a semiconductor chip.

  In recent years, with the progress of the digital society, there has been an increasing demand for miniaturization, high functionality, and high speed operation of semiconductor integrated circuit devices, and semiconductor integrated circuit devices are being further integrated on a larger scale. For this reason, conventionally, pad electrodes (hereinafter referred to as pads) arranged at the peripheral edge of the semiconductor chip are arranged in an array on the entire surface of the semiconductor chip, so that the increase in the number of terminals can be accommodated. A configuration that satisfies the mountability of has been developed.

  A conventional semiconductor integrated circuit device will be described below with reference to the drawings.

  FIG. 16 shows a cross-sectional configuration of a conventional semiconductor integrated circuit device. As shown in FIG. 16, a conventional semiconductor integrated circuit device (semiconductor chip) 100 includes a substrate 101, a plurality of elements 102 formed on the substrate 101, and a main part of the substrate 101 including the plurality of elements 102. A plurality of insulating layers 103 covering the surface, a wiring 104 formed in each insulating layer 103, a plurality of pads 105 formed on the insulating layer 103 and electrically connected to the element 102 through the wiring 104, have.

  FIG. 17 shows an example of a mounting form of a conventional semiconductor integrated circuit device. As shown in FIG. 17, in the semiconductor chip 100, each bump 110 formed on each pad electrode 105 and each pad connection terminal 112 formed on the upper surface of the interposer (laminated wiring substrate) 111 are opposed to each other. By doing so, it is electrically connected to the interposer 111.

  FIG. 18 shows a planar configuration of a conventional semiconductor chip 100. As shown in FIG. 18, the plurality of pads 105 are arranged on the upper surface of the semiconductor chip 100 at an equal pitch in a direction parallel to each side of the semiconductor chip 100. 19 to 22 show connection examples of the wiring layers 111a to 111d of the interposer 111 when the semiconductor chip 100 shown in FIG. 18 is used.

As described above, in the conventional semiconductor integrated circuit device described above, the wiring of the four-layer interposer 111 shown in FIGS. 19 to 22 is used to draw out the 81 pads 105a to 105d shown in FIG. The number of layers is required.
Japanese Patent Laid-Open No. 07-022460 JP 2003-077948 A

  As described above, the conventional semiconductor integrated circuit device (semiconductor chip) has a problem that the number of wiring layers of the interposer increases as the number of pads formed on the semiconductor chip increases. As the number of wiring layers increases, the manufacturing process of the interposer becomes complicated, the throughput decreases, and the cost increases.

  An object of the present invention is to solve the above-described conventional problems and reduce the number of wiring layers of an interposer that leads to wirings connected to a plurality of pads formed on a semiconductor chip.

  In order to achieve the above object, according to the present invention, when a semiconductor integrated circuit device is arranged with a plurality of pads at all lattice points of a lattice shape, the lattice placement angle is set to the outer side of the semiconductor chip. Either non-parallel or a plurality of pads are selectively arranged at some grid points of the grid pattern.

  Specifically, a first semiconductor integrated circuit device according to the present invention includes a semiconductor substrate having a plurality of elements formed on the main surface, and a plurality of elements formed on the semiconductor substrate and electrically connected to the plurality of elements. Each of the plurality of first pad electrodes is disposed on each of the lattice points of the square lattice shape or the triangular lattice shape, and at least one of the plurality of lines connecting the lattice points is: It is characterized by being non-parallel to the outline (edge) of the semiconductor substrate.

  According to the first semiconductor integrated circuit device, the plurality of first pad electrodes are respectively arranged on the lattice points of the square lattice shape or the triangular lattice shape, and at least one of the plurality of lines connecting the lattice points. Is not parallel to the outer side (edge) of the substrate, and therefore, even if the distance between the first pad electrodes is the minimum pitch, the first The distance between the pad electrodes is larger than the minimum pitch. Therefore, the minimum pitch between the pad electrodes located at the peripheral edge when connecting the necessary wiring inside the interposer (laminated wiring board) on which the semiconductor integrated circuit device (semiconductor chip) is mounted (primary mounting). Thus, at least one wiring can be arranged from a region having a larger interval. As a result, the lead-out wiring from the pad electrode located on the inner side can be led out to the outside through between the pad electrodes having a large gap between the peripheral portions. It is possible to form an interposer in the same layer as the lead wiring. As a result, the number of wiring layers of the interposer necessary for wiring can be reduced.

  In the first semiconductor integrated circuit device, it is preferable that the non-parallel lines intersect with the edge of the semiconductor substrate at an angle of 45 °. Alternatively, in the first semiconductor integrated circuit device, the non-parallel lines preferably intersect with the edge of the semiconductor substrate at an angle of less than 45 °. By doing so, the arrangement direction of the first pad electrode and the cleavage direction of the substrate can be shifted, so that the mechanical strength can be increased against the external stress applied to the semiconductor chip.

  In the first semiconductor integrated circuit device, the distance between the adjacent first pad electrodes arranged on the outermost periphery at the edge of the semiconductor substrate is preferably larger than the distance between the closest lattice points at each lattice point. In this way, it is possible to form more lead wires from the pad electrodes in the same layer of interposer.

  A second semiconductor integrated circuit device according to the present invention includes a semiconductor substrate having a plurality of elements formed on the main surface, and a plurality of first elements formed on the semiconductor substrate and electrically connected to the plurality of elements. And a plurality of first pad electrodes are arranged on at least a part of each lattice point of a square lattice shape or a triangular lattice shape.

  According to the second semiconductor integrated circuit device, the plurality of first pad electrodes are arranged at least at a part on each lattice point of the square lattice shape or the triangular lattice shape, so A region in which the interval is larger than the minimum pitch is formed. As a result, at least one wiring can be arranged from a region having a larger interval than the minimum pitch, so that the lead-out wiring from the pad electrode located on the inner side passes through between the pad electrodes having a larger peripheral portion interval to the outside. It can be pulled out. Accordingly, since the lead-out wiring from the pad electrode located on the inner side can be formed in the same layer as the lead-out wiring of the outer pad electrode, the number of wiring layers of the interposer necessary for wiring can be reduced. Can do.

  In the second semiconductor integrated circuit device, the plurality of first pad electrodes are preferably arranged so that the arrangement density is sparser in the peripheral portion than in the central portion of the semiconductor substrate. In this way, since many lead-out wirings can be arranged in a sparse region, it is possible to efficiently lead out the wiring from the first pad electrode arranged in the central portion of the substrate.

  In the second semiconductor integrated circuit device, it is preferable that at least one of the plurality of lines connecting the lattice points is not parallel to the outline (edge) of the semiconductor substrate.

  In the second semiconductor integrated circuit device, it is preferable that the distance between the adjacent first pad electrodes arranged on the outermost periphery at the edge of the semiconductor substrate is larger than the distance between the closest lattice points at each lattice point. In this way, it is possible to form more lead wires from the pad electrodes in the same layer of interposer.

  The first or second semiconductor integrated circuit device includes a plurality of second pad electrodes formed in a region outside the plurality of first pad electrodes on the semiconductor substrate and electrically connected to the plurality of elements. The distance between adjacent second pad electrodes is preferably smaller than the minimum value of the distance between the first pad electrodes. As described above, since the second pad electrode is formed in a region outside the first pad electrode, the wiring can be drawn out from the second pad electrode on the surface of the interposer. Accordingly, since it is not necessary to provide vias that penetrate the interposer, the number of pads can be increased without increasing the number of wiring layers of the interposer. In addition, since the pitch of the second pad electrode is smaller than that of the first pad electrode, more second pad electrodes can be disposed on the upper side of the main surface of the substrate.

  In this case, it is preferable that the plurality of second pad electrodes are arranged in one row, that is, inline along the peripheral edge of the semiconductor substrate.

  In this case, it is preferable that the plurality of second pad electrodes are arranged in two rows in a staggered manner along the peripheral edge of the semiconductor substrate.

  According to the semiconductor integrated circuit device of the present invention, it is possible to reduce the total number of wiring layers of an interposer that draws wirings connected to a plurality of pads formed on a semiconductor chip to the outside. As a result, the manufacture of the interposer can be simplified, the reliability of the semiconductor integrated circuit device can be improved, and the manufacturing cost can be reduced.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a cross-sectional configuration of a main part of a semiconductor integrated circuit device according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor integrated circuit device (semiconductor chip 10) according to the first embodiment includes a substrate 11 made of a semiconductor such as silicon (Si), a transistor formed on the substrate 11, and the like. , A plurality of insulating layers 13 made of, for example, silicon oxide (SiO ₂ ) covering the main surface of the substrate 11, and copper (Cu And a plurality of wirings 14 made of a conductive material such as an aluminum (Al) alloy formed on the insulating layer 13 and electrically connected to the element 12 through the wirings 14. And a pad electrode 15. Here, each pad 15 is made of a conductive material such as Al alloy or Cu, and each pad electrode 15 is subjected to a surface treatment such as gold (Au) plating with nickel (Ni) as an underlayer. It may be. Further, a protective film made of silicon nitride (SiN), polyimide, or the like and opening each pad electrode 15 may be formed on the insulating layer 13.

  FIG. 2 shows an example of a mounting form of the semiconductor integrated circuit device according to the first embodiment. As shown in FIG. 2, the semiconductor chip 10 opposes each bump 20 formed on each pad electrode 15 and each pad connection terminal 22 formed on the upper surface of the interposer (laminated wiring substrate) 21. By doing so, it is electrically connected to the interposer 21 and is primarily mounted on the interposer 21 by a so-called face-down method.

  The interposer 21 includes a plurality of wiring layers 21a, 21b, and 21c that are sequentially stacked from the semiconductor chip 10 side. A plurality of lead wires 23 are formed in each of the wiring layers 21 a to 21 c, and each lead wire 23 passes through a via 24 and a via receiving portion 25 in contact with the via 24, and a surface (back surface) opposite to the semiconductor chip 10 in the interposer 21. ) Formed on the external terminal 26 for secondary mounting.

  In this way, each pad 15 formed on the semiconductor chip 10 is converted into an external terminal 26 having an interval (pitch) that can be secondarily mounted on a printed circuit board (not shown) or the like by interposing the interposer 21. Is done.

  Gold (Au) bumps, solder bumps, or the like are used for the bumps 20 formed on each pad electrode 15 of the semiconductor chip 10.

  The interposer 21 is composed of a resin substrate or the like whose main raw material is an organic resin material, and solder balls 27 or the like are used for connection between the external terminals 26 and the secondary mounting substrate.

  Further, the connecting portion between the semiconductor chip 10 and the interposer 21 is protected by hardening the injected underfill material 28 between the semiconductor chip 10 and the interposer 21. Further, the semiconductor chip 10 and the underfill material 28 are sealed with a sealing resin material 29 as necessary. Note that the mounting form shown in FIG. 2 is an example, and it is not always necessary to adopt this form in the present invention.

  FIG. 3A shows a plan view of the main part of the semiconductor integrated circuit device (semiconductor chip 10) according to the first embodiment of the present invention, and FIG. 3B shows a modification thereof.

  As shown in FIG. 3A, on the upper surface of the semiconductor chip 10 according to the first embodiment, that is, on the insulating layer 13, an imaginary line 16A connecting lattice points is 45 ° to the outer side of the semiconductor chip 10. A quadrangular lattice intersecting at an angle of is formed, and a pad electrode 15 is disposed on each lattice point. Here, the square lattice has a square, a rectangle, a parallelogram, or the like.

  Further, as shown in FIG. 3B, one of three imaginary lines 16B connecting lattice points is formed on the insulating layer 13 of the semiconductor chip 10 according to a modification of the first embodiment. Is formed in parallel with the outer side of the semiconductor chip 10, and pad electrodes 15 are arranged on the respective lattice points. Here, the triangular lattice constitutes a regular triangle, an acute triangle, or the like.

  As a feature of the first embodiment, the interval P1 between the pad electrodes 15 arranged substantially parallel to the outer side of the semiconductor chip 10 on the peripheral edge of the semiconductor chip 10 is larger than the lattice interval P2. For example, if the lattice points are square, the interval P1 is (√2) times the lattice interval P2, that is, about 1.4 times.

  Therefore, as shown in FIG. 3A, when the pad electrode 15 is arranged at each vertex of the square lattice and the imaginary line connecting the lattice points intersects the outer side of the semiconductor chip 10 at 45 °, The interval P1 between the pad electrodes 15 arranged substantially parallel to each side of the semiconductor chip 10 is the largest. As a result, even when the lattice pitch P2 is the minimum pitch, in the interposer 21, at least one lead wire 23 is disposed between the pad electrodes 15 disposed on the periphery of the pad electrode 15 disposed on the inner side of the semiconductor chip 10. Can be placed in between.

  Similarly, in one modification of the first embodiment, the interval P3 between the pad electrodes 15 arranged substantially parallel to the outer side of the semiconductor chip 10 on the peripheral edge of the semiconductor chip 10 is the lattice interval P4. Larger than For example, if the lattice point is an equilateral triangle, the interval P3 is (√3) times the lattice interval P4, that is, about 1.7 times.

  Therefore, as shown in FIG. 3B, when the pad electrode 15 is arranged at each vertex of the triangular lattice and one of the imaginary lines connecting the lattice points is parallel to the outer side of the semiconductor chip 10, The interval P3 between the pad electrodes 15 arranged substantially parallel to each side of the semiconductor chip 10 is the largest. As a result, even if the lattice spacing P4 is the minimum pitch, in the interposer 21, the pad electrode 15 in which at least one lead-out wiring 23 is arranged in the peripheral portion from the pad electrode 15 arranged inside the upper surface of the semiconductor chip 10. They can be placed between each other. In addition, in the present modification, the pad electrodes 15 can be arranged more densely than in the square lattice, and therefore, more pad electrodes 15 can be arranged efficiently per unit area.

  Hereinafter, a method for connecting the semiconductor chip 10 and the interposer 21 according to the first embodiment will be described with reference to the drawings.

  Here, as shown in the plan view of FIG. 4, a case where a plurality of pad electrodes 15 are arranged on the upper surface of the semiconductor chip 10 in a square lattice shape (shown in FIG. 3A) and at an equal pitch P is described. To do. 5 to 7 show connection examples of the wiring layers 21a to 21c of the interposer 21 when the semiconductor chip 10 shown in FIG. 4 is used. Here, for example, “a” is added to, for example, the lead-out wiring formed in the wiring layer 21a as in 23a to distinguish it from the other wiring layers 21b and 21c. The same applies to the other wiring layers 21b and 21c.

  In the following, as an example, the semiconductor chip 10 has a square shape with a side of 2 mm, the minimum width L of the lead wires 23a to 23c formed in the respective wiring layers 21a to 21c of the interposer 21 is 0.02 mm, and the minimum space S 0.02 mm, the diameter R required for forming the vias 24 a to 24 c penetrating the wiring layers 21 a to 21 c and the via receiving portions 25 a to 25 c that receive the vias is 0.2 mm, and the diameter a of the external terminal 26 is The pitch b of the external terminals 26 is 0.8 mm.

  As shown in FIGS. 4 to 7, in order to arrange the maximum number of terminals that can be connected by the interposer 21 on the semiconductor chip 10, the pitch determined by the processing limit of the vias 24, that is, the formation of the vias 24 and the via receiving portions 25. The pad electrodes 15 may be arranged at a pitch P = R + S determined by the sum of the minimum diameter R and the minimum space S required for the above.

  As shown in FIG. 4, here, the pitch P is 0.22 mm, and the pad electrodes 15 are arranged at an interval of 0.22 mm with an equal pitch P in a direction of 45 ° with each outer side of the semiconductor chip 10. In this case, 85 pad electrodes 15 can be arranged. However, it is calculated here that the pad electrode 15 can be disposed on the entire top surface of the semiconductor chip 10.

  In the first embodiment, as shown in FIGS. 5 and 6, in each wiring layer 21 a and 21 b of the interposer 21, between the pad connection terminals 22 positioned on the outermost periphery of the semiconductor chip 10, There is an interval through which the lead-out wiring 23 passes from the pad electrode 15 located in a line on the inner side from the outer periphery. Therefore, the pad electrodes 15 for two rows are connected to the inner side from the outermost periphery of the pad connection terminal 22. Therefore, it is possible to connect to the external terminal 26 using the lead-out wiring 23a in the wiring layer 21a and the lead-out wiring 23b in the wiring layer 21b. In the wiring layer 21a, 44 pad electrodes can be extracted, and in the wiring layer 21b, 28 pad electrodes can be extracted. Further, in the wiring layer 21 c, the central pad electrode 15 can be drawn right below, so that 13 pad electrodes 15 for three rows from the center of the semiconductor chip 10 can be connected to the external terminals 26.

  Therefore, in the first embodiment, the number of wiring layers of the interposer 21 necessary for extracting all of the plurality of pad electrodes 15 to the outside is three.

  As described above with reference to FIG. 19, in the case of the conventional example in which the plurality of pad electrodes 105 are arranged at equal pitches in the direction parallel to the respective sides of the semiconductor chip 100, the design conditions are the same and the interposer 111 is used. Requires four wiring layers 111a to 111d (see FIGS. 20 to 23). However, when the pad arrangement method according to the first embodiment of the present invention shown in FIG. 4 is adopted, 85 pad electrodes 15 which are four more than the number of conventional pad electrodes can be drawn out and necessary. It is possible to reduce the number of wiring layers of the interposer 21 by one layer.

  The same applies to the first modification example in which the pad electrodes 15 shown in FIG. 3B are arranged in a triangular lattice pattern.

  As described above, according to the first embodiment and the modification thereof, the plurality of pad electrodes 15 are arranged on the entire upper surface of the semiconductor chip 10 with the minimum pitch P, and the outer sides of the semiconductor chip 10 are arranged. The pad electrodes 15 arranged substantially parallel to the sides are arranged so that the distance between them is larger than the minimum pitch P. That is, the pad electrodes 15 are arranged on the peripheral edge portion of the semiconductor chip 10 at a pitch larger than the minimum pitch P. For this reason, when arranging and connecting the lead wires 23 in the interposer 21, at least one lead wire 23 is provided between the pad connecting terminals 22 in a region where the interval is larger than the minimum outer pitch P. it can. Therefore, by passing the lead-out wiring 23 that leads out the pad electrode 15 located in the inner region of the semiconductor chip 10 from the region wider than the minimum pitch P, the number of lead-out wires 23 per wiring layer can be increased. . As a result, the number of wiring layers constituting the interposer 21 necessary for providing the plurality of lead wirings 23 can be reduced as compared with the conventional case.

  Therefore, the manufacture of the interposer 21 can be simplified, the reliability as a semiconductor integrated circuit device can be improved, and the manufacturing cost can be reduced.

  In the first embodiment and the modification thereof, the configuration in which the arrangement of the plurality of pad electrodes 15 is regularly arranged on each lattice point of the square lattice or the triangular lattice has been described. do not have to. That is, even if the plurality of pad electrodes 15 are irregularly arranged, the plurality of pad electrodes 15 have a pitch P2 or P4 at which the lead wirings 23 cannot be arranged between the pad electrodes 15 on the semiconductor chip 10. What is necessary is just to arrange | position so that the space | interval of the pad electrodes 15 arrange | positioned and arrange | positioned on the peripheral part of the semiconductor chip 10 substantially in parallel with the outer side may become larger than the pitch P2 or P4.

  The interval larger than the minimum pitch P specifically refers to a pitch at which at least one lead-out wiring 23 can be arranged between the pad connection terminals 22 formed in the interposer 21.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 8A shows a planar configuration of a semiconductor integrated circuit device (semiconductor chip 10) according to the second embodiment of the present invention, and FIG. 8B shows a modification thereof. In FIG. 8A and FIG. 8B, the same components as those in FIG. 3A and FIG.

  As shown in FIG. 8A, on the upper surface of the semiconductor chip 10 according to the second embodiment, that is, the upper portion of the insulating layer 13, a virtual line 16A connecting lattice points is 0 ° with the outer side of the semiconductor chip 10. And a rectangular grid intersecting at an angle of less than 45 ° is formed, and a pad electrode 15 is disposed on each grid point. The square lattice has a square or a rectangle, a parallelogram, and the like.

  Further, as shown in FIG. 8B, one of three imaginary lines 16B connecting lattice points is formed on the insulating layer 13 of the semiconductor chip 10 according to a modification of the second embodiment. A triangular lattice intersecting with the outer side of the semiconductor chip 10 at an angle exceeding 0 ° and less than 45 ° is formed, and a pad electrode 15 is disposed on each lattice point. Here, the triangular lattice has a regular triangle, an acute triangle, or the like.

  In this way, when the arrangement direction of each pad electrode 15 is arranged at an angle of less than 45 ° with respect to the outer side of the semiconductor chip 15, as shown in FIG. In at least one place, the interval P1 between the pad electrodes 15 arranged substantially parallel to the outer side of the semiconductor chip 10 is larger than the lattice interval P2. For this reason, in the interposer 21, even if the lattice spacing P2 is the minimum pitch, the pad electrodes 15 in which at least one lead-out wiring 23 is arranged in the peripheral portion from the pads 15 arranged inside the upper surface of the semiconductor chip 10 Can be placed between. As a result, similarly to the first embodiment, the number of layers of the interposer 21 necessary for the lead-out wiring 23 can be reduced. Similarly, in the case shown in FIG. 8B, since the interval P3 is larger than the lattice interval P4, the number of layers of the interposer 21 can be reduced as in FIG. 8A.

  In addition, in the second embodiment and one modification thereof, the arrangement direction of each pad electrode 15 is shifted from the plane orientation of the cleaved surface of the semiconductor chip 10 (side of the semiconductor chip 10). Mechanical strength improves with respect to the stress which each pad electrode 15 receives at the time of mounting or after mounting.

  In the second embodiment and the modification thereof, the configuration in which the arrangement of the plurality of pad electrodes 15 is regularly arranged on each lattice point of the square lattice or the triangular lattice has been described. There is no need to be. That is, even if the plurality of pad electrodes 15 are irregularly arranged, the plurality of pad electrodes 15 have a pitch P2 or P4 at which the lead wirings 23 cannot be arranged between the pad electrodes 15 on the semiconductor chip 10. It is only necessary that the pad electrodes 15 disposed on the peripheral edge of the semiconductor chip 10 be arranged on the peripheral edge of the semiconductor chip 10 so as to have an interval larger than the pitch P2 or P4.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

  FIG. 9A shows a planar configuration of a semiconductor integrated circuit device (semiconductor chip 10) according to the third embodiment of the present invention, FIG. 9B shows a first modification of the third embodiment, FIG. 9C shows a second modification of the third embodiment. In FIG. 9A to FIG. 9C, the same components as those in FIG. 3A and FIG.

  As shown in FIG. 9A, in the third embodiment, the virtual line 16A connecting the lattice points is parallel to the outer side of the semiconductor chip 10, and the plurality of pad electrodes 15 are, for example, 4 Each pad electrode group 30 is configured, and the pad electrode groups 30 are arranged densely with one row and one column between adjacent ones, that is, with a spacing P1. As a result, the spacing between the pad electrodes 15 on the semiconductor chip 10 includes a lattice spacing P2 and a spacing P1 larger than the lattice spacing P2.

  Further, as shown in FIG. 9B, in the first modification of the third embodiment, the virtual lines 16A connecting the lattice points are arranged in parallel with the outer sides of the semiconductor chip 10, and The plurality of pad electrodes 15 are arranged so as to be dense at the center of the upper surface of the semiconductor chip 10 and sparse at the peripheral edge. Thereby, the space | interval P1 of the pad electrodes 15 in the peripheral part of the semiconductor chip 10 becomes larger than the lattice space | interval P2.

  In addition, as shown in FIG. 9C, in the second modification of the third embodiment, the virtual lines 16B of the respective lattices are arranged so as to be non-parallel, as shown in FIG. In a modification of the second embodiment, the plurality of pad electrode groups 30 are arranged so that the plurality of pad electrodes 15 are dense at the center of the upper surface of the semiconductor chip 10 and sparse at the peripheral edge. Thereby, the space | interval P3 of the pad electrodes 15 in the peripheral part of the semiconductor chip 10 becomes larger than the lattice space | interval P4.

  As described above, according to the third embodiment and each of the modifications, the region where the plurality of pad electrodes 15 are locally and sparsely arranged at least at one place on the upper surface of the semiconductor chip 10, particularly at the peripheral portion thereof. And having a region arranged densely in the central portion. For example, the arrangement shown in FIG.

  Therefore, in the interposer 21, even if the lattice spacing is the minimum pitch, at least one lead wiring 23 is disposed between the pad electrodes 15 disposed on the inner periphery of the upper surface of the semiconductor chip 10. Can be placed in between. As a result, as in the first embodiment, the number of interposer layers required for the lead-out wiring 23 can be reduced.

  The pad electrode 15 may be arranged in parallel with each of the outer sides of the semiconductor chip 10 as in the third embodiment and the first modification, and the semiconductor device as in the second modification. You may arrange | position so that the virtual line 16B of each grating | lattice may become non-parallel to each edge | side of the chip | tip 10 outside.

  Also in this embodiment, the arrangement of lattice points does not have to be regular, and may be irregular.

  Hereinafter, the difference in the number of wiring layers in the interposer between the case where the semiconductor chip 10 according to the third modification of the third embodiment is used and the case where the conventional semiconductor chip 100 is used will be described with reference to the drawings. .

  FIG. 10 shows a planar configuration of a semiconductor chip 10 according to a third modification of the third embodiment. FIG. 11 shows a planar configuration of an interposer 21 according to a third modification of the third embodiment. 12, 13, and 14 show the planar configurations of the conventional semiconductor chip 100 and interposer 111. Here, the planar dimensions of the semiconductor chips 10 and 100 and the minimum width L and the minimum space S of the lead wires 23 and 113a formed in the interposers 21 and 111 are the same as those in the first embodiment. That is, the semiconductor chips 10 and 100 have a square shape with a side of 2 mm, and the minimum width L of the lead wires 23, 113a and 113b formed in the wiring layers 21, 111a and 111b of the interposers 21 and 111 is 0.02 mm. The minimum space S is 0.02 mm, and it is necessary to form the vias 24, 114a and 114b penetrating the wiring layers 21, 111a and 111b and the via receiving portions 25, 115a and 115b receiving the vias 24, 114a and 114b. The diameter R is 0.2 mm, the diameter a of the external terminals 26 and 116 is 0.5 mm, and the pitch b of the external terminals 26 and 116 is 0.8 mm.

  As shown in FIGS. 10 and 11, the 61 pad electrodes 15 arranged roughly on the upper surface of the semiconductor chip 10 have a peripheral portion of the semiconductor chip 10 even when the pitch P is arranged at 0.22 mm. At least one region having a larger interval than the pitch P is formed. Therefore, the number of interposer wiring layers required to form the lead wirings 23 drawn from the 61 pad electrodes 15 is only one.

  On the other hand, the conventional semiconductor chip 100 shown in FIG. 12 shows a case where 56 pad electrodes 15 are arranged in two rows with a pitch P of 0.22 mm on the peripheral edge of the upper surface thereof. In this case, as shown in FIGS. 13 and 14, the number of wiring layers of the interposer 111 necessary for forming the lead wirings 113a and 113b drawn from the 56 pad electrodes 105 is two.

  As described above, according to the semiconductor chip according to this modification, a larger number of pad electrodes can be arranged than the arrangement of the pad electrodes in the conventional semiconductor chip, and the number of interposer wiring layers required for the arrangement can be reduced. Has the special effect of being able to.

  As described above, according to the third embodiment and each modification, the plurality of pad electrodes 15 are disposed locally on the upper surface of the semiconductor chip 10, that is, by providing a dense portion and a sparse portion at the periphery. As a result, the number of wiring layers of the interposer 21 necessary for drawing out the plurality of pad electrodes 15 can be reduced.

  In the present embodiment, the arrangement of the pad electrode group 30 is not limited to that shown in FIGS. 9A to 9C and FIG. 10. If the chip has a sparse region at the peripheral portion of the chip and a dense region at the central portion, the effect of the present invention can be obtained in that more lead electrodes from the pad electrode can be provided in the wiring layer of the interposer.

(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.

  FIG. 15A shows a planar configuration of a semiconductor integrated circuit device (semiconductor chip 10) according to the fourth embodiment of the present invention, FIG. 15B shows a first modification of the fourth embodiment, FIG. 15C shows a second modification of the fourth embodiment, and FIG. 15D shows a third modification of the fourth embodiment. In FIG. 15A to FIG. 15D, the same components as those in FIG. 3A and FIG.

  As shown in FIG. 15A, the semiconductor chip 10 according to the fourth embodiment includes a plurality of second semiconductor chips 10 arranged in a square lattice pattern on the entire surface other than the peripheral portion of the insulating layer 13 formed on the upper surface thereof. One pad electrode 15 </ b> A and a plurality of second pad electrodes 15 </ b> B arranged in a staggered manner in two rows on the periphery of the insulating layer 13. Here, the interval (pitch) between the second pad electrodes 15B is smaller than the interval (pitch) between the first pad electrodes 15A.

  Note that the second pad electrodes 15B are not necessarily arranged in two rows, and may be arranged in one row, that is, inline.

  The semiconductor chip 10 according to the fourth embodiment has a configuration in which the second pad electrode 15B is added to the configuration of the semiconductor chip 10 according to the first embodiment, and the first modification shown in FIG. The semiconductor chip 10 has a configuration in which a second pad electrode 15B is added to the configuration of the semiconductor chip 10 according to a modification of the first embodiment. Further, the semiconductor chip 10 according to the second modified example shown in FIG. 15C has a configuration in which a second pad 15B is added to the configuration of the semiconductor chip 10 according to the modified example of the second embodiment. The semiconductor chip 10 according to the third modification shown in FIG. 15D has a configuration in which the second pad electrode 15B is added to the configuration of the semiconductor chip 10 according to the first modification of the third embodiment.

  Here, the second pad electrode 15 </ b> B does not have to be disposed on the entire periphery of the semiconductor chip 10, and may be disposed along at least one side of the semiconductor chip 10. Moreover, it is not always necessary to arrange them at regular intervals, and they may be partially thinned out.

  As described above, when the semiconductor chip 10 according to the fourth embodiment and each modification is mounted on the interposer 21, the lead-out wiring 23 drawn out from the plurality of second pad electrodes 15B in FIG. 2 and FIG. It can be formed in the same wiring layer as the terminal 22, that is, 21a.

  On the other hand, as described above, the lead-out wiring 23 drawn out from the first pad electrode 15A needs to be connected to the lower wiring layers 21b and 21c through the via 24. Usually, the minimum diameter required for the via receiving portion 25 is larger than the minimum width of the pad connection terminal 22 required for connection to the bump 20 formed on the first pad electrode 15A. Accordingly, the outer second pad electrode 15B that can form the lead-out wiring 23 from the pad connection terminal 22 in the upper wiring layer 21a is compared with the inner first pad electrode 15A in which the via 24 needs to be formed. Can be arranged at a small pitch.

  As described above, the second pad electrode 15B having a smaller arrangement pitch than the first pad electrode 15A is arranged on the upper surface of the semiconductor chip 10 outside the first pad electrode 15A, so that the upper layer of the interposer 21 is formed. Since the number of pads that can be drawn out to the wiring layer 21a increases, it is possible to reduce the number of wiring layers of the interposer 21 necessary for forming the lead-out wiring drawn out from the same number of pad electrodes 15A and 15B.

  The semiconductor integrated circuit device according to the present invention is useful for mounting a semiconductor chip in which a plurality of pad electrodes are arranged on the upper surface of a semiconductor chip.

1 is a cross-sectional view showing a semiconductor integrated circuit device according to a first embodiment of the present invention. It is sectional drawing which shows an example of the mounting form of the semiconductor integrated circuit device which concerns on the 1st Embodiment of this invention. (A) is a top view which shows the semiconductor integrated circuit device based on the 1st Embodiment of this invention. (B) is a top view which shows the semiconductor integrated circuit device based on the modification of the 1st Embodiment of this invention. 1 is a plan view illustrating a semiconductor integrated circuit device according to a first embodiment of the present invention, which is mounted on an interposer. FIG. 1 is a plan view showing an upper wiring layer of an interposer for mounting a semiconductor integrated circuit device according to a first embodiment of the present invention. 1 is a plan view showing a middle wiring layer of an interposer on which a semiconductor integrated circuit device according to a first embodiment of the present invention is mounted. 1 is a plan view showing a wiring layer below an interposer on which a semiconductor integrated circuit device according to a first embodiment of the present invention is mounted. (A) is a top view which shows the semiconductor integrated circuit device based on the 2nd Embodiment of this invention. (B) is a top view which shows the semiconductor integrated circuit device based on the modification of the 2nd Embodiment of this invention. (A) is a top view which shows the semiconductor integrated circuit device based on the 3rd Embodiment of this invention. (B) is a top view which shows the semiconductor integrated circuit device based on the 1st modification of the 3rd Embodiment of this invention. (C) is a top view which shows the semiconductor integrated circuit device based on the 2nd modification of the 3rd Embodiment of this invention. It is a semiconductor integrated circuit device which concerns on the 3rd modification of the 3rd Embodiment of this invention, Comprising: It is a top view explaining the mounting form to an interposer. It is a top view which shows the interposer which mounts the semiconductor integrated circuit device based on the 3rd modification of the 3rd Embodiment of this invention. FIG. 11 is a plan view illustrating a conventional semiconductor integrated circuit device for comparison, which is mounted on an interposer. It is a top view which shows the wiring layer of the upper layer of the interposer which mounts the conventional semiconductor integrated circuit device for a comparison. It is a top view which shows the wiring layer of the lower layer of the interposer which mounts the conventional semiconductor integrated circuit device for a comparison. (A) is a top view which shows the semiconductor integrated circuit device based on the 4th Embodiment of this invention. (B) is a top view which shows the semiconductor integrated circuit device based on the 1st modification of the 4th Embodiment of this invention. (C) is a top view which shows the semiconductor integrated circuit device based on the 2nd modification of the 4th Embodiment of this invention. (D) is a top view which shows the semiconductor integrated circuit device based on the 3rd modification of the 4th Embodiment of this invention. It is sectional drawing which shows the conventional semiconductor integrated circuit device. It is sectional drawing which shows an example of the mounting form of the conventional semiconductor integrated circuit device. It is a conventional semiconductor integrated circuit device, and is a plan view for explaining a mounting form on an interposer. It is a top view which shows the wiring layer of the 1st layer of the interposer which mounts the conventional semiconductor integrated circuit device. It is a top view which shows the wiring layer of the 2nd layer of the interposer which mounts the conventional semiconductor integrated circuit device. It is a top view which shows the wiring layer of the 3rd layer of the interposer which mounts the conventional semiconductor integrated circuit device. It is a top view which shows the wiring layer of the 4th layer of the interposer which mounts the conventional semiconductor integrated circuit device.

Explanation of symbols

10 Semiconductor integrated circuit device (semiconductor chip)
11 substrate 12 element 13 insulating layer 14 wiring 15 pad 15A first pad 15B second pad 16A virtual line 16B virtual line 20 bump 21 interposer 21a wiring layer 21b wiring layer 21c wiring layer 22 pad connection terminal 23 lead wiring 23a lead Wiring (upper layer)
23b Lead-out wiring (middle layer)
23c Lead-out wiring (lower layer)
24 Via 24a Via (upper layer)
24b Via (middle layer)
24c Via (lower layer)
25 Via receiving part 25a Via receiving part (upper layer)
25b Via receiving part (middle layer)
25c Via receiving part (lower layer)
26 External terminal 27 Solder ball 28 Underfill material 29 Sealing resin material 30 Pad group

Claims (11)

A semiconductor substrate having a plurality of elements formed on the main surface;
A plurality of first pad electrodes formed on the semiconductor substrate and electrically connected to the plurality of elements;
The plurality of first pad electrodes are respectively arranged on each lattice point of a square lattice shape or a triangular lattice shape, and at least one of the plurality of lines connecting the lattice points is with respect to an edge of the semiconductor substrate A semiconductor integrated circuit device characterized by being non-parallel.   2. The semiconductor integrated circuit device according to claim 1, wherein the non-parallel lines intersect with an edge of the semiconductor substrate at an angle of 45 [deg.].   2. The semiconductor integrated circuit device according to claim 1, wherein the non-parallel lines intersect with an edge of the semiconductor substrate at an angle of less than 45 [deg.].   2. The semiconductor according to claim 1, wherein a distance between adjacent first pad electrodes arranged on an outermost periphery at an edge of the semiconductor substrate is larger than a distance between nearest lattice points at each lattice point. Integrated circuit device. A semiconductor substrate having a plurality of elements formed on the main surface;
A plurality of first pad electrodes formed on the semiconductor substrate and electrically connected to the plurality of elements;
The semiconductor integrated circuit device according to claim 1, wherein the plurality of first pad electrodes are arranged on at least a part of each lattice point of a square lattice shape or a triangular lattice shape.   6. The semiconductor integrated circuit device according to claim 5, wherein the plurality of first pad electrodes are arranged so that the arrangement density is sparser in a peripheral portion than in a central portion of the semiconductor substrate.   7. The semiconductor integrated circuit device according to claim 5, wherein at least one of the plurality of lines connecting the respective lattice points is non-parallel to an edge of the semiconductor substrate.   8. The semiconductor according to claim 7, wherein a distance between the adjacent first pad electrodes arranged on the outermost periphery at an edge of the semiconductor substrate is larger than a distance between nearest lattice points at each of the lattice points. Integrated circuit device. A plurality of second pad electrodes formed on a region outside the plurality of first pad electrodes on the semiconductor substrate and electrically connected to the plurality of elements;
9. The semiconductor integrated circuit device according to claim 1, wherein a distance between the adjacent second pad electrodes is smaller than a minimum value of an interval between the first pad electrodes. 10. .   The semiconductor device according to claim 9, wherein the plurality of second pad electrodes are arranged in a line along a peripheral edge portion of the semiconductor substrate.   11. The semiconductor device according to claim 10, wherein the plurality of second pad electrodes are arranged in two rows in a staggered manner along a peripheral portion of the semiconductor substrate.

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