JP2007164913A - Ferroelectric storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric storage device which improves a sense margin accompanying the reduction of a cell array degree of integration and bit line capacity. <P>SOLUTION: The ferroelectric storage device includes main bit lines MBL1 and MBL1b; sub-bit lines SBL1 and SBL1b; a ferroelectric capacitor; memory cells which are provided at positions at which a word line crosses the SBL1 and the SBL1b; a transistor TR1 which connects the SBL1 with the MBL1; a transistor DTR1 which grounds the sub-bit line SBL1; a transistor TR1b which connects the sub-bit line SBL1b with the MBL1b; a transistor DTR1b which grounds the SBL1b; a selection line BLSEL1 which is connected in common to each of the gates of the TR1 and DTR1b; a selection line BLSEL1b which is connected in common to each of the gates of the DTR1 and TR1b; a plate line PL1 to which the memory cell of the SBL1 is connected; and a plate line PL2 to which the memory cell of the SBL1b is connected. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a ferroelectric memory device.

  In order to increase the memory capacity, it is required to increase the number of cells in the bit line direction in the cell array. On the other hand, in order to increase the sense margin and increase the speed, it is required to reduce the bit line capacitance.

  As a technique for reducing the bit line capacitance, for example, a hierarchical bit line system is known. In order to increase the memory capacity, it is important to apply a 1T1C (1 Transistor 1 Capacitor) type ferroelectric memory device. In this case, the configuration of the cell array includes a reference signal caused by noise. A folded bit line method that can reduce the margin of the sense amplifier and reduce the area of the sense amplifier is conceivable (see Patent Document 1).

However, according to this conventional configuration, when the folded bit line method is applied, the memory cells and the reference cells storing predetermined information are alternately shifted in the word line direction, and different word lines are used. It must be controlled, and it cannot be said that the degree of integration of the cell array is high, and the word line driver is required twice, and the circuit configuration is complicated.
Japanese Patent Laid-Open No. 9-7377

  SUMMARY OF THE INVENTION An object of the present invention is to provide a ferroelectric memory device capable of improving the sense margin accompanying the improvement of the degree of integration of the cell array and the reduction of the bit line capacitance.

(1) A ferroelectric memory device according to an embodiment of the present invention includes:
First and second main bit lines;
First and second sub-bit lines;
A memory cell including a ferroelectric capacitor and provided at an intersection of a word line and the first and second sub-bit lines;
A first transistor connecting the first sub-bit line and the first main bit line;
A second transistor for grounding the first sub-bit line;
A third transistor connecting the second sub-bit line and the second main bit line;
A fourth transistor for grounding the second sub-bit line;
A first select line commonly connected to the gates of the first and fourth transistors;
A second select line commonly connected to the gates of the second and third transistors;
A first plate line to which memory cells of the first sub-bit line are connected;
A second plate line to which the memory cells of the second sub-bit line are connected;
including.

  According to this, when the potential for turning on the first and fourth transistors is supplied to the first select line, the first sub bit line is connected to the first main bit line, and the second main bit is connected. The wire is grounded. Similarly, when the potential for turning on the second and third transistors is supplied to the second select line, the first main bit line is grounded, and the second sub bit line is connected to the second main bit line. Connected. According to this, for example, while reading the information of the memory cell through one main bit line, the reference signal can be supplied through the other main bit line that is grounded. That is, since the wiring for supplying the reference signal also serves as the supply of the read signal for the memory cell, the circuit configuration can be simplified and the degree of integration of the cell array can be improved. Further, according to the above configuration, the junction capacity of the memory cell can be reduced by a so-called hierarchical bit line system. Therefore, it is possible to improve the sense margin and increase the speed.

(2) In this ferroelectric memory device,
In one of the first and second main bit lines, a read signal stored in the memory cell is supplied to a sense amplifier, and in the other, a reference signal to be compared with the read signal is supplied to the sense amplifier. It may be.

(3) In this ferroelectric memory device,
Further comprising first and second reference cells in which the reference signal is stored;
The first reference cell corresponds to the first main bit line, and a transfer gate is connected to the second select line,
The second reference cell may correspond to the second main bit line, and a transfer gate may be connected to the first select line.

  According to this, when the information of the memory cell is read from the first main bit line, the reference signal of the second reference cell can be supplied via the second main bit line. On the other hand, when the information of the memory cell is read from the second main bit line, the reference signal of the first reference cell can be supplied through the first main bit line.

  In addition, since the first and second reference cells are connected to either the first or second select line, there is no need to form a control line for controlling the operation of the reference cell. Further simplification of the circuit configuration can be achieved.

(4) In this ferroelectric memory device,
The first reference cell is connected to the second plate line;
The second reference cell may be connected to the first plate line.

(5) In this ferroelectric memory device,
The capacitor size of each of the first and second reference cells may be substantially the same as the capacitor size of the memory cell.

  According to this, for example, since a plurality of cells including a memory cell and a reference cell can be formed by the same process, process variations can be suppressed.

  In addition, since the sub bit line is connected to the main bit line to which the read signal is transmitted, and the sub bit line is not connected to the main bit line to which the reference signal is transmitted, the capacity is reduced by the amount corresponding to the sub bit line in the latter. The Therefore, even if the capacitor sizes of the memory cell and the reference cell are the same, the reference signal can be easily set to a voltage different from the read signal.

(6) In this ferroelectric memory device,
In the first and second reference cells, “0” data may be stored as the reference signal.

  According to this, for example, when extracting information from a memory cell and a reference cell each holding “0” data, a sub bit line is connected to a main bit line to which a read signal of the memory cell is transmitted. On the other hand, since the sub bit line is not connected to the main bit line to which the reference signal is transmitted, the capacity is reduced by the amount corresponding to the sub bit line in the latter. Therefore, since a voltage higher than the “0” data of the memory cell is extracted from the reference cell, for example, an intermediate voltage between “1” data and “0” data can be easily obtained.

(7) In this ferroelectric memory device,
The plurality of first and second main bit lines may be arranged so that one of them is adjacent to each other.

(8) In this ferroelectric memory device,
The first and second plate lines are provided to intersect the word line,
The first plate line is shared by adjacent first main bit lines,
The second plate line may be shared by the adjacent second main bit lines.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1. Configuration of Ferroelectric Memory Device FIG. 1 is a circuit diagram showing an example of a ferroelectric memory device according to an embodiment of the present invention.

  A ferroelectric memory device (semiconductor memory device) 100 includes a memory cell array 10. Memory cell array 10 includes a plurality of memory cells MC1-0b to n-2,... Including ferroelectric capacitors. The memory cell MC1-1 will be described by taking the memory cell MC1-1 as an example. The memory cell MC1-1 includes a ferroelectric capacitor Cfe and a transfer gate Tg (for example, an N-type MOS transistor). One end of the ferroelectric capacitor Cfe is connected to one of the source / drain of the transfer gate Tg, and the other end is connected to the plate line PL1. Further, the word line WL1 is connected to the gate of the transfer gate Tg, the sub-bit line SBL1 is connected to one of the source / drain, and one end of the ferroelectric capacitor Cfe is connected to the other of the source / drain. In the example shown in FIG. 1, a so-called 1T1C (1 Transistor 1 Capacitor) type memory cell is shown.

  In the ferroelectric memory device 100, a plurality of word lines WL1 to WLn, a main bit line MBLk (k = 0, 1, 2,...) As a first main bit line, and a second main bit line Main bit line MBLkb (k = 0, 1, 2,...), A sub bit line SBLk (k = 0, 1, 2,...) As a first sub bit line, and a sub bit line as a second sub bit line SBLkb (k = 0, 1, 2,...) Are provided. In the ferroelectric memory device 100, a plurality of pairs of main bit lines MBLk, MBLkb are provided, and a plurality of pairs of sub bit lines SBLk, SBLkb are also provided. The main bit line and the sub bit line are arranged in parallel to each other, and they are arranged so as to cross the word line.

  The plurality of pairs of main bit lines MBLk, MBLkb are arranged so that one of them (that is, the main bit lines MBLk or the main bit lines MBLkb) are adjacent to each other. In the example shown in FIG. 1, main bit lines MBL0b, MBL0, MBL1, MBL1b, MBL2b, MBL2,... Are arranged in order.

  The same sense amplifier SA is connected to the pair of main bit lines MBLk, MBLkb. In the present embodiment, a so-called hierarchical bit line system is employed, in which one main bit line MBLk corresponds to a sub bit line SBLk, and the other main bit line MBLkb corresponds to a sub bit line SBLkb. . Further, the same word lines WL1 to WLn intersect the plurality of pairs of sub bit lines SBLk and SBLkb.

  Each main bit line may correspond to a sub bit line other than the illustrated sub bit line. In this case, other word lines (not shown) intersect with the other sub-bit lines, and other memory cells (not shown) are arranged at the intersecting positions.

  Memory cells MC1-0b to n-2,... Are provided at intersections between the plurality of pairs of sub-bit lines SBLk and SBLkb and the plurality of word lines WL1 to WLn, respectively. For example, in the case of the memory cells MC1-0b to 1-2 in the first row of the memory cell array 10, the memory cells MC1-0b to 1-2 are connected to the sub bit lines SBL0b to SBL2, respectively. A word line WL1 is commonly connected to the gates of the transfer gates Tg.

  One sub-bit line SBLk includes a transistor TRk (k = 0, 1, 2,...) As a first transistor connected to the main bit line MBLk and a transistor DTRk (k = 0) as a second transistor to be grounded. , 1, 2,... The transistors TRk and DTRk are provided at both ends of the sub bit line SBLk, and the sub bit line SBLk is connected to the main bit line MBLk through the transistor TRk. Specifically, in the transistor TRk, one of the source / drain is connected to the sub bit line SBLk, and the other is connected to the main bit line MBLk. In the transistor DTRk, one of the source / drain is connected to the sub bit line SBLk, and the other is grounded.

  The other sub-bit line SBLkb includes a transistor TRkb (k = 0, 1, 2,...) As a third transistor connected to the main bit line MBLkb and a transistor DTRkb (k = 0) as a fourth transistor to be grounded. , 1, 2,... The transistors TRkb and DTRkb are provided at both ends of the sub bit line SBLkb, and the sub bit line SBLkb is connected to the main bit line MBLkb via the transistor TRkb. Specifically, in the transistor TRkb, one of the source / drain is connected to the sub bit line SBLkb, and the other is connected to the main bit line MBLkb. In the transistor DTRkb, one of the source / drain is connected to the sub bit line SBLkb, and the other is grounded.

  The transistor TRk (or transistor DTRk) connected to the sub bit line SBLk is arranged on the opposite side to the transistor TRkb (or transistor DTRkb) connected to the sub bit line SBLkb in the main bit line direction. Transistors TRk and TRkb function as switching elements for connecting each sub bit line to the main bit line, and transistors DTRk and DTRkb function as a switching element for discharging each sub bit line. Each of the transistors can be composed of, for example, an N-type MOS transistor.

  The electrical connection of the sub bit lines SBLk and SBLkb is controlled based on signals supplied to the select line BLSEL1 as the first select line and the select line BLSEL1b as the second select line. The select lines BLSEL1, 1b are controlled by a not-shown select line driver, and only select lines BLSELk, BLSELkb (k = 0, 1, 2,...) Corresponding to the memory cells to be accessed are set to the H level. An L level signal is supplied to the other select lines.

  As shown in FIG. 1, in the pair of sub-bit lines SBLk and SBLkb, the gates of the pair of transistors TRk and TRkb (or transistors DTRk and DTRkb) are connected to different select lines. Specifically, the gates of the transistor TRk of the sub bit line SBLk and the transistor DTRkb of the sub bit line SBLkb are commonly connected to the select line BLSEL1. The select line BLSEL1b is commonly connected to the gates of the transistor DTRk of the sub bit line SBLk and the transistor TRkb of the sub bit line SBLkb. Thus, when the H level (for example, the power supply potential VDD) is supplied to one of the select lines BLSEL1 and 1b, one of the pair of sub bit lines SBLk and SBLkb is connected to the corresponding main bit line, and the other is grounded. it can.

  In the example shown in FIG. 1, in the ferroelectric memory device 100, a plurality of plate lines PL0, 1, 2, 3,... Intersect with a plurality of word lines WL1 to WLn (in other words, sub-bit lines SBLk and SBLkb). In parallel). For example, the plate line PL1 is connected to each ferroelectric capacitor of the plurality of memory cells MC1-1 to n-1 connected to the sub bit line SBL1. A plurality of plate lines PL0, 1, 2, 3,... Are controlled by a plate line driving unit PLDrv.

  As shown in FIG. 1, the memory cell of the sub bit line SBLk is connected to the first plate line (for example, the plate line PL1 in the case of the memory cell of the sub bit line SBL1), and the memory cell of the sub bit line SBLkb is It is connected to a plate line (for example, plate line PL2 for sub-bit line SBL1b). As a result, different plate voltages can be supplied to the memory cells of the sub bit lines SBLk and SBLkb.

  In the example shown in FIG. 1, the plate line PL1 is shared by adjacent sub-bit lines SBL0 and SBL1 (that is, main bit lines MBL0 and MBL1), and the plate line PL2 is adjacent to the sub-bit lines SBL1b and SBL2b (that is, Main bit lines MBL1b and MBL2b) are shared. The plate line PL1 is controlled by a predetermined plate line driving unit PLDrv, and the plate line PL2 is controlled by another plate line driving unit PLDrv. Since the sub bit lines SBL0, 1, 2,... (Or sub bit lines SBL0b, 1b, 2b) have the same operation state controlled based on the select lines BLSEL1, 1b, the control signal (PLDrv) That is, the plate line) can be shared.

  In the example shown in FIG. 1, one plate line driving unit PLDrv is provided for every two main bit lines MBLk (or main bit line MBLkb). Alternatively, one plate line driving unit may be provided for 2m (m = 2 or more) main bit lines MBLk (or main bit lines MBLkb). Alternatively, one plate line and one plate line driving unit may be provided for each main bit line.

  In the ferroelectric memory device 100, a reference cell RCk (k = 0, 1, 2,...) As a first reference cell and a reference cell RCkb (k = 0, 1, 2,...) As a second reference cell. , ...) are provided. The reference cells RCk and RCkb are cells that generate a reference signal for comparison with a read signal read from the memory cell, and the reference cells RCk and RCkb have the same configuration. The reference cell RC1 will be described as an example. The reference cell 1 includes a ferroelectric capacitor Cfe and a transfer gate Tg (for example, an N-type MOS transistor). One end of the ferroelectric capacitor is connected to one of the source / drain of the transfer gate Tg, and the other end is connected to the plate line PL2. The second select line BLSEL1b is connected to the gate of the transfer gate Tg, the main bit line MBL1 is connected to one of the source / drain, and one end of the ferroelectric capacitor Cfe is connected to the other of the source / drain. Has been. In the example shown in FIG. 1, a so-called 1T1C (1 Transistor 1 Capacitor) type reference cell is shown.

  One reference cell RCk is provided corresponding to the main bit line MBLk. Specifically, one end of the ferroelectric capacitor is connected to the main bit line MBLk via a transfer gate. The other reference cell RCkb is provided corresponding to the main bit line MBLkb. Specifically, one end of the ferroelectric capacitor is connected to the main bit line MBLkb via a transfer gate.

  In each reference cell RCk, RCkb, the other end of the ferroelectric capacitor is connected to a different plate line. Specifically, the reference cell RCk is connected to a second plate line connected to the sub bit line SBLkb (ie, the main bit line MBLkb), and the reference cell RCkb is connected to the sub bit line SBLk (ie, the main bit line MBLk). Connected to the first plate line.

  The transfer gate of the reference cell RCk is connected to a select line BLSEL1b as a second select line, and the transfer gate of the reference cell RCkb is connected to a select line BLSEL1 as a first select line.

  Reference cells RCk, RCkb may have substantially the same configuration as memory cells MC1-0b to n-2,. Specifically, the size, shape, material, and the like of each component (capacitor, transfer gate) of the reference cells RCk, RCkb and the memory cell may be substantially the same. For example, the memory cells RCk and RCkb and the memory cell can have substantially the same capacitor size. According to this, for example, since a plurality of cells including a memory cell and a reference cell can be formed by the same process, process variations can be suppressed.

2. Operation of Ferroelectric Memory Device Next, an example of the operation of the ferroelectric memory device shown in FIG. 1 will be described. FIG. 2 is a diagram for explaining the waveform of a signal on each control line (word line, bit line, etc.) during data reading. Hereinafter, a pair of main bit lines MBL1, MBL1b will be described as an example.

  First, at time t1, an H level potential (for example, power supply potential VDD) is supplied to the select line BLSEL1, and at time t1, the select line BLSEL1b is kept at an L level potential (for example, 0 V).

  As a result, the transistors TR1 and DTR1b connected to the select line BLSEL1 are turned on, and the transistors DTR1 and TR1b connected to the select line BLSEL1b are turned off. As a result, one sub bit line SBL1 is connected to the main bit line MBL1, and the other sub bit line SBL1b is grounded. In other words, the sub bit line SBL1 is connected to the main bit line MBL1, but the main bit line MBL1b is electrically disconnected from the sub bit line SBL1b.

  Also, the transfer gate of the reference cell RC1b among the reference cells RC1 and RC1b is turned on by the above operation of the select lines BLSEL1 and 1b. As a result, one end of the ferroelectric capacitor of the reference cell RC1b and the main bit line MBL1b are electrically connected.

  Next, at time t2, one of the plurality of word lines WL1 to WLn is selected. For example, the word line WL1 is selected as shown in FIG. That is, an H level potential is supplied to the word line WL1. Thereby, each transfer gate of the plurality of memory cells MC1-0b to 1-2,... Connected to the word line WL1 is turned on. As a result, the pair of main bit lines MBL1, MBL1b will be described. The ferroelectric capacitor of the memory cell MC1-1 is connected to the main bit line MBL1 through the transistor TR1, and the ferroelectric capacitor of the memory cell MC1-1b is It is grounded through the transistor DTR1b.

  After that, at time t3, an H level potential is supplied to the plate line PL1 connected to the memory cell MC1-1. As a result, charge is taken out from the ferroelectric capacitor of the memory cell MC1-1, and a read signal corresponding to data “1” or “0” stored in advance appears on the main bit line MBL1. Further, while supplying an H level potential to the plate line PL1, the plate line PL2 maintains an L level potential state. As a result, both ends of the ferroelectric capacitor of the memory cell MC1-2 are at the same potential (for example, ground potential) and no electric field is applied, so that data stored in the ferroelectric capacitor in advance is destroyed. It is held without.

  Further, by supplying an H level potential to the plate line PL1, charges are taken out from the ferroelectric capacitor of the reference cell RC1b, and a reference signal corresponding to prestored data (for example, “0” data) is generated. It appears on the main bit line MBL1b.

Here, the reference cell RC1b supplies a reference signal to the main bit line MBL1b is, since in the operation to the main bit line MBL1b not connected sub-bit line SBL1B, the bit line capacitance C _BL1b applied to the main bit line MBL1b is This is smaller than the bit line capacitance C _BL1 applied to the main bit line MBL1. Specifically, if the capacity of the main bit line MBL1 is C _MBL1 , the capacity of the main bit line MBL1b is C _MBL1b , and the capacity of the sub bit line SBL1 is C _SBL1 ,
C _BL1 = C _MBL1 + C _SBL1
C _BL1b = C _MBL1b
If the relationship is established and the capacity C _MBL1 and C _MBL1b are almost the same,
C _BL1 > C _BL1b
The relationship is established. As a result, when the reference cell RC1b connected to the main bit line MBL1b stores the same “0” data as the memory cell MC1-1 to be read (that is, the same charge amount indicating “0” data), the main bit In the line MBL1b, the capacity is reduced by the amount corresponding to the sub bit line SBL1, so that a voltage higher than that of the main bit line MBL1 is extracted. Therefore, as described above, even if the capacitor sizes of the memory cell and the reference cell are the same, the reference signal can be easily converted to a voltage different from the read signal (for example, “1” data and “0” data of the memory cell). Intermediate voltage).

  As shown in FIG. 2, finally, at time t4, the sense amplifier SA is turned on, for example, the voltage indicating the read signal appearing on the main bit line MBL1 is amplified, and the comparison with the reference signal can be performed accurately. .

  In the above description, the example in which the read signal from the memory cell is supplied to the main bit line MBL1 and the reference signal from the reference cell RC1b is supplied to the main bit line MBL1b has been described. It is clear that the present invention is not limited to this. For example, by supplying an L level potential to the select line BLSEL1 and an H level potential to the select line BLSEL1b, the reference signal from the reference cell RC1 is supplied to the main bit line MBL1, and the main bit line MBL1b has a memory. A read signal from the cell can be supplied. It is also clear that the pair of main bit lines MBL1, MBL1b is merely an example, and that the above description can be applied to the main bit lines MBLk, MBLkb.

  According to the present embodiment, when the potential for turning on the transistors TRk and DTRkb is supplied to the select line BLSEL1, the sub bit line SBLk is connected to the main bit line MBLk, and the main bit line MBLkb is grounded. Similarly, when the potential for turning on the transistors DTRk and TRkb is supplied to the select line BLSEL1b, the main bit line MBLk is grounded, and the sub bit line SBLkb is connected to the main bit line MBLkb. According to this, for example, while reading the information of the memory cell through one main bit line, the reference signal can be supplied through the other main bit line that is grounded. That is, since the wiring for supplying the reference signal also serves as the supply of the read signal for the memory cell, the circuit configuration can be simplified and the degree of integration of the cell array can be improved. Further, according to the above configuration, the junction capacity of the memory cell can be reduced by a so-called hierarchical bit line system. Therefore, it is possible to improve the sense margin and increase the speed.

  More specifically, according to the present embodiment, when memory cell information is read from the main bit line MBLk, the reference signal of the reference cell RCkb can be supplied via the main bit line MBLkb. On the other hand, when the memory cell information is read from the main bit line MBLkb, the reference signal of the reference cell RCk can be supplied through the main bit line MBLk.

  Further, each reference cell RCk, RCkb has a transfer gate connected to one of the select lines BLSEL1, 1b, so that it is not necessary to newly form a control line for controlling the operation of the reference cell, and the circuit configuration can be further simplified. Can be achieved.

  FIG. 3 is a circuit diagram showing a modification of the ferroelectric memory device according to the embodiment of the present invention. In the example shown in FIG. 3, the reference cell described above is omitted, and the content described based on FIG. 1 can be applied to other configurations. Also in this modification, as in the above-described example, the reference signal can be supplied via the other main bit line that is grounded while the information of the memory cell is read via one main bit line.

  As another modification, a plurality of plate lines may be provided in parallel with the plurality of word lines WL1 to WLn. An example will be described with reference to FIG. 3. Two plate lines are provided for each of the word lines WL1 to WLn, and a memory cell corresponding to the sub-bit line SBLk is connected to one of the two plate lines. On the other hand, a memory cell corresponding to the sub bit line SBLkb may be connected. In this case, the two plate lines are controlled by different plate line driving units.

  The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

1 is a diagram showing a circuit configuration of a ferroelectric memory device according to an embodiment of the present invention. The figure which shows an example of operation | movement of the ferroelectric memory device based on embodiment of this invention. The figure which shows the circuit structure of the ferroelectric memory device based on the modification of embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Ferroelectric memory device 10 ... Memory cell

Claims (8)

First and second main bit lines;
First and second sub-bit lines;
A memory cell including a ferroelectric capacitor and provided at an intersection of a word line and the first and second sub-bit lines;
A first transistor connecting the first sub-bit line and the first main bit line;
A second transistor for grounding the first sub-bit line;
A third transistor connecting the second sub-bit line and the second main bit line;
A fourth transistor for grounding the second sub-bit line;
A first select line commonly connected to the gates of the first and fourth transistors;
A second select line commonly connected to the gates of the second and third transistors;
A first plate line to which memory cells of the first sub-bit line are connected;
A second plate line to which the memory cells of the second sub-bit line are connected;
Including a ferroelectric memory device. The ferroelectric memory device according to claim 1,
In one of the first and second main bit lines, a read signal stored in the memory cell is supplied to a sense amplifier, and in the other, a reference signal to be compared with the read signal is supplied to the sense amplifier. A ferroelectric memory device. The ferroelectric memory device according to claim 2, wherein
Further comprising first and second reference cells in which the reference signal is stored;
The first reference cell corresponds to the first main bit line, and a transfer gate is connected to the second select line,
The ferroelectric memory device, wherein the second reference cell corresponds to the second main bit line, and a transfer gate is connected to the first select line. The ferroelectric memory device according to claim 3, wherein
The first reference cell is connected to the second plate line;
The ferroelectric memory device, wherein the second reference cell is connected to the first plate line. The ferroelectric memory device according to claim 3 or 4, wherein:
A ferroelectric memory device, wherein the capacitor size of each of the first and second reference cells is substantially the same as the capacitor size of the memory cell. The ferroelectric memory device according to any one of claims 3 to 5,
A ferroelectric memory device in which “0” data is stored as the reference signal in the first and second reference cells. The ferroelectric memory device according to any one of claims 1 to 6,
The ferroelectric memory device, wherein the plurality of first and second main bit lines are arranged so that one of them is adjacent to each other. The ferroelectric memory device according to claim 7, wherein
The first and second plate lines are provided to intersect the word line,
The first plate line is shared by adjacent first main bit lines,
The ferroelectric memory device, wherein the second plate line is shared by adjacent second main bit lines.

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