JP2007159224A - Apparatus and method for driving load - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem wherein in a method in which a current is directly PWM-controlled, based on the result of detection of the current, the lower limit of pulse width is relatively increased, therefore, attenuation in load current cannot follow a rapidly decreasing target current or a low target current, and the difference between the load current and the target currents is increased. <P>SOLUTION: Constructions for more actively controlling current attenuation are provided so that a load current accurately follows a target current even when the magnitude of the load current is larger than the magnitude of the target current at start of PWM control. One construction is for increasing attenuation when a current flows back. Another construction is for applying a current in an opposite direction so that when the load current exceeds the target current, the load current is attenuated to the target current. These control constructions are combined according to the state of load driving. Thus, a load current is made to accurately follow a rapidly decreasing target current or a target current of low level. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a load driving device and a load driving method for controlling a current value, and is particularly useful for driving an inductive load such as a motor or an actuator as a load.

As a device for PWM control of the current of the inductive load, the current value is controlled by operating the drive switch element so that the current value to be controlled increases toward the current value of the predetermined control target during the PWM ON period. A configuration is known in which when the target current value is reached, the drive switch element is operated so as to return to the PWM OFF state. This configuration is described in Patent Document 1, for example. Further, Patent Document 2 discloses a configuration in which this method is developed to realize a smooth current waveform even with PWM control.
JP-A-11-18474 JP2003-174789

  FIG. 15 shows a basic circuit configuration of the current control method disclosed in Patent Document 1 described above. An outline of the operation of FIG. 15 will be described below with reference to a timing chart shown in FIG. In response to the energization switching signal, the energization control circuit 14 turns on any of the high potential side drive switches 1p, 2p, 3p, and further PWM drives any of the low potential side drive switches 4p, 5p, 6p. Here, for the sake of simplicity, description will be made assuming that the high potential side drive switch 1 is in the on state and the low potential side drive switch 5 is in the PWM drive state.

  FIGS. 16A and 16B show the ON start timing and ON end timing in the low potential side drive switch in the PWM drive state. In FIG. 16C, 31Ap is a current flowing through the current detection resistor 10p, and 32Ap is a load current flowing through the motor windings 7p and 8p. 33Ap is a target current level given from the command signal input terminal 15p. The ON start timing is given by the pulse generation circuit 11p in FIG. 15, and the ON end timing is given by the comparator 13p in FIG. 15p.

  The RS flip-flop 12p is latched on at the ON start timing shown in FIG. 16A by the set pulse given by the pulse generation circuit 11p. The low potential power supply side drive switch 5p in the PWM drive state is turned on at this on start timing, and the load current 32Ap starts to increase. The load current 32Ap that has started to increase is detected by the current detection resistor 10p as the detection resistance current 31Ap. When the detected resistance current 31Ap reaches the target current level 33Ap given from the command signal input terminal 15p, the comparator 13p outputs a reset pulse. The RS flip-flop 12p is latched off by the reset pulse at the ON end timing shown in FIG. The current from the high-potential power supply to the low-potential power supply is referred to as drive current. The drive current path is cut off by the latch-off of the RS flip-flop 12p, and the load current 32Ap of each winding 7p, 8p is gradually increased. A decaying return current flows.

  Although the target current level 33Ap in FIG. 16C is shown as being constant for simplicity, it is possible to give a gradual change to the load current by changing this according to time. As described above, the ON period in the PWM state is the time from when the low-potential power supply side drive switch 5p starts to turn on until the detection resistance current 31Ap reaches the target current level 33Ap. In this way, the PWM pulse width is controlled, and the pulse width has a lower limit pulse width. The cause of the inability to make the lower limit pulse width of the PWM pulse width infinitely small is the delay in response time of the circuit system. Second, spike noise or the like caused by the ON start pulse may induce an erroneous output from the comparator 13p. In order to prevent the possibility that this erroneous output latches off the RS flip-flop 12p, a waiting time is required.

  In FIG. 17, the detection resistance current 31Bp is PWM-controlled with the lower limit pulse width 34p of the PWM pulse width. However, since the current attenuation in the return state of the load current 32B is small with respect to the target current 33Bp that suddenly decreases, the difference between the load current 32Bp and the target current 33Bp increases with time. FIG. 18 shows a case where the target current 33Cp is constant but the value is small. The detection resistance current 31Cp is PWM-controlled with the lower limit pulse width. However, since the lower limit pulse width gives a duty ratio equal to or higher than the target current level, the load current 32Cp still exceeds the target current 33Cp. These occur because the control for suppressing the current is insufficient when the magnitude of the load current at the start of the PWM control exceeds the magnitude of the target current.

  An object of the present invention is to solve the conventional problems described above, and to appropriately perform control that promotes attenuation of the load current even when the magnitude of the load current exceeds the magnitude of the target current. And

  In order to achieve the above object, the load driving device of the present invention repeatedly performs a forward drive state in which a drive current is supplied to an inductive load and a return state in which a return current is received from the inductive load. A driving signal generating unit that generates a driving signal representing a logical state of the forward driving state and the return state, and a driving unit that generates the driving current based on the driving signal. Current detection means for detecting the drive current or possibly further the return current and generating a current detection signal; and target signal generation means for generating a target signal representing a target value of the current flowing through the inductive load; Comparing means for comparing the current detection signal with the target signal and generating a comparison result signal, wherein the drive signal generation means controls the drive signal and is based on the comparison result signal It is characterized by prohibiting the forward drive state.

  The load driving method of the present invention is a method of driving the inductive load by repeatedly performing a forward drive state in which a drive current is supplied to the inductive load and a return state in which the return current is received from the inductive load. A step of generating a drive signal representing the logical state of the forward drive state and the reflux state, a step of generating the drive current based on the drive signal, and further depending on the drive current or in some cases Detecting the return current and generating a current detection signal; generating a target signal representing a target value of the current flowing through the inductive load; comparing the current detection signal and the target signal; Generating a result signal, controlling the drive signal, and prohibiting the forward drive state based on the comparison result signal.

  According to the load driving device and the load driving method of the present invention, even when the load current exceeds the target current or when the PWM driving current having the lower limit pulse width is generated, by performing the control to promote the attenuation of the load current, The load current can accurately follow the target current. Therefore, it is possible to suppress the occurrence of distortion in the current waveform and to drive the load while maintaining a smooth current waveform.

Hereinafter, a load driving device and a load driving method according to embodiments of the present invention will be described with reference to the drawings. In the drawings, elements having substantially the same configuration, operation, and effect are denoted by the same reference numerals. In addition, the numbers described below are all illustrated for specifically explaining the present invention, and the present invention is not limited to the illustrated numbers.
(Embodiment 1)

  FIG. 1 is a block diagram illustrating a configuration of the load driving device according to the first embodiment. The load driving device of the present invention drives the inductive load 85 by repeatedly performing a forward drive state in which a drive current is supplied to the inductive load 85 and a return state in which the return current is received from the inductive load 85. The sum of the drive current and the return current is called a load current.

  Here, the outline of the first embodiment will be described with reference to FIG. Reference numeral 100 denotes a high potential side power source, and 101 denotes a low potential side power source, for example, a ground terminal. The drive signal generation unit 80 generates a drive signal S <b> 16 </ b> A that represents the logical state of the forward drive state and the return state and inputs the drive signal S <b> 16 </ b> A to the drive unit 81. The drive unit 81 generates a drive current based on the drive signal S16A and drives the inductive load 85. The current detector 82 detects the load current flowing through the inductive load 85 and generates a current detection signal S82. The target signal generator 83 generates target signals S17A and 17B that represent target values of the current flowing through the inductive load 85. The comparison unit 84 compares the current detection signal S82 with the target signal S17A, generates a comparison result signal S84, and inputs the comparison result signal S84 to the drive signal generation unit 80. Thus, the drive signal generation unit 80 is controlled so that the current detection signal S82 and the target signal S17A match. When one of the high potential side power source 100 and the low potential side power source 101 is called a first power source, the other is called a second power source. The forward drive state is a state in which a drive current is supplied to the inductive load 85 in the direction of the target signal to drive the inductive load 85.

  Next, the first embodiment will be described in detail. The command signal generator 15 generates a command signal S15 that represents a target value of the load current flowing through the inductive load 85. The polarity separator 17 separates the command signal S15 into an absolute value signal S17A that represents the absolute value of the command signal S15 and a polarity signal S17B that represents the polarity of the command signal S15. The command signal generator 15 and the polarity separator 17 are included in the target signal generator 83. The absolute value signal S17A is simply called the target signal S17A in the first embodiment. The target signal S17A is input to the comparator 13, and the polarity signal S17B is input to the energization control unit 16A. The comparator 13 is included in the comparison unit 84. The current detection unit 82 including the current detection resistor 10 generates a current detection signal S82 representing the voltage across the current detection resistor 10 and inputs the current detection signal S82 to the comparator 13.

  On the other hand, the set signal generation unit 11 generates a set signal S11 representing a periodic pulse signal and inputs the set signal S11 to the drive suppression unit 23A. The drive inhibition unit 23A generates a drive start signal S23A and inputs it to the set terminal of the PWM signal generation unit 12 including the RS flip-flop. The drive start signal S23A operates as a set pulse to the PWM signal generator 12. The drive inhibiting unit 23A determines whether or not to prohibit the passage of the set signal S11 based on the comparison result signal S84.

  When the current detection signal S82 is equal to or less than the target signal S17A, the set signal S11 is passed. In this case, the drive start signal S23A sets the PWM signal generation unit 12, and sets the PWM signal S12 generated by the PWM signal generation unit 12 to a high level. Further, when the current detection signal S82 is equal to or higher than the target signal S17A, the drive suppression unit 23A prohibits the passage of the set signal S11. In this case, the PWM signal generator 12 is not set even when the set signal S11 is set, and the PWM signal S12 remains at a low level. A period in which the current detection signal S82 is equal to or greater than the target signal S17A is referred to as a target excess period, and is also referred to as a first mask period in the sense of prohibiting the passage of the set signal S11. That is, the drive inhibiting unit 23A prohibits the passage of the set signal S11 during the target excess period or the first mask period.

  Further, the comparison result signal S84 is input to the reset terminal of the PWM signal generation unit 12. The comparison result signal S84 operates as a reset pulse for the PWM signal generator 12. When the current detection signal S82 is equal to or higher than the target signal S17A, the PWM signal generation unit 12 is reset and the PWM signal S12 becomes a low level. When the PWM signal S12 is at a low level, it remains at a low level even when the current detection signal S82 becomes equal to or higher than the target signal S17A.

  Normally, the PWM signal generator 12 is set by the drive start signal S23A at the set timing of the set signal S11 and reset by the comparison result signal S84. As a result, the PWM signal generation unit 12 generates a PWM signal S12 having a PWM pulse width from setting to reset. However, when the current detection signal S82 is equal to or higher than the target signal S17A even in the reset state, the set signal S11 is prohibited from passing and the PWM signal generation unit 12 is not set.

  The drive unit 81 includes two half bridges. The half bridge U is configured such that the source of the high potential side drive switch 18S and the drain of the low potential side drive switch 20S are connected by the winding terminal QU. The half bridge V is configured such that the source of the high potential side drive switch 19S and the drain of the low potential side drive switch 21S are connected by the winding terminal QV. The single-phase winding 22 included in the inductive load 85 is inserted between the winding terminal QU and the winding terminal QV. The cathode of the diode 18D is connected to the drain of the drive switch 18S. The cathodes of the diodes 20D, 19D, and 21D are similarly connected to the drains of the drive switches 20S, 19S, and 21S. The anode of the diode 18D is connected to the source of the drive switch 18S, and the anode of the diode 19D is connected to the source of the drive switch 19S. The anodes of the diodes 20D and 21D are connected to the low potential side power source 101. As an example of connecting each anode of the diodes 20D and 21D to the low potential side power source 101, there is a configuration in which each well terminal of the drive switches 20S and 21S is connected to the low potential side power source 101.

  That is, the drive unit 81 includes diodes 18D, 19D, 20D, and 21D connected in parallel to the drive switches 18S, 19S, 20S, and 21S in the reverse conduction direction, and includes the first power supply and the current detection unit 82. The drive switches 20S and 21S are connected to the current detection unit 82, and the diodes 20D and 21D are connected to the second power supply.

  Each drive switch 18S, 19S, 20S, 21S is a circuit that can be switched by a control signal in any type of device such as MOS transistor, bipolar transistor, IGBT (Insulated Gate Bipolar Transistor), etc. Can be used. In the embodiment of the present invention, an n-channel MOS transistor is used. In this case, the control electrode of the drive switch corresponds to the gate, the first main electrode corresponds to the drain, and the second main electrode corresponds to the source. The voltage applied to the control electrode is the gate voltage, the voltage appearing at the first main electrode is the drain voltage, and the voltage appearing at the second main electrode is the source voltage. Needless to say, the high potential side drive switch may be a p-channel type and the low potential side drive switch may be an n channel type.

  Among the drive switches 18S, 19S, 20S, and 21S, the logic level of the drive signal S80 corresponding to the drive switch in the on state is called the operation state level, and the logic level of the drive signal S80 corresponding to the drive switch in the off state. The level is called a non-operational level. In the case of the n-channel MOS transistor used in the embodiment of the present invention, the operating state level is high and the non-operating state level is low. A logic state at one timing such that the logic level takes an operating state level or a non-operating state level is called a logic state.

  Here, the energization control unit 16 </ b> A controls the drive signal S <b> 80 based on the polarity signal S <b> 17 </ b> B and sets the direction of the load current that flows through the single-phase winding 22. For example, assume that a load current flows from the winding terminal QV to the winding terminal QU. In this case, the high potential side drive switch 18S is turned off, the low potential side drive switch 20S is turned on, and the output of the half bridge U is fixed at a low level. Further, the energization control unit 16A controls the drive signal S80 based on the PWM signal S12, and PWM-controls the high potential side drive switch 19S of the half bridge V. That is, the high potential side drive switch 19S is in a PWM drive state that repeats an on state and an off state, respectively, in repetition of the forward drive state and the reflux state. At this time, the low potential side drive switch 21S of the half bridge V is turned off and synchronous rectification is not performed.

  In the forward drive state, the high potential side drive switch 19S is turned on, and the drive current is the high potential side power source 100, the high potential side drive switch 19S, the single phase winding 22, the low potential side drive switch 20S, and the current detection. It flows through the path of the resistor 10 and the low potential side power source 101. This path is called a drive path. In the return state, the high potential side drive switch 19S is turned off, and the return current is supplied from the single phase winding 22, the low potential side drive switch 20S, the current detection resistor 10, the low potential side power supply 101, the diode 21D, and the single phase winding. It flows along the path of the line 22. This route is called the reflux route. Thus, naturally, in the forward drive state, the drive current flows through the current detector 82. Even in the reflux state, the reflux current not only circulates through the drive unit 81 but also flows through the current detection unit 82. With such a configuration, even in the return state, the current detection unit 82 can accurately detect the return current and reflect it as the current detection signal S82.

  The drive inhibition unit 23A receives the set signal S11 from the set signal generation circuit 11 through the reflux state in the PWM operation. At this time, when the current detection signal S82 that accurately reflects the drive current and the return current is equal to or less than the target signal S17A, the drive suppression unit 23A passes the set signal S11. Thereby, the drive part 81 will be in a forward drive state, and the drive current which flows into the single phase winding 22 will increase. Conversely, when the current detection signal S82 is equal to or greater than the target signal S17A, the drive suppression unit 23A prohibits the set signal S11. As a result, the drive unit 81 remains in the return state, and the return current flowing through the single-phase winding 22 further decreases. Thus, in a state where a driving current larger than the target current is flowing through the single-phase winding 22, it is possible to avoid further entering the forward driving state, and the difference between the target current and the actual driving current. Can be prevented from becoming large.

  FIG. 2 is a timing chart for explaining the above situation. FIG. 2A shows the set signal S11, and FIG. 2B shows the drive start signal S23A. In FIG. 2C, reference numeral 35 denotes a period in which the current detection signal S82 is equal to or greater than the target signal S17A, which is the above-described target excess period. In the target excess period 35, as shown in FIG. 2B, the set signal S11 is prohibited and the drive start signal S23A remains at the low level.

  As a result, the PWM signal S12 becomes a high level only during the period of the lower limit pulse width 34 of the PWM pulse width when the current detection signal S82 exceeds the target signal S17A, and then remains at a low level until the target excess period 35 ends. Will remain. That is, the reflux state is continued and it is avoided to enter the forward drive state. The current detection signal S82 converges on the target signal S17A in the shortest time, and enables load current waveform control with less distortion. When the current detection signal S82 becomes equal to or lower than the target signal S17A, the drive inhibition unit 23A resumes the generation of the drive start signal S23A and sets the forward drive state in order to increase the drive current.

In this way, the drive signal generation unit 80 controls the drive signal S80 and prohibits switching from the reflux state to the forward drive state based on the comparison result signal S84. Further, it can be said that the drive signal generation unit 80 maintains the reflux state based on the comparison result signal S84. Furthermore, when the magnitude of the current detection signal S82 exceeds the magnitude of the target signal S17A, the drive signal generation unit 80 prohibits switching from the reflux state to the forward drive state.
(Embodiment 2)

  In the first embodiment, the necessity of driving is determined using the comparison result signal S84. In the second embodiment, the case where the PWM signal S12 is used will be described focusing on differences from the first embodiment. Other configurations, operations, and effects are the same as those in the first embodiment.

  FIG. 3 is a block diagram illustrating the load driving device according to the second embodiment. FIG. 3 shows a configuration in which a mask signal generation unit 24, a reset prohibition unit 25, and a drive suppression unit 30A are added to the first embodiment already described with reference to FIG. The mask signal generator 24 generates a mask signal S24 having a predetermined second mask period starting from the rising timing of the set signal S11. The reset prohibition unit 25 prohibits the comparison result signal S84 from passing for a predetermined second mask period based on the mask signal S24. The drive end signal S25 of the masked reset prohibition unit 25 is input to the reset terminal of the PWM signal generation unit 12. The drive end signal S25 operates as a reset pulse for the PWM signal generator 12.

  Noise caused by the set signal S11 may cause an erroneous pulse output of the comparator 13 and reset the PWM signal generator 12. The mask signal generation unit 24 and the reset prohibition unit 25 prevent the PWM signal generator 12 from being inadvertently reset by prohibiting the passage of the comparison result signal S84 for a predetermined second mask period. Since the lower limit pulse width cannot be reduced to infinity by the second mask period, the actual load current deviates from the target current.

  The drive inhibition unit 30A reflects the history of the PWM pulse width in the PWM signal S12, and controls whether or not the set signal S11 is prohibited from being input to the set terminal of the PWM signal generation unit 12. That is, it is estimated from the detection history of the PWM pulse width corresponding to the lower limit pulse width that the drive current exceeds the target current, and the subsequent PWM drive is thinned out.

  FIG. 4 is a block diagram showing an internal configuration of the drive inhibiting unit 30A. The reference signal generator 26 generates a reference signal S26 having a falling edge delayed by a predetermined period from the end edge of the second mask period of the mask signal S24. Although this predetermined period can be set arbitrarily, it is normally set within a short period of time equal to or less than the lower limit pulse width of the PWM signal S12. The latch unit 28 compares the falling edge of the PWM signal S12 with the falling edge of the reference signal S26 and generates a latch output signal S28. The mask signal generation unit 29 generates a mask signal S29 representing a predetermined first mask period based on the latch output signal S28 of the latch unit 28. The set prohibition unit 27 prohibits the passage of the set signal S11 based on the mask signal S29 for a predetermined first mask period. The drive start signal S30A of the masked set prohibition unit 27 is input to the set terminal of the PWM signal generation unit 12. The drive start signal S30A operates as a set pulse to the PWM signal generation unit 12.

  The falling edge of the PWM signal S12 is always after the second mask period by way of the reset prohibition unit 25. When the falling edge of the reference signal S26 is later than the falling edge of the PWM signal S12, it indicates that PWM control is performed with a substantially lower limit pulse width in the forward drive state. In this case, even in the next forward drive state, the load current may be driven with the lower limit pulse width even though the load current exceeds the target current, and the load current may further exceed the target current. Based on the latch output signal S28, by setting a predetermined first mask period, control for prohibiting the forward drive state by a predetermined number of times is performed.

  In the above description, the latch unit 28 compares the falling edge of the PWM signal S12 with the falling edge of the reference signal S26. However, the driving of the output of the reset prohibiting unit 25 and the falling edge of the reference signal S26 is completed. The rising edge of the signal S25 may be compared with time.

  FIG. 5 is a timing chart for explaining the above control. 5A shows a rising edge of the set signal S11 output from the set signal generation unit 11 in FIG. 3, and FIG. 5B shows a falling edge of the reference signal S26 output from the reference signal generation unit 26. It is an edge. FIGS. 5C and 5D show a reset pulse and a set pulse input to the PWM signal generation unit 12. The signal waveforms in FIG. 5 (e) are the same as those described with the same reference numerals in FIG. FIG. 6F is an example of a timing diagram of the latch output signal S28.

  Whether the next set pulse is to be applied or not is determined by whether the latch output signal S28 is high level or low level before the next set pulse is applied. The PWM signal S12 started to be driven by the set pulse 39A is ended by the reset pulse 38A. The PWM pulse width is substantially the lower limit pulse width, and the falling edge 38A of the PWM signal S12 is earlier in time than the falling edge 37A of the reference signal S26. In response to this, the latch output signal S28 is at a low level. For this reason, the mask signal generation unit 29 prohibits application of the next set pulse.

  The PWM signal S12 is resumed after being prohibited once, starts driving with the set pulse 39C, and ends with the reset pulse 38C. The falling edge 38C of the PWM signal S12 is later in time than the falling edge 37C of the reference signal S26. In response to this, the latch output signal S28 is at a high level. For this reason, the mask signal generation unit 29 does not prohibit the application of the next set pulse 39D. The PWM signal S12 starts to be driven by the set pulse 39D, and is ended by the reset pulse 38D. The PWM pulse width is substantially the lower limit pulse width, and the falling edge 38D of the PWM signal S12 is earlier in time than the falling edge 37D of the reference signal S26. In response to this, the latch output signal S28 is at a low level. For this reason, the mask signal generation unit 29 prohibits application of the next set pulse.

  As described above, in the configuration of the second embodiment, the PWM pulse width of the PWM signal S12 is set based on the comparison result signal S84, but cannot be narrowed below the lower limit pulse width to prevent noise malfunction. The drive inhibiting unit 30A sets whether to set the forward drive state based on whether the PWM pulse width of the PWM signal S12 is in the vicinity of the lower limit pulse width. Thereby, the generation of the PWM signal S12 having the lower limit pulse width is suppressed, and the current detection signal S82 is urged to converge to the target signal S17A. Therefore, it is possible to control the drive current waveform with less distortion.

  Thus, the drive signal generation unit 80A controls the drive signal S80A and prohibits switching from the reflux state to the forward drive state based on the comparison result signal S84. Further, it can be said that the drive signal generation unit 80A maintains the reflux state based on the comparison result signal S84. Furthermore, when the period of the forward drive state becomes shorter than the predetermined period, the drive signal generation unit 80A prohibits switching from the reflux state to the forward drive state.

  Here, the reason why the PWM signal S12 becomes close to the lower limit pulse width is that the current detection signal S82 becomes equal to or higher than the target signal S17A immediately after the set pulse is applied, the reset prohibition unit 25 outputs the drive end signal S25, and the PWM signal generation unit 12 is reset. That is, as a result of the current detection signal S82 becoming equal to or greater than the target signal S17A, the PWM pulse width of the PWM signal S12 is narrowed, and the drive inhibiting unit 30A temporarily stops the forward drive state.

In the configuration of the second embodiment, after the set pulse is prohibited once, it is set that the next set pulse is not prohibited. However, in order to suppress the divergence between the load current and the target current, there is a case where it is not sufficient to always prohibit one time. In this case, in the mask signal generation unit 29, a history storage unit that stores a history when the PWM pulse width is the lower limit pulse width, and a prohibition for setting the number of set pulse inhibitions based on the stored contents of the history storage unit A number setting unit may be provided. Further, in the second embodiment, since the load current suppression control is performed using the history of the forward drive state of the lower limit pulse width, the present invention is not limited to the return via the diode but can be applied to the return using the synchronous rectification.
(Embodiment 3)

  In the third embodiment, the case where the drive current is detected without using the current detection resistor 10 will be described with a focus on differences from the first embodiment. Other configurations, operations, and effects are the same as those in the first embodiment.

  The configuration will be described with reference to FIG. The polarity separation unit 17 generates an absolute value signal S17A and a polarity signal S17B and inputs them to the command transmission unit. The command transmission unit 42 selects either the first comparison switch 43A or the second comparison switch 43B based on the polarity of the polarity signal S17B, and sets the selected comparison switch based on the absolute value signal S17A. Then, a current corresponding to the target current or the target signal is supplied. The current flowing through the first comparison switch 43A corresponds to the target signal S83AA. The current flowing through the second comparison switch 43B corresponds to the target signal S83AB. The gates of the first comparison switch 43A and the second comparison switch 43B are connected to the high potential side drive switches 18S and 19S, respectively, and the drains of the first comparison switch 43A and the second comparison switch 43B are the high potential. Connected to the side power supply 100.

  The command signal generator 15, the polarity separator 17, the command transmitter 42, the first comparison switch 43A, and the second comparison switch 43B are included in the target signal generator 83A. Note that any or all of the command transmission unit 42, the first comparison switch 43A, and the second comparison switch 43B may be included in the drive unit 81.

  The first comparison switch 43A and the second comparison switch 43B have the same structure as the high-potential side drive switches 18S and 19S, and have different size ratios. Usually this size ratio is well below 1. In consideration of power consumption, it is set as small as possible so that the error does not increase. The target current based on the absolute value signal S17A is multiplied by this size ratio, and flows to the first comparison switch 43A and the second comparison switch 43B.

  The current detector 82A detects the source potential of the high potential side drive switch 18S, generates a current detection signal S82AA, detects the source potential of the high potential side drive switch 19S, and generates a current detection signal S82AB. The comparator 13A compares the current detection signal S82AA with the target signal S83AA, and generates a comparison result signal S13A. The comparator 13B compares the current detection signal S82AB with the target signal S83AB, and generates a comparison result signal S13B. The selection unit 41 selects either the comparison result signal S13A or the comparison result signal S13B based on the polarity signal S17B, and generates a comparison result signal S84A. The comparison result signal S84A is input to the drive signal generation unit 80 in the same manner as the comparison result signal S84 in the first embodiment. The comparators 13A and 13B and the selection unit 41 are included in the comparison unit 84A.

  The energization control unit 16A sets the logic state of the drive signal S80 in the direction of the load current flowing through the single-phase winding 22 based on the polarity signal S17B. For example, assume that a load current flows from the winding terminal QV to the winding terminal QU. In this case, the high potential side drive switch 18S is turned off, the low potential side drive switch 20S is turned on, and the high potential side drive switch 19S is PWM-controlled. The low-potential side drive switch 21S may be synchronously rectified in synchronization with the high-potential side drive switch 19S, or may be turned off as in the first embodiment.

  In the forward drive state, the high potential side drive switch 19S is turned on, and the drive current is the high potential side power supply 100, the high potential side drive switch 19S, the single phase winding 22, the low potential side drive switch 20S, the low potential. It flows through the drive path of the side power supply 101. In the return state, the high potential side drive switch 19S is turned off, and the return current is returned to the single phase winding 22, the low potential side drive switch 20S, the low potential side power supply 101, the diode 21D, and the single phase winding 22. Flowing the route. In the case of synchronous rectification, the return current flows through the return path of the single phase winding 22, the low potential side drive switch 20 </ b> S, the low potential side power supply 101, the low potential side drive switch 21 </ b> S, and the single phase winding 22.

  As described above, the current detection unit 82A includes the common connection point QU between the drive switches 18S and 20S and the single-phase winding 22 and the common connection point QV between the drive switches 19S and 21S and the single-phase winding 22. The drive current and the return current can be accurately detected and reflected as the current detection signal S82AA regardless of the presence or absence of the synchronous rectification in both the forward drive state and the return state.

  The command transmission unit 42 selects the first comparison switch 43A based on the polarity signal S17B, and causes a current corresponding to the target signal S83AA to flow through the first comparison switch 43A. The selection unit 41 selects the comparison result signal S13A based on the polarity signal S17B, and generates the comparison result signal S84A.

  In this way, when the current detection signal S82AA is equal to or higher than the target signal S83AA, the passage of the set signal S11 is prohibited, and the drive unit 81 does not enter the forward drive state and continues in the reflux state. Thereby, the generation of the PWM signal S12 having the lower limit pulse width is suppressed, and the load current is urged to converge to the target current. Accordingly, it is possible to control the waveform of the drive current with less distortion.

The same can be said for the case where the load current is opposite to the above. Further, the same effect can be obtained by using one comparator instead of the two comparators 13A and 13B and selecting the input of the comparator according to the polarity signal S17B. Further, in the third embodiment, since each comparison switch 43A, 43B is used without using the current detection resistor, not only the return via the diode but also the return by synchronous rectification can be performed.
(Embodiment 4)

  In the fourth embodiment, another configuration example in which the drive current is detected without using the current detection resistor 10 will be described focusing on differences from the second and third embodiments. Other configurations, operations, and effects are the same as those in the second and third embodiments.

  This will be described with reference to FIG. The fourth embodiment corresponds to the configuration in which the drive signal generation unit 80 in the third embodiment is replaced with the drive signal generation unit 80A in the second embodiment. That is, the fourth embodiment includes the drive signal generation unit 80A in the second embodiment, the drive unit 81, the current detection unit 82A, the target signal generation unit 83A, and the comparison unit 84A in the third embodiment.

In such a configuration, the operation is as described in the second and third embodiments. In the fourth embodiment, the generation of the PWM signal S12 having the lower limit pulse width is suppressed, and the current detection signals S82AA and S82AB are urged to converge to the target signals S83AA and S83AB, respectively. Therefore, it is possible to control the waveform of the load current with less distortion. Further, the comparison switches 43A and 43B are used without using the current detection resistor. Thereby, in addition to the effects of the second embodiment, not only the reflux via the diode but also the reflux using the synchronous rectification can be performed.
(Embodiment 5)

  In the fifth embodiment, a two-phase load driving device will be described focusing on differences from the first to fourth embodiments. Other configurations, operations, and effects are the same as those in the first to fourth embodiments.

  FIG. 8 shows a two-phase load driving device. In FIG. 8, the load driving unit 44 </ b> X and the load driving unit 44 </ b> Y are the same as the configurations in FIGS. 1, 3, 6, and 7 except for the inductive load 85 and the command signal generation unit 15. The operation is also as described in the first to fourth embodiments. The command signal generator 46 generates a command signal S46 that represents a target value of the load current that drives the two-phase type inductive load 85A. The two-phase command signal generation unit 47 generates two-phase command signals S15X and S15Y representing the target values of the respective load currents in the phase windings 22X and 22Y based on the command signal S46. Normally, the two-phase command signals S15X and S15Y are shifted by 90 degrees from each other. The load drive units 44X and 44Y supply drive currents to the phase windings 22X and 22Y based on the two-phase command signals S15X and S15Y, respectively.

By configuring in this way, it is possible to provide a two-phase load driving device that has the same effect as in the first to fourth embodiments and drives the two-phase inductive load 85A. According to the fifth embodiment, it is possible to configure a two-phase stepping motor drive device that suppresses vibration and noise by realizing a smooth current waveform. Note that the set signal generation unit 11 may be configured so that both load drive units use one set signal generation unit without having the load drive units 44X and 44Y independently.
(Embodiment 6)

  In the sixth embodiment, when the load current exceeds the target current, a configuration in which attenuation control is performed up to the target current value by energizing in the reverse direction will be described with a focus on differences from the first embodiment. Other configurations, operations, and effects are the same as those in the first embodiment.

  The configuration of the sixth embodiment will be described with reference to FIG. 9 corresponds to the drive inhibition unit 23A, the polarity separation unit 17, and the energization control unit 16A in FIG. 1 corresponding to the drive inhibition unit 23B, the polarity separation unit 17B corresponding to the drive inhibition unit 23B, and the drive inhibition unit 23B. This corresponds to the configuration replaced with the energization control unit 16B.

  FIG. 10 is a configuration example of the current detection unit 82B in FIG. The current detection unit 82B includes a current detection resistor 10 and a preamplifier 55. The high potential side terminal and the low potential side terminal of the current detection resistor 10 are connected to the inverting input terminal 52 and the non-inverting input terminal 53 of the preamplifier 55, respectively. By connecting the reference power supply 54 to the non-inverting input terminal 53, the preamplifier 55 converts the current flowing through the current detection resistor 10 into a voltage based on the reference potential 54 and outputs it as a current detection signal S82B. . The current detection signal S82B and the target signal S17BA are compared in the comparator 13. As described above, the current detection signal S82B outputs the difference between the voltage at the inverting input terminal 52 and the voltage at the non-inverting input terminal 53 with reference to the reference potential 54.

  Next, a control operation when reverse direction energization is performed will be described. In FIG. 9, when the load current exceeds the target current in the reflux state, the drive inhibiting unit 23B generates an energization inversion signal S23BA instructing inversion of the energization direction and sends it to the energization control unit 16B. Further, the drive inhibiting unit 23B sends a drive start signal S23BB indicating that the reverse drive state is started to the PWM signal generating unit 12. Further, the drive inhibiting unit 23B instructs the polarity separating unit 17B via the output S23BC to set the target current whose polarity is reversed in the direction opposite to the normal time with the reference potential 54 as a reference.

  Thereby, reverse direction energization is performed on the winding 22. The reverse energization is, for example, when each drive switch 18S, 21S is turned off when a drive current is passed from the high potential side power supply 100 to the low potential side power supply 101 via each drive switch 18S, 21S. This is to turn on the switches 19S and 20S. The reverse case is also called reverse energization. A driving state in reverse energization is referred to as a reverse driving state. Thus, in the driving state, the forward driving state in which the driving current is supplied in the direction of the target current to the inductive load 85, and the forward direction is the opposite direction, that is, the target current direction is opposite. There is a reverse drive state in which a drive current is supplied.

  A change in current at this time will be described with reference to FIG. The vertical axis represents current, and the horizontal axis represents time. At the time 58, the load current 56 detected as the current detection signal S82B is I1, which is in a state exceeding the target current value IA. In the reverse drive state, the load current 56 eventually approaches a negative value (−VM / R) obtained by dividing the power supply voltage VM by the resistance component R of the current path.

  Here, when the reverse drive state is started at time 58, the reverse drive state is stopped at time 59 when the load current 56 becomes equal to the target current value IA. That is, the load current 56 is attenuated to the target current IA. Thereafter, the drive signal generator 80B returns to the forward drive state before entering the reverse drive state, and is controlled based on the target signal S17BA and the polarity signal S17BB generated by the target signal generator 83B. Whether the drive signal generation unit 80B controls the drive signal S80B and, based on the comparison result signal S84, permits the forward drive state or prohibits the forward drive state and permits the reverse drive state. Is determined.

In the above description, in the reverse drive state, the target signal S17BA output from the polarity separator 17B to the comparator 13 is given a value corresponding to the target current with the polarity reversed. However, it is also possible to perform current attenuation control by reverse energization by inverting the current detection signal S82B of the current detection unit 82B and the comparison result signal S84 of the comparison unit 84. In FIG. 9, the set signal S11 output from the set signal generation unit 11 is input to the PWM signal generation unit 12 via the drive suppression unit 23B. However, the PWM signal generation unit 12 does not pass through the drive suppression unit 23B. May be entered. Further, in FIG. 6, the drive suppression unit 23A, the polarity separation unit 17, and the energization control unit 16A are replaced with a drive suppression unit 23B, a polarity separation unit 17B corresponding to the drive suppression unit 23B, and an energization control unit corresponding to the drive suppression unit 23B. The same effect can be obtained even if it is replaced with 16B.
(Embodiment 7)

  Similarly to the sixth embodiment, the seventh embodiment differs from the second and sixth embodiments in the configuration in which attenuation control is performed to the target current value by energizing in the reverse direction when the load current exceeds the target current. The explanation will focus on the points. Other configurations, operations, and effects are the same as those of the second and sixth embodiments.

  The configuration of the seventh embodiment will be described with reference to FIG. The configuration of FIG. 12 corresponds to the drive suppression unit 30A, the polarity separation unit 17, and the energization control unit 16A in FIG. 3 corresponding to the drive suppression unit 30B, the polarity separation unit 17B corresponding to the drive suppression unit 30B, and the drive suppression unit 30B. This corresponds to the configuration replaced with the energization control unit 16B. The current detection unit 82B is the same as the configuration in FIG.

  An example of the configuration of the drive inhibiting unit 30B is shown in FIG. In FIG. 13, the reference signal generation unit 26, the set prohibition unit 27, and the latch unit 28 have the same configuration as the blocks with the same reference numerals in FIG. The mask signal generation unit 29B has a configuration in which a signal transmission function to the energization control unit 16B and the polarity separation unit 17B is added to the mask signal generation unit 29 in FIG. As in the second embodiment, the latch unit 28 compares the falling edge of the PWM signal S12 with the falling edge of the reference signal S26 to generate a latch output signal S28.

  Based on the latch output signal S28 of the latch unit 28, the mask signal generation unit 29B generates a mask signal S29B representing a predetermined first mask period. When the falling edge of the reference signal S26 is later than the falling edge of the PWM signal S12, the mask signal generation unit 29B generates an energization inversion signal S30BA instructing inversion of the energization direction and sends it to the energization control unit 16B. Further, the mask signal generation unit 29 </ b> B sends a drive start signal S <b> 30 BC indicating that the forward drive state is started to the PWM signal generation unit 12 via the set prohibition unit 27. That is, in the mask signal S29B representing a predetermined first mask period, the first mask period is set to zero. Further, the mask signal generation unit 29B instructs the polarity separation unit 17B via the output S30BB to set the target current whose polarity is reversed in the direction opposite to the forward drive state with the reference potential 54 as a reference.

  Thereby, reverse direction energization is performed on the winding 22. That is, for example, when a drive current is passed from the high potential side power supply 100 to the low potential side power supply 101 via the drive switches 18S and 21S, the drive switches 18S and 21S are turned off and the drive switches 19S and 20S are turned off. Turn on. The change in current at this time is the same as that in FIG. That is, in the reverse driving state, the load current 56 is controlled to be attenuated to the target current IA. Thereafter, the drive signal generator 80C returns to the forward energization state before entering the reverse drive state, and is controlled based on the target signal S17BA and the polarity signal S17BB generated by the target signal generator 83B. As described above, the drive signal generation unit 80C controls the drive signal S80C and, based on the comparison result signal S84, permits the forward drive state or prohibits the forward drive state and reverse drive state. It is decided whether or not to allow.

  In the above description, in the reverse drive state, the target signal S17BA output from the polarity separator 17B to the comparator 13 is given a value corresponding to the target current with the polarity reversed. However, it is also possible to perform current attenuation control by reverse energization by inverting the current detection signal S82B of the current detection unit 82B and the comparison result signal S84 of the comparison unit 84. In FIG. 13, the set signal S11 output from the set signal generation unit 11 is input to the PWM signal generation unit 12 via the set prohibition unit 27. However, the PWM signal generation unit 12 does not pass through the set prohibition unit 27. May be entered. Further, in FIG. 7, the drive suppression unit 30A, the polarity separation unit 17, and the energization control unit 16A are replaced with a drive suppression unit 30B, a polarity separation unit 17B corresponding to the drive suppression unit 30B, and an energization control unit corresponding to the drive suppression unit 30B. The same effect can be obtained even if it is replaced with 16B.

Further, the latch unit 28 compares the falling edge of the PWM signal S12 with the falling edge of the reference signal S26, but the falling edge of the reference signal S26 and the drive end signal S25 output from the reset prohibition unit 25 are compared. You may compare the time with the rising edge.
(Embodiment 8)

  The configuration of the eighth embodiment will be described with a focus on differences from the above-described embodiment in increasing the attenuation of the return current. Other configurations, operations, and effects are the same as those of the above-described embodiment.

  The degree of attenuation of the return current in the return state varies depending on the device control state of the return path. In normal PWM control, synchronous rectification driving is performed in order to reduce power loss due to return current. However, when the load current exceeds the target current, the current decay in the return state is insufficient in the synchronous rectification drive. Therefore, in the eighth embodiment, when the load current exceeds the target current in the return state, the drive switch that performs the synchronous rectification operation is turned off, and the return current flows through the diode connected in parallel to the drive switch. . Thereby, the attenuation rate of the load current in the return state becomes larger than that in the case of synchronous rectification.

  This will be described in detail with reference to FIG. For example, when the drive switch 19S is in the PWM drive state, the drive switch 21S is in the off state. In this case, in the forward drive state, the drive switch 19S is turned on, and the drive current is driven by the high potential side power source 100, the drive switch 19S, the single phase winding 22, the drive switch 20S, and the low potential side power source 101. Flowing the route. In the return state, the drive switch 19S is turned off, and the return current of the eighth embodiment flows through the return path of the single-phase winding 22, the low-potential side drive switch 20S, the diode 21D, and the single-phase winding 22. .

  In the case of FIG. 1 in the first embodiment and FIG. 9 in the sixth embodiment, the load current detection in the return state is originally not the synchronous rectification but the return through the diode, and the eighth embodiment is applied. Yes. 3 in the second embodiment, the drive inhibition unit 23A in FIG. 6 in the third embodiment, the drive inhibition unit 30A in FIG. 7 in the fourth embodiment, and the drive inhibition unit in FIG. 12 in the seventh embodiment. If the unit 30B is configured to generate a command to turn off the drive switch that was originally synchronously rectified, and supply the command to each of the energization control units 16A and 16B, in these embodiments also, the eighth embodiment Applied.

As described above, the recirculation by the diode has a larger current attenuation than the recirculation by the synchronous rectification, so that it is possible to suppress the load current from greatly exceeding the target current. In the reflux state before the set pulse is applied, the determination that the load current exceeds the target current is substantially the same as the lower limit pulse width as a result of the load current exceeding the target current as described in the second embodiment. Obviously, the determination may be made that the corresponding PWM pulse has been output.
(Embodiment 9)

  In the configuration of the ninth embodiment, another embodiment in which the attenuation of the return current is increased will be described focusing on differences from the eighth embodiment. Other configurations, operations, and effects are the same as those in the eighth embodiment.

  In the ninth embodiment, when the load current exceeds the target current in the return state, the drive switch that performs the synchronous rectification operation is turned off, and the return current is simply passed through the diode connected in parallel to the drive switch. Instead, all the drive switches forming the reflux path are turned off. That is, in the half bridge that performs the PWM operation, the drive switch that is not the drive switch that is performing the PWM control is turned off, and the return current flows through the diodes connected in parallel. Further, in the forward drive state and the reflux state, the drive switches included in other half bridges that form the same load current path together with the half bridge are also turned off.

  This will be described in detail with reference to FIG. For example, when the drive switch 19S is in the PWM drive state, the other drive switches 18S, 20S, and 21S are all in the off state in the reflux state. In this case, in the forward drive state, the drive switch 19S is turned on, and the drive current is driven by the high potential side power source 100, the drive switch 19S, the single phase winding 22, the drive switch 20S, and the low potential side power source 101. Flowing the route. In the return state, all the drive switches are turned off, and the return current of the ninth embodiment includes the single-phase winding 22, the diode 18D, the high-potential side power supply 100, the low-potential side power supply 101, the diode 21D, the single-phase winding. It flows through the reflux path of line 22. In other words, current flows back from the low potential side power source 101 to the high potential side power source 100.

  With respect to the block configuration, in the drive inhibition unit 23A in FIGS. 1 and 6, the drive inhibition unit 30A in FIGS. 3 and 7, the drive inhibition unit 23B in FIG. 9, and the drive inhibition unit 30B in FIG. What is necessary is just to comprise so that the instruction | command which makes all the drive switches of the load current path | route which was flowing the return current into an OFF state generate | occur | produced, and it gives to each electricity supply control part 16A, 16B.

  When all the drive switches are turned off, the current flows back from the low potential power source 101 to the high potential power source 100 or in the opposite direction. In this case, the return current is more attenuated than the return by the synchronous rectification and the return by the diode described in the eighth embodiment. Thereby, it can suppress that load current greatly exceeds target current.

Note that the determination that the load current during reflux before application exceeds the target current substantially corresponds to the lower limit pulse width as a result of the load current exceeding the target current as described in the second embodiment. You may replace with the judgment that the PWM pulse was output. Further, when the return current is not sufficiently attenuated even by the recirculation by the diode described in the eighth embodiment, the recirculation from the low potential side power source to the high potential side power source described in the ninth embodiment is performed. May be.
(Embodiment 10)

  In the tenth embodiment, the configurations described in the first, third, eighth, and ninth embodiments are all added to 23B of the sixth embodiment, and other configurations, operations, and effects are the same as those in the respective embodiments. The same as 1, 3, 6, 8, and 9.

  In the tenth embodiment, the drive signal generator 80 combines the five control states in response to the fact that the load current exceeds the target current in the return state. The first control state is a control state in which the passage of the set signal is prohibited as in the first and third embodiments. The second control state is a control state for switching to the reverse drive state as in the sixth embodiment. As in the eighth embodiment, the third control state is a control state in which the other drive switch of the half bridge including the drive switch in the PWM drive state is set to the non-operation level. The fourth control state is a control state in which all the drive switches other than the drive switch in the PWM drive state are set to the non-operation level as in the ninth embodiment. The fifth control state is a control state in which the other drive switch is set to the operation level as in the third embodiment.

Normally, one of the first control state and the second control state is selected. In addition, one of the third control state, the fourth control state, and the fifth control state is selected. The priority in each combination may be configured to be sequentially selected by returning the effectiveness of the effect. According to the tenth embodiment, appropriate attenuation control is performed according to the control state.
(Embodiment 11)

  In the eleventh embodiment, all the configurations described in the second, fourth, eighth, and ninth embodiments are added to 30B of the seventh embodiment. The other configurations, operations, and effects are the same as those of the seventh embodiment. The same as 2, 4, 7, 8, and 9.

  In the eleventh embodiment, the drive signal generation unit 80 combines the five control states in response to the fact that the load current exceeds the target current in the reflux state. The first control state is a control state in which the passage of the set signal is prohibited as in the second and fourth embodiments. The second control state is a control state for switching to the reverse drive state as in the seventh embodiment. As in the eighth embodiment, the third control state is a control state in which the other drive switch of the half bridge including the drive switch in the PWM drive state is set to the non-operation level. The fourth control state is a control state in which all the drive switches other than the drive switch in the PWM drive state are set to the non-operation level as in the ninth embodiment. The fifth control state is a control state in which the other drive switch is set to the operation level as in the fourth embodiment.

Normally, one of the first control state and the second control state is selected. In addition, one of the third control state, the fourth control state, and the fifth control state is selected. The priority order in the combination may be a configuration in which effectiveness of the effect is fed back and sequentially selected. According to the eleventh embodiment, appropriate attenuation control is performed in accordance with the control state.
(Embodiment 12)

  In the above-described embodiment, the case of two-phase energization has been described. In the twelfth embodiment, the case of three-phase energization will be described with a focus on differences from the above-described embodiments. Other configurations, operations, and effects are the same as those of the above-described embodiment.

  In Embodiment 12, the configurations of Embodiments 1 to 4 and 6 to 11 are applied to a three-phase load driving device. Even three-phase driving is a combination of single-phase driving if time is divided. For this reason, if the control described in Embodiments 1 to 4 and 6 to 11 is applied according to the state of the energization control unit, current suppression control can be performed.

  The configuration and operation of the twelfth embodiment will be described with reference to FIG. FIG. 14 shows a sensorless three-phase load driving device for driving the three-phase driving motor 85T. Each of the winding terminals QU, QV, QW and the three-phase windings 7, 8, and 9 Y-connected between the center points CN have two independent current paths, that is, a first path and a second path. The current of each of the two current paths and the total current thereof are controlled to predetermined values in a time-sharing manner according to the energization control state, and a smooth three-phase load current waveform is obtained.

  The drive unit 81T includes high-potential side drive switches 1, 2, and 3 and low-potential side drive switches 4, 5, and 6. The source of the high potential side drive switch 1 is connected to each drain of the low potential side drive switch 4 by the winding terminal QU. The other high-potential side drive switches 2 and 3 and the low-potential side drive switches 5 and 6 are similarly connected at the winding terminals QV and QW, respectively. The rotor position signal generator 62 detects a counter electromotive voltage from the terminal voltages SU, SV, SW generated in the windings 7, 8, 9 and the center point voltage SCN generated at the center point CN, and each rotor position signal. S62A and S62B are generated. The rotor position signals S62A and S62B are output to the energization control unit 16T and the target signal generation unit 83T, respectively.

  The energization control unit 16T includes a logic unit 66 that performs energization control signal processing and a level shift unit 67. Of these, the level shifter 67 can be omitted depending on conditions. The target signal generator 83T generates a torque command signal that specifies the torque of the three-phase drive motor 85T. The target signal generation unit 83T has three types of target signal S83TD for the first path, target signal S83TE for the second path, and total target signal S83TF for the first path and the second path based on the torque command signal. A target signal is generated. The current detection unit 82T amplifies the load current flowing through the current detection resistor 10 by the preamplifier 55, and generates a current detection signal S82T. In the comparators 13D, 13E, and 13F included in the comparison unit 84T, the target signals S83TD, S83TE, and S83TF are input, and the current detection signal S82T is input in common as a comparison signal.

  Based on the control signal S16T from the energization control unit 16T, the mask unit 68 determines whether the current detection signal S82T is based on the current of the first path, the current of the second path, or the total current of both. . According to this determination result, the comparison result signals S13D, S13E, and S13F of the three comparators 13D, 13E, and 13F are appropriately used in time division, thereby corresponding to the control of the first path and the control of the second path. Two comparison result signals S68A and S68B are obtained. Each comparison result signal S68A, S68B gives a reset pulse to the PWM signal generator 12T having a latching action.

  Next, the drive suppression unit 30T includes a reference signal generation unit, a latch unit, a mask signal generation unit, and a set prohibition unit. The reference signal generation unit receives the set signal S11T from the set signal generation unit 11T and generates a reference signal. The latch unit compares the timings of the reference signal and the PWM signal S12T of the PWM signal generation unit 12T for each of the first path and the second path. The mask signal generation unit generates a mask signal representing a predetermined first mask period based on the comparison result. The set prohibition unit prohibits passage of the set signal S11T based on the mask signal for a predetermined first mask period. The drive start signal S30T of the masked set prohibition unit is input to the set terminal of the PWM signal generation unit 12T. The drive start signal S30T operates as a set pulse to the PWM signal generator 12T. The configuration of the drive inhibiting unit 30T is as described above, but basically, the configuration of FIG. 4 in the second embodiment is prepared for two of the first route and the second route. .

  The drive inhibiting unit 30T determines whether or not the lower limit pulse width is output from the comparison result of the latch unit. As a result of the load current exceeding the target current, a lower limit pulse width is generated, and it is determined that there is a need to suppress the load current. When there is a need to suppress the load current, the drive suppression unit 30T prohibits the passage of the set signal S11T for the corresponding current path. As a result, the forward drive state is stopped, and the current in the current path exceeding the target current is urged to attenuate to the target current.

  Usually, the motor drive device realizes efficient drive by supplying a drive current corresponding to the rotor position to the stator winding while detecting the rotor position. In order to detect the rotor position, a magnetic sensor or an induction sensor is used. The sensorless motor is a motor that does not use such a position sensor, and has advantages in terms of cost reduction and longer life. In the drive of the sensorless motor, the rotor position is detected from the zero cross timing of the counter electromotive voltage appearing at one of the winding terminals, and is used for controlling the energization switching timing.

  Here, since all the embodiments in the present invention directly control the load current, there is no delay in the load current suppression control. Embodiments other than the two-phase load driving device of the fifth embodiment can be applied to the three-phase load driving device of the twelfth embodiment, and suppression control without delay is possible. That is, since the three-phase load driving device of the twelfth embodiment can cause the load current to follow the target current with high accuracy, the load current of any phase can be made zero at the timing when the energization should be switched. Easy to do. Thus, the present invention is most effective when applied to a sensorless motor among the three-phase load driving devices.

  Note that the present invention is applicable not only to the configuration of the sensorless driving device of FIG. 14 but also to a three-phase load driving device that performs rotation control using a position sensor such as a Hall element. By the current attenuation control similar to that of the twelfth embodiment, the degree of coincidence of the load current can be improved with respect to a target current that decreases rapidly or a low target current.

  The explanations developed in the embodiments are all examples embodying the present invention, and the present invention is not limited to these examples.

  The present invention can be used for a load driving device and a load driving method.

The block diagram which shows the load drive device in Embodiment 1 of this invention. The timing diagram explaining the current attenuation | damping control in Embodiment 1 of this invention. The block diagram which shows the load drive device in Embodiment 2 of this invention. The block diagram which shows the internal structural example of the drive suppression part in Embodiment 2 of this invention. The timing diagram explaining the current attenuation | damping control in Embodiment 2 of this invention. The block diagram which shows the load drive device in Embodiment 3 of this invention. The block diagram which shows the load drive device in Embodiment 4 of this invention. The block diagram which shows the load drive device in Embodiment 5 of this invention. The block diagram which shows the load drive device in Embodiment 6 of this invention. The block diagram which shows the internal structure of the comparator in Embodiment 6 of this invention. Explanatory drawing of the current attenuation | damping control in Embodiment 6 of this invention. The block diagram which shows the load drive device in Embodiment 7 of this invention. The block diagram which shows the structural example of the drive suppression part in Embodiment 7 of this invention. The block diagram which shows the three-phase load drive device in Embodiment 12 of this invention. The block diagram which shows the basic circuit structure of the load drive device in a prior art example. The timing diagram of the current control in a prior art example. The timing diagram of the load current with respect to the target current which decreases rapidly in the conventional example. The timing diagram of the load current with respect to the low target current in a prior art example.

Explanation of symbols

1, 2, 3, 18S, 19S High potential side switch 4, 5, 6, 20S, 21S Low potential side switch 7, 8, 9 Three-phase motor winding 10 Current detection resistor 11, 11T Set signal generator 12, 12T PWM signal generation unit 13, 13A, 13B, 13D, 13E, 13F Comparator 15 Command signal generation unit 16, 16A, 16B, 16T Energization control unit 17, 17B Polarity separation unit 18D, 19D, 20D, 21D Diode 22 Single phase winding Line 23A Drive inhibition unit 24 Mask signal generation unit 25 Reset prohibition unit 26 Reference signal generation unit 27 Set prohibition unit 28 Latch unit 29, 29B Mask signal generation unit 30A, 30B, 30T Drive inhibition unit 41 Selection unit 42 Command transmission unit 43A, 43B Comparison switch 44X, 44Y Load drive unit 46 Command signal generator 47 Two-phase command signal generator Unit 54 reference potential 55 preamplifier 62 rotor position signal generation unit 66 logic processing unit 67 level shift unit 80, 80A, 80B, 80T drive signal generation unit 81, 81A, 81T drive unit 82, 82A, 82B, 82T current detection unit 83, 83A, 83B, 83T Target signal generation unit 84, 84A, 84T Comparison unit 85, 85A Inductive load 85T Three-phase drive motor 100 High potential power supply 101 Low potential power supply

Claims (25)

A forward drive state for supplying a drive current to an inductive load and a return state for receiving a return current from the inductive load are repeatedly performed to drive the inductive load,
Drive signal generating means for generating a drive signal representing the logical state of the forward drive state and the reflux state;
Driving means for generating the driving current based on the driving signal;
Current detection means for detecting at least the drive current and generating a current detection signal;
Target signal generating means for generating a target signal representing a target value of a current flowing through the inductive load;
Comparing means for comparing the current detection signal with the target signal and generating a comparison result signal,
The load drive device, wherein the drive signal generation unit controls the drive signal and inhibits the forward drive state based on the comparison result signal.   The load driving device according to claim 1, wherein the drive signal generating unit maintains the return state based on the comparison result signal.   The drive signal generation means switches from the return state to a reverse drive state in which the drive current is supplied in a direction opposite to the forward direction based on the comparison result signal. The load driving device described.   2. The load driving device according to claim 1, wherein the driving signal generation unit prohibits the forward driving state when a magnitude of the current detection signal is equal to or larger than a magnitude of the target signal. 3.   2. The load driving device according to claim 1, wherein the driving signal generation unit prohibits the forward driving state when a period of the forward driving state becomes shorter than a predetermined period. 3. The driving means includes N (N is an integer of 2 or more) half bridges including two driving switches,
The at least one of the 2 × N drive switches is in a PWM drive state that repeats an on state and an off state, respectively, in the repetition of the forward drive state and the return state. 2. The load driving device according to 1.   The load driving device according to claim 6, wherein the other driving switch of the half bridge including the driving switch in the PWM driving state is in an off state in the reflux state.   The load driving device according to claim 6, wherein all of the drive switches other than the drive switch in the PWM drive state are in an off state in the return state. The driving means includes
In each of the 2 × N drive switches, 2 × N diodes connected in the reverse conduction direction are provided in parallel.
Inserted between the first power source and the second power source via the current detection means;
The load drive according to claim 7, wherein the other drive switch is connected to the current detection means, and the diode connected to the other drive switch is connected to the second power source. apparatus. The current detection means includes
Connected to the N common connection points of the two drive switches included in each of the N half bridges and the inductive load;
The load driving device according to claim 6, wherein the driving current and the return current are detected from the common connection point.   The drive signal generating means drives the drive in the direction opposite to the forward direction from the return state based on the comparison result signal and the first control state for maintaining the return state based on the comparison result signal. 2. The load driving device according to claim 1, wherein one of the second control states for switching to a reverse driving state for supplying a current is selected.   The drive signal generating means includes: a third control state in which the other drive switch of the half bridge including the drive switch in the PWM drive state is set to a non-operation level in the return state; and the drive switch in the PWM drive state Any one of the fourth control states in which all other drive switches are set to the non-operating level in the reflux state and the fifth control state in which the other drive switch is set to the operating level in the return state The load driving device according to claim 6, wherein the load driving device is selected.   The load driving device according to claim 1, wherein the load driving device drives a three-phase driving motor. A forward drive state in which a drive current is supplied to an inductive load and a return state that receives a return current from the inductive load are repeatedly performed to drive the inductive load,
Generating a drive signal representing the logical state of the forward drive state and the reflux state;
Generating the drive current based on the drive signal;
Detecting at least the drive current and generating a current detection signal;
Generating a target signal representing a target value of the current flowing through the inductive load;
Comparing the current detection signal with the target signal and generating a comparison result signal;
A load driving method, wherein the driving signal is controlled, and the forward driving state is prohibited based on the comparison result signal.   The load driving method according to claim 14, wherein the reflux state is maintained based on the comparison result signal.   The load driving method according to claim 14, wherein, based on the comparison result signal, switching from the return state to a reverse drive state in which the drive current is supplied in a direction opposite to the forward direction.   The load driving method according to claim 14, wherein when the magnitude of the current detection signal is greater than or equal to the magnitude of the target signal, the forward drive state is prohibited.   15. The load driving method according to claim 14, wherein the forward driving state is prohibited when a period of the forward driving state becomes shorter than a predetermined period.   In N half bridges (N is an integer of 2 or more) including two drive switches, at least one of the 2 × N drive switches repeats the forward drive state and the reflux state. The load driving method according to claim 14, wherein the load driving method is in a PWM driving state in which an ON state and an OFF state are repeated.   The load driving method according to claim 19, wherein the other driving switch of the half bridge including the driving switch in the PWM driving state is in an off state in the reflux state.   20. The load driving method according to claim 19, wherein all of the drive switches other than the drive switch in the PWM drive state are in an off state in the return state.   The drive current and the return current are detected from N common connection points of the two drive switches included in each of the N half bridges and the inductive load. Item 20. The load driving method according to Item 19.   A first control state that maintains the return state based on the comparison result signal, and a reverse direction drive that supplies the drive current from the return state in a direction opposite to the forward direction based on the comparison result signal. The load driving method according to claim 14, wherein one of the second control states to be switched to the state is selected.   A third control state in which the other drive switch of the half bridge including the drive switch in the PWM drive state is set to a non-operation level in the return state; and a drive switch other than the drive switch in the PWM drive state; One of the fourth control state in which the operation state is set to the non-operating level in the reflux state and the fifth control state in which the other drive switch is set to the operation level in the return state are selected. The load driving method according to claim 19. The load driving method according to claim 14, wherein the three-phase driving motor is driven.

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