JP2007157823A - Magnetic memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an MRAM (Magnetic Random Access Memory) assuring higher integration density. <P>SOLUTION: The memory cells MC (m, n) and MC (m+1, n) have the magnetic tunnel junction elements MR1 and MR11 respectively connected with the word lines WLn at one end, and connected with the bit lines BLm and BLm+1 at the other end of the magnetic tunnel junction elements MR1 and MR11. Moreover, the memory cells MC (m, n+1) and MC (m+1, n+1) have the magnetic tunnel junction elements MR3 and MR31 respectively connected with the word lines WLn+1 at the one end, and connected respectively with the bit lines BLm and BLm+1 at the other end of the magnetic tunnel junction elements MR3 and MR31. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a magnetic memory device, and more particularly to a magnetic memory device having a nonvolatile memory array using a magnetic tunnel resistance element for each memory cell.

  A structure in which an insulator is sandwiched between two ferromagnets is called a magnetic tunnel junction (MTJ), and an element having at least one magnetic tunnel junction is a magnetic tunnel resistance element or a magnetic tunnel. It is called a junction element.

  When a voltage is applied between two ferromagnets, when the current tunneling through the insulator is measured, a phenomenon is observed in which the current value varies depending on the direction of the magnetization vectors of the two ferromagnets. This phenomenon occurs because the magnetic tunnel resistance in the insulator changes, and is referred to as a tunnel magnetic resistance (TMR) effect.

  Of the two ferromagnets, the direction of one magnetization vector is fixed, and the direction of the other magnetization vector can be arbitrarily changed to the same or opposite direction. A device that stores information by correlating the magnetization direction of the body with bit 0 or bit 1 is an MRAM (Magnetic Random Access Memory).

  That is, of the two combinations of the magnetization directions of the two ferromagnets, the combination with the higher resistance is set to bit 1, the combination with the lower resistance is set to bit 0, or vice versa. Memory becomes possible.

Patent Document 1 discloses an example of a conventional magnetic storage device.
For example, in FIG. 1 of Patent Document 1, a structure of a general magnetic tunnel junction element is shown.

  In the magnetic tunnel junction element shown in FIG. 1 of Patent Document 1, two ferromagnetic layers are stacked on an insulator layer, and a ferromagnetic layer is disposed below the insulator layer to form a magnetic tunnel junction. It is composed. Note that an antiferromagnetic layer is disposed below the ferromagnetic layer. This antiferromagnetic layer is for fixing the direction of magnetization of the immediately above ferromagnetic layer, and this structure is called a spin valve type magnetic tunnel junction.

  The magnetic tunnel junction element is embedded in an interlayer insulating film, and wiring layers are respectively disposed above and below the magnetic tunnel junction element. The extending directions of the two wiring layers are mutually in plan view. The directions are orthogonal.

  Information is written to the magnetic tunnel junction element by one of the two ferromagnetic layers sandwiching the insulator layer by a magnetic field generated by applying a predetermined current to the two wiring layers (word line and bit line). This is done by determining the direction of the magnetization vector.

Japanese Patent Laying-Open No. 2003-297069 (FIG. 1)

  As described above, the conventional magnetic memory device employs a configuration in which the magnetic tunnel junction element is disposed between the wiring layers in a vertical relationship, so that the occupied area of the memory cell is the spacing between the wiring layers. It will be decided by.

  In general, since the arrangement interval of the wiring layer is set larger than the arrangement interval of the gate electrode, the occupied area of the memory cell of the MRAM is in an electrostatic storage device such as a DRAM (Dynamic Random Access Memory). There has been a problem that the degree of integration of the MRAM is smaller than that of an electrostatic storage device such as a DRAM.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide an MRAM with an increased degree of integration.

  According to a first aspect of the present invention, there is provided a magnetic storage device comprising a plurality of memory cells each having a plurality of bit lines and a plurality of word lines that intersect in a non-contact manner to form a matrix and a magnetic tunnel junction element. In the device, the plurality of memory cells each include first and second magnetic tunnel junction elements commonly connected to one word line of the plurality of word lines. A plurality of memory cell pairs each including a memory cell, wherein the first magnetic tunnel junction element of the first memory cell has one end connected to the word line and the other end connected to the plurality of bit lines; One end connected to the word line and the other end of the plurality of bit lines connected to the first bit line of the second memory cell. It is connected to the second bit line.

  According to the magnetic memory device of the first aspect of the present invention, since the first and second magnetic tunnel junction elements are commonly connected to one word line, the first and second magnetic tunnel junction elements are formed on both side surfaces of the word line. By forming the second magnetic tunnel junction element, the arrangement interval of the magnetic tunnel junction elements can be set to the same degree as the arrangement interval of the gate electrodes, and the magnetic tunnel junction elements are arranged between the upper and lower wiring layers. Compared with a conventional MRAM in which a junction element is provided, the degree of integration of memory cells can be increased, and the area occupied by the memory cells can be reduced to the same level or less as that of an electrostatic storage device such as a DRAM. . In addition, since the word line is commonly used by the two magnetic tunnel junction elements, the bit information stored in the two magnetic tunnel junction elements can be read simultaneously, and the information reading speed can be improved.

<Embodiment>
<A. Device configuration>
FIG. 1 shows a circuit configuration of a memory cell array of an MRAM 100 according to an embodiment of the present invention.

  As shown in FIG. 1, the memory cell array of the MRAM 100 has a configuration in which a plurality of pairs of memory cells commonly connected to one word line are connected.

  That is, memory cell MC (m, n) has a magnetic tunnel junction element MR1 connected at one end to word line WLn, and the other end of magnetic tunnel junction element MR1 is connected to bit line BLm and a diode. It is connected to a common potential (substrate potential here) via D1.

  The memory cell MC (m + 1, n) has a magnetic tunnel junction element MR11 having one end connected to the word line WLn, and the other end of the magnetic tunnel junction element MR11 is connected to the bit line BLm + 1. It is connected to a common potential via D11.

  As described above, the memory cell MC (m, n) and the memory cell MC (m + 1, n) are commonly connected to the word line WLn to form a pair, and are referred to as a memory cell pair MP1.

  Similarly, the memory cell MC (m + 2, n) has a magnetic tunnel junction element MR2 having one end connected to the word line WLn, and the other end of the magnetic tunnel junction element MR2 is connected to the bit line BLm + 2. It is connected to a common potential via a diode D2.

  Memory cell MC (m + 3, n) has magnetic tunnel junction element MR21 having one end connected to word line WLn, and the other end of magnetic tunnel junction element MR21 is connected to bit line BLm + 3, and a diode. It is connected to a common potential via D21.

  As described above, the memory cell MC (m + 2, n) and the memory cell MC (m + 3, n) are commonly connected to the word line WLn to form a pair and are referred to as a memory cell pair MP2.

  Memory cell MC (m, n + 1) has magnetic tunnel junction element MR3 having one end connected to word line WLn + 1, and the other end of magnetic tunnel junction element MR3 is connected to bit line BLm and diode D3 is connected to memory cell MC (m, n + 1). To the common potential.

  The memory cell MC (m + 1, n + 1) has a magnetic tunnel junction element MR31 having one end connected to the word line WLn + 1, and the other end of the magnetic tunnel junction element MR31 is connected to the bit line BLm + 1 and a diode. It is connected to a common potential via D31.

  As described above, the memory cell MC (m, n + 1) and the memory cell MC (m + 1, n + 1) are commonly connected to the word line WLn + 1 to form a pair and are referred to as a memory cell pair MP3.

  Memory cell MC (m + 2, n + 1) has a magnetic tunnel junction element MR4 having one end connected to word line WLn + 1, and the other end of magnetic tunnel junction element MR4 is connected to bit line BLm + 2 and via diode D4. Connected to a common potential.

  Memory cell MC (m + 3, n + 1) has magnetic tunnel junction element MR41 having one end connected to word line WLn + 1, and the other end of magnetic tunnel junction element MR41 is connected to bit line BLm + 3 and a diode. It is connected to a common potential via D41.

  As described above, the memory cell MC (m + 2, n + 1) and the memory cell MC (m + 3, n + 1) are commonly connected to the word line WLn + 1 to form a pair and are referred to as a memory cell pair MP4.

  In FIG. 1, only four memory cell pairs MP1 to MP4 are shown, but these are part of the MRAM 100, and each of the word line WLn and the word line WLn + 1 includes a plurality of memory cells. It goes without saying that pairs are connected and that there are a plurality of word lines and bit lines.

  FIG. 2 schematically shows a planar layout of the memory cell array portion of the MRAM 100.

  FIG. 2 shows memory cells constituting the memory cell pairs MP1 to MP4 shown in FIG. 1 in the memory cell array.

  As shown in FIG. 2, bit lines BLm, BLm + 1, BLm + 2 and BLm + 3 are arranged in parallel, and word lines WLn and WLn + 1 are arranged in parallel so as to be orthogonal to these bit lines in plan view. .

  Magnetic tunnel junction elements MR1 and MR11, MR2 and MR21 are arranged in contact with both side surfaces in the width direction of word line WLn, and magnetic tunnel junction element MR3 is arranged on both side surfaces in the width direction of word line WLn + 1. MR31, MR4, and MR41 are disposed so as to contact each other.

  Here, since the bit lines BLm and BLm + 1 are connected to the memory cell pair MP1 and MP3, they can be referred to as paired bit lines, and the bit lines BLm + 2 and BLm + 3 are connected to the memory cell pair MP2 and MP4. , Can be referred to as a pair of bit lines.

  The bit lines BLm + 1 and BLm + 3 are configured by first layer wirings, and the bit lines BLm and BLm + 2 are configured by second layer wirings provided above the first layer wiring, both of which are formed as metal wirings. Yes. The first layer wiring is indicated by a broken line for convenience.

  Word lines WLn and WLn + 1 are configured by gate wirings formed in the same process as the gate electrodes of MOS transistors (not shown). The magnetic tunnel junction elements MR1 and MR11, MR2 and MR21 provided on the side surface of the word line WLn are configured as sidewalls of the word line WLn and provided on the side surface of the word line WLn + 1. MR31, MR4, and MR41 are configured as sidewalls of word line WLn + 1.

  The magnetic tunnel junction elements MR1 and MR11, MR3 and MR31 are arranged in a line, and a bit line BLm is disposed above the arrangement along the extending direction of the arrangement, and the magnetic tunnel junction Elements MR2 and MR21, MR4 and MR41 are arranged in a line, and bit line BLm + 2 is arranged above the arrangement along the extending direction of the array.

  Magnetic tunnel junction elements MR1 and MR3 are electrically connected to bit line BLm via contact portion C1 and via portion V1, and magnetic tunnel junction elements MR11 and MR31 are connected to bit line BLm + 1 via contact portion C1. Electrically connected. Similarly, magnetic tunnel junction elements MR2 and MR4 are electrically connected to bit line BLm + 2 via contact portion C1 and via portion V1, and magnetic tunnel junction elements MR21 and MR41 are connected to bit line BLm + 3 via contact portion C1. Is electrically connected.

FIG. 3 shows a cross-sectional configuration taken along line AA shown in FIG.
As shown in FIG. 3, a P-type well layer 2 is disposed on the upper layer portion of the silicon substrate 1, and an element isolation insulating film 3 having an STI (Shallow Trench Isolation) structure formed using a well-known technique is provided. It is selectively arranged.

  A magnetic tunnel junction element and a word line are disposed on the element isolation insulating film 3. Taking the word line WLn and the magnetic tunnel junction elements MR1 and MR11 as examples, an insulating film 21 formed in the same process as the gate insulating film of the MOS transistor is selectively disposed on the element isolation insulating film 3. On the insulating film 21, a word line WLn formed in the same process as the gate electrode of the MOS transistor is disposed. The element isolation insulating film 3 is linearly disposed along the extending direction of the word line WLn.

  The insulating film 21 is formed of a high dielectric film called a so-called High-k film such as a silicon oxide film, a silicon oxynitride film, or HfSiON (hafnium silicate containing nitrogen).

  An insulating film 22 is provided on the element isolation insulating film 3 so as to sandwich the insulating film 21 from both sides. Magnetic tunnel junction elements MR1 and MR11 are provided on the insulating film 22.

  The insulating film 22 is composed of a silicon oxide film, a silicon oxynitride film, or a high dielectric film such as HfSiON, like the insulating film 21, and the insulating films 21 and 22 may be formed as an integral film of the same material. Alternatively, different films may be formed of different materials.

  The magnetic tunnel junction elements MR1 and MR11 formed on the insulating film 22 have basically the same configuration, and are stacked on the side surface of the word line WLn in order from the word line WLn side to form a ferromagnetic film / anti-strength. A multilayer film 11 of a magnetic film, an insulating film 12 and a multilayer film 13 of a ferromagnetic film are disposed.

  Here, the forming method of the multilayer film 11, the insulating film 12, and the multilayer film 13 is basically the same as the forming method of the sidewall insulating film of the MOS transistor. After forming the word line, the entire surface of the silicon substrate 1 is formed. The multilayer film 11 is formed so as to cover it, and the multilayer film 11 other than the side surface of the word line is removed by anisotropic etching. Subsequently, an insulating film 12 is formed so as to cover the entire surface of the silicon substrate 1, and the insulating film 12 other than the side surfaces of the multilayer film 11 is removed by anisotropic etching. Finally, the multilayer film 13 is formed so as to cover the entire surface of the silicon substrate 1, and the multilayer film 13 other than the side surface of the insulating film 12 is removed by anisotropic etching, so that the multilayer film 13 is stacked on the side surface of the word line. A configuration in which the film 11, the insulating film 12, and the multilayer film 13 are disposed can be obtained.

  Further, after the word line is formed, the multilayer film 11, the insulating film 12, and the multilayer film 13 are sequentially formed so as to cover the entire surface of the silicon substrate 1, and the multilayer film 11, the insulating film 12, and the multilayer film other than the side surface of the word line are formed. A method of removing 13 by one-time anisotropic etching may be employed.

  As shown in FIG. 2, the word lines are arranged so as to extend over the entire arrangement area of the memory cell array, and only a part of them is connected to the magnetic tunnel junction element. Therefore, it goes without saying that the portion where the magnetic tunnel junction element is not connected is masked with a photoresist, an insulating film or the like when the magnetic tunnel junction element is formed.

  For the multilayer film 11 of the ferromagnetic film / antiferromagnetic film, a material is selected that is less likely to reverse the direction of the magnetization vector than the multilayer film 13 of the ferromagnetic film, and the multilayer film 13 of the ferromagnetic film is selected. Even if a magnetic field that reverses the direction of the magnetization vector is applied, the direction of magnetization does not reverse, and it is called a pinned layer. On the other hand, the multilayer film 13 of a ferromagnetic film is called a free layer because the direction of the magnetization vector can be easily reversed by a magnetic field, and these multilayer films constitute a so-called spin valve type magnetic tunnel junction. ing.

  In FIG. 3, magnetization vectors formed in the multilayer films 11 and 13 are schematically indicated by arrows, and the magnetization vectors are oriented in a direction perpendicular to the main surface of the silicon substrate 1. However, the direction of the magnetization vector is not limited to this direction, and a direction parallel to the main surface of the silicon substrate 1 or an angle other than perpendicular to the main surface of the silicon substrate 1 may be used.

  In addition, the multilayer films 11 and 13 and the insulating film 12 do not have to have a particularly new composition, and films having a known composition may be employed.

For example, an alumina insulating material such as Al ₂ O ₃ or AlO _x is used for the insulating film 12, CoFe is used for the ferromagnetic film included in the multilayer film 11, and the antiferromagnetic film is used for the antiferromagnetic film. For example, IrMn containing 20 to 30 atom.% Of Ir (iridium) may be used, and CoFe or Ni ₈₀ Fe ₂₀ may be used for the ferromagnetic film included in the multilayer film 13.

  Here, the information storing operation in the magnetic tunnel junction element will be described with reference to FIGS.

  4A and 4B show a cross-sectional configuration of the magnetic tunnel junction element MR, which is the same configuration as the magnetic tunnel junction element constituting the MRAM 100 shown in FIGS.

  As shown in FIG. 4A, the multilayer film 11 is composed of a ferromagnetic multilayer film 112 and an antiferromagnetic film 111. The direction of the magnetization vector of the ferromagnetic multilayer film 112 and The direction of the magnetization vector of the multilayer film 13 of the magnetic film is the same. This state is referred to as a Bit0 (or 1) state.

  On the other hand, in FIG. 4B, the direction of the magnetization vector of the multilayer film 112 made of ferromagnetic material is opposite to the direction of the magnetization vector of the multilayer film 13 made of ferromagnetic film. This is because the direction of the magnetization vector of the multilayer film 13 that is a free layer is reversed by applying a magnetic field from the outside, and the direction of the magnetization vector of the multilayer film 112 that is a pinned layer is fixed. This state is referred to as a Bit1 (or 0) state.

  In this way, depending on whether the magnetization vector directions of the ferromagnetic multilayer films 13 and 112 sandwiching the insulating film 12 are the same state (parallel state) or 180 ° different states (antiparallel state: Antiparallel), Resistance value decreases or increases. Bit information is stored in the magnetic tunnel junction element MR by the binary change of the resistance value.

  Since the direction of the magnetization vector of the multilayer film 13 does not change unless a magnetic field is applied from the outside, even if the power supply to the MRAM is stopped, the bit information of the magnetic tunnel junction element MR is stored in a nonvolatile manner and is not lost. Absent.

Here, the description returns to FIG. 3 again.
The upper portions of the word lines WLn, WLn + 1, the ferromagnetic film / antiferromagnetic film multilayer film 11, the insulating film 12 and the ferromagnetic film multilayer film 13 are covered with the interlayer insulating film 5, and the multilayer film 13 It is configured to be connected to the side surface of the contact portion C1 that penetrates the insulating film 5 and reaches the silicon substrate 1.

  That is, between the element isolation insulating films 3 selectively provided in the upper layer portion of the P-type well layer 2, a semiconductor layer 4 containing an N-type impurity is provided on the surface of the P-type well layer 2. It has been. The semiconductor layer 4 is selectively disposed outside the both side surfaces of the element isolation insulating film 3 in accordance with the position of the magnetic tunnel junction element disposed on the element isolation insulating film 3.

  A hole CH1 is provided so as to penetrate the interlayer insulating film 5 and reach the semiconductor layer 4, and a conductive film 31 such as TaN is provided so as to cover the inner surface of the hole CH1. The hole CH1 covered with the conductive film 31 is filled with a conductor such as W (tungsten) to form the plug 32. The plug 32 and the conductive film 31 form the contact portion C1, and the multilayer film 13 Is connected to the side surface of the contact portion C1. Precisely, the outermost layer film of the multilayer film 13 (the film on the side opposite to the film that contacts the side surface of the word line) is connected to the side surface of the contact portion C1. Note that, depending on the material of the plug 32, the conductive film 31 may not be required, so that the contact portion can be configured without the conductive film 31.

  Here, a PN junction diode is formed by the semiconductor layer 4 and the P-type well layer 2, and these become the diodes D1 to D4 and D11 to D41 shown in FIG.

  Note that an N-type well layer may be formed instead of the P-type well layer 2 and the semiconductor layer 4 may be composed of P-type impurities. A thyristor may be used in place of the diode, and it is not limited to a PN junction diode or a Schottky diode as long as it has a rectifying action.

  The contact portion C1 is formed by forming a hole CH1 penetrating the interlayer insulating film 5 and reaching the semiconductor layer 4, covering the inner surface of the hole CH1 with the conductive film 31, and then covering the entire surface of the interlayer insulating film 5 over the first surface. A material for layer wiring, for example, a tungsten layer is formed, and the tungsten layer is filled in the hole CH1 to form the plug 32. Thereafter, the first layer wiring such as the bit lines BLm + 1 and BLm + 3 is patterned, and the contact portion C1 is also patterned.

  As shown in FIG. 2, the contact portion C1 electrically connected to the magnetic tunnel junction elements MR11 and MR31 is connected to the first layer wiring, but electrically connected to the magnetic tunnel junction elements MR1 and MR3. The contact part C1 to be connected is patterned so as to be independent of the first layer wiring.

  The contact portion C1 and the first layer wiring may be formed in separate steps, and the contact portion C1 and the first layer wiring may have different materials.

  An interlayer insulating film 6 covering the contact portion C1 is disposed on the interlayer insulating film 5, and second layer wirings such as bit lines BLm and BLm + 2 are disposed on the interlayer insulating film 6. The second layer wiring (bit line BLm in FIG. 3) is configured to be electrically connected to the contact portion C1 through the via portion V1 that penetrates the interlayer insulating film 6 and reaches the contact portion C1. .

  The via portion V1 is configured to be connected to a contact portion C1 other than the contact portion C1 connected to the first layer wiring among the plurality of contact portions C1, and in FIG. 3, the via portion V1 is electrically connected to the magnetic tunnel junction element MR1. The contact portion C1 to be connected and the contact portion C1 electrically connected to the magnetic tunnel junction element MR3 are configured to be connected.

  Here, the via portion V1 is formed by forming a hole CH2 that penetrates through the interlayer insulating film 6 and reaches the predetermined contact portion C1, and then forms aluminum on the entire surface of the interlayer insulating film 6 as a material for the second layer wiring. Alternatively, a conductive film is formed with copper or the like and the inside of the hole CH2 is filled. Thereafter, the via layer V1 is obtained by patterning the second layer wiring such as the bit lines BLm and BLm + 2.

  In the above description, as shown in FIG. 3, the multilayer film 13 of the ferromagnetic film constituting the magnetic tunnel junction element is described as being electrically connected to the contact portion C1, but the ferromagnetic film The arrangement position of the multilayer film 13 and the multilayer film 11 is set so that the multilayer film 11 of the body film / antiferromagnetic film is connected to the contact portion C1, and the ferromagnetic film is in contact with the insulating film 12. You may replace it as you do.

<B. Device operation>
Next, bit information writing and reading operations in the MRAM 100 will be described with reference to FIGS.

  FIG. 5 is a diagram for explaining a bit information write operation in the MRAM 100, and assumes a case where a memory cell MC (m + 1, n) including the magnetic tunnel junction element MR11 is a write target cell.

  In FIG. 5, a current is passed through the word line WLn to be the selected word line in a direction perpendicular to the drawing and from the far side to the near side.

  At this time, for example, a voltage of minus 2 V is applied to the bit line BLm + 1 so that a current flows from the silicon substrate 1 toward the bit line BLm + 1 via the contact portion C1 connected to the bit line BLm + 1. The voltage of the P-type well layer 2 is set to 0V. In this case, since a voltage is applied in the forward direction (forward biased) to the diode D11 formed of the semiconductor layer 4 and the P-type well layer 2, the silicon substrate 1 is applied to the bit line BLm + 1. An electric current flows toward.

  On the other hand, by setting the voltage of the bit line BLm, which is a non-selected bit line, to +1 V, a voltage is applied in the reverse direction to the diodes D1 and D3 formed by the semiconductor layer 4 and the P-type well layer 2. Therefore, no current flows from the silicon substrate 1 toward the bit line BLm. Further, a current is not allowed to flow through the word line WLn + 1 which is a non-selected word line.

  Thus, by providing the diodes D1 to D4 and D11 to D41, when writing bit information, a non-selected memory cell is reverse-biased so that no current flows through the contact portion C1. In the selected memory cell, bit information can be written by applying a forward bias to flow a current through the contact portion C1.

  As described above, the magnetization vector of the multilayer film 13 of the magnetic tunnel junction element MR11 is generated by the combined magnetic field generated by the current flowing through the word line WLn and the contact portion C1 arranged orthogonal to each other. It can be set in a predetermined direction.

  Here, the magnitude of the synthetic magnetic field to be generated is set so as to be larger than the critical magnetic field necessary for changing the direction of the magnetization vector of the multilayer film 13.

  Here, the magnetic tunnel junction element MR1 of the memory cell adjacent to the memory cell MC (m + 1, n) that is the write target cell, that is, the memory cell MC (m, n) commonly connected to the word line WLn has a magnetization. Only one of the two types of currents for controlling the direction of the vector is supplied, and is in a half-select state. In this case, since only a current flowing through the word line WLn is set so as not to generate a combined magnetic field that changes the direction of the magnetization vector of the multilayer film 13, the bit information of the cell adjacent to the write target cell changes. Never do.

  FIG. 6 is a diagram for explaining an operation of writing bit information different from the case of FIG. 5 to the memory cell MC (m + 1, n) that is a write target cell.

  In FIG. 6, a current is supplied to the word line WLn to be a selected word line in a direction perpendicular to the drawing and from the near side to the far side. The word line WLn is different from the case of FIG. The direction of the current flowing through the is different.

  For this reason, since the direction of the generated synthetic magnetic field is opposite to that in FIG. 5, the direction of the magnetization vector of the multilayer film 13 of the magnetic tunnel junction element MR11 is also set to be opposite to that in FIG.

  In FIG. 5, the direction of the magnetization vector of the multilayer film 13 shows a state opposite to the direction of the magnetization vector of the multilayer film 11 (anti-parallel state), and in FIG. 6, the direction of the magnetization vector of the multilayer film 13 However, in order to set the direction of the magnetization vector of the free layer, the direction of the current flowing through the selected word line and the selected bit line is arbitrarily set. Can be set. Also, whether the direction of the magnetization vector of the free layer is assigned to 0 or 1 is arbitrarily set depending on whether the direction of the magnetization vector is parallel or antiparallel to the pinned layer. be able to.

  FIG. 7 is a diagram for explaining the read operation of bit information in the MRAM 100. The memory cell MC (m, n) including the magnetic tunnel junction element MR1 and the memory cell MC (m + 1, n) including the magnetic tunnel junction element MR11 are illustrated. It is assumed that the cell is a read target cell.

  As described above, the bit information differs depending on whether the direction of the magnetization vector of the free layer is parallel to the pinned layer or antiparallel, and the difference in bit information is the difference between the free layer and the pinned layer. It is defined by the difference in the magnetic tunnel resistance of the insulating film sandwiched between.

  Therefore, when a predetermined voltage is applied to the word line WLn, the bit line BLm, and the bit line BLm + 1 in a pair of read target cells connected to the common word line WLn, the magnetic tunnel junction elements MR1 and MR11 are respectively magnetically connected. Current flows according to the tunnel resistance.

  Specifically, as shown in FIG. 7, for example, a voltage of 1 V is applied to the word line WLn to be a selected word line, the voltages of the bit lines BLm and BLm + 1 are set to 0 V, and the bit lines BLm and BLm + 1 are supplied from the word line WLn. Keep the current flowing toward On the other hand, the voltage of the word line WLn + 1 that is a non-selected word line is set to 0 V so that no current flows from the word line WLn + 1 to the bit lines BLm and BLm + 1. The voltage of the P-type well layer 2 is also set to 0V.

  Through the above operation, currents flow through the magnetic tunnel junction elements MR1 and MR11 according to the respective magnetic tunnel resistances, and the currents are detected by the sense amplifiers (not shown) connected to the bit lines BLm and BLm + 1. Thus, the bit information held in the magnetic tunnel junction elements MR1 and MR11 can be read out simultaneously. The sense system in the sense amplifier may be current sense or voltage sense, and a known configuration may be adopted as the configuration of the sense amplifier.

<C. Effect>
As described above, in the MRAM 100, the multilayer film 11 of the ferromagnetic film / antiferromagnetic film is laminated so as to be stacked on both side surfaces of the word line formed simultaneously in the step of forming the gate electrode of the MOS transistor. A magnetic tunnel junction element formed by disposing an insulating film 12 and a multilayer film 13 of a ferromagnetic film is used.

  For this reason, the arrangement interval of the magnetic tunnel junction elements can be set to be approximately the same as the arrangement interval of the gate electrodes, and the conventional MRAM in which the magnetic tunnel junction elements are arranged between the upper and lower wiring layers is used. In comparison, the degree of integration of the memory cells can be increased, and the area occupied by the memory cells can be made equal to or less than that of an electrostatic storage device such as a DRAM.

  In addition, since magnetic tunnel junction elements are stacked on both sides of the word line and the word line is used in common by the two magnetic tunnel junction elements, the bit information stored in the two magnetic tunnel junction elements can be read simultaneously. And the reading speed of information can be improved.

<D. Modification>
In the embodiment described above, the multilayer film 11 of the ferromagnetic film / antiferromagnetic film is laminated on both side surfaces of the word line formed simultaneously in the step of forming the gate electrode of the MOS transistor. Although a magnetic tunnel junction device having an insulating film 12 and a multilayer film 13 of a ferromagnetic film is shown, a multilayer of ferromagnetic film / antiferromagnetic film is laminated so as to be laminated only on one side surface of a word line. A configuration in which the film 11, the insulating film 12, and the multilayer film 13 of the ferromagnetic film are disposed may be employed.

  Also in this case, the degree of integration of the memory cells can be increased as compared with the conventional MRAM in which the magnetic tunnel junction elements are disposed between the wiring layers in the vertical relationship, and the occupied area of the memory cells can be reduced by the electrostatic capacity of the DRAM or the like. It is possible to make it less than or equal to a typical storage device.

It is a circuit diagram which shows the structure of MRAM of embodiment which concerns on this invention. It is a top view which shows the structure of MRAM of embodiment which concerns on this invention. It is sectional drawing which shows the structure of MRAM of embodiment which concerns on this invention. It is sectional drawing explaining the memory | storage operation | movement of the information in a magnetic tunnel junction element. It is sectional drawing explaining the write-in operation | movement of the bit information of MRAM of embodiment which concerns on this invention. It is sectional drawing explaining the write-in operation | movement of the bit information of MRAM of embodiment which concerns on this invention. It is sectional drawing explaining the read-out operation | movement of the bit information of MRAM of embodiment which concerns on this invention.

Explanation of symbols

2 P-type well layer, 3 element isolation insulating film, 4 semiconductor layer, 5 interlayer insulating film, MR1-MR4, MR11-MR41 magnetic tunnel junction element, WLn, WLn + 1 word line, BLn, BLn + 1, BLn + 2, BLn + 3 bit line.

Claims (5)

A plurality of bit lines and a plurality of word lines that intersect in a non-contact manner to form a matrix;
A magnetic storage device comprising a plurality of memory cells each having a magnetic tunnel junction element,
The plurality of memory cells include
A plurality of memory cell pairs each including first and second memory cells each having first and second magnetic tunnel junction elements commonly connected to one of the plurality of word lines; ,
The first magnetic tunnel junction element of the first memory cell has one end connected to the word line and the other end connected to a first bit line of the plurality of bit lines,
The second magnetic tunnel junction element of the second memory cell has one end connected to the word line and the other end connected to a second bit line of the plurality of bit lines. Storage device. The first memory cell has a first rectifying element connected between the other end of the first magnetic tunnel junction element and a predetermined potential,
The magnetic memory device according to claim 1, wherein the second memory cell includes a second rectifying element connected between the other end of the second magnetic tunnel junction element and the predetermined potential. The word line, the first and second magnetic tunnel junction elements are disposed on an element isolation insulating film selectively disposed on an upper layer portion of the semiconductor substrate,
The first and second magnetic tunnel junction elements each include a multilayer film that is selectively stacked on both side surfaces of the word line so as to have the same arrangement order toward the outside.
The multilayer film is
The magnetic memory device according to claim 1, comprising at least an insulating film and two ferromagnetic films disposed so as to sandwich the insulating film. The magnetic memory device includes an interlayer insulating film covering the word lines and the first and second magnetic tunnel junction elements,
In the first magnetic tunnel junction element, the outermost layer film of the multilayer film is in contact with the side surface of the first contact part that penetrates the interlayer insulating film and reaches the semiconductor substrate,
In the second magnetic tunnel junction element, an outermost layer film of the multilayer film is in contact with a side surface of a second contact part that penetrates the interlayer insulating film and reaches the semiconductor substrate,
The magnetic memory device according to claim 3, wherein the first contact portion is connected to the first bit line, and the second contact portion is connected to the second bit line. A first conductivity type first semiconductor layer disposed in an upper layer portion of the semiconductor substrate;
A second semiconductor layer of a second conductivity type selectively disposed on an upper layer portion of the first semiconductor layer,
The element isolation insulating film is linearly disposed on the upper layer portion of the first semiconductor layer so as to extend along the word line,
The second semiconductor layer is selectively disposed outside both side surfaces of the element isolation insulating film,
The magnetic memory device according to claim 4, wherein the first and second contact portions are arranged to reach the second semiconductor layer.

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