JP2007156620A - Multiplier with asynchronous code and its algorithm - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiplier with an asynchronous code attaining faster multiplication. <P>SOLUTION: This multiplier with an asynchronous code includes N pieces of partial product generators (PPG); an arithmetic module; and a preceding zero bit detector. The partial product generator generates a plurality of partial product values according to multipliers and multiplicands. The arithmetic module executes a total operation to outputs from the PPG ranging from the (N+1)th PPG to the first PPG, and the output from the Nth PPG is added at the end. Furthermore, when the preceding zero bit detector detects a preceding zero bit in the multipliers and the multiplicands, a partial product output corresponding to the bit of "0" is directly set as zero. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a multiplier and its algorithm, and more particularly to an asynchronous signed multiplier and its algorithm.

  Multipliers play an important role in many applications such as microprocessors, data signal processing, discrete cosine transforms, and so on. In fact, the multiplier consumes most of the computation time in the computing chip. Thus, the execution time of the multiplier determines the overall efficiency of the chip. To date, several approaches in synchronous circuit design have been provided, and some approaches in asynchronous circuit design have also been proposed. In general, asynchronous methods have several advantages over synchronous circuits, such as low power consumption, low average computation time, adaptability to different manufacturing processes and environments, and the like. In particular, these advantages are extremely important in solving the problems encountered by certain types of VLSIs (very large scale integrated circuits).

  Today's types of multipliers can be divided into right-to-left (R-L) array multipliers, left-to-right (L-R) array multipliers, partitioned array multipliers, and multiple array multipliers.

  FIG. 1A and FIG. 1B schematically illustrate a carry-save array multiplier 100 and a carry-save array multiplier 120, respectively. Both vessels have an 8 × 8 left-to-right (LR) architecture. Referring to FIGS. 1A and 1B, the LR multiplier 100 or 120 mainly includes a partial product generator (PPG) 102, an LR adder array 104, and a final stage adder 108. The difference between the RL multiplier and the LR multiplier is in the adder array 104 and the final stage adder 108. In the RL adder array, the summation operation starts with the least significant bit partial product (LSBPP), then the sum and carry are spread one step at a time to the next higher bit, and finally the highest bit in the final stage adder. The partial product of bits (MSBPP) is added. Conversely, in the LR adder array, the sum operation starts with the partial product (MSBPP) of the most significant bit, and the result spreads one step at a time to the next lower bit, and finally the least significant bit of the last stage adder. The partial product (LSBPP) is added.

  It is well known that one bit of either the multiplier or the multiplicand is 0, and the corresponding partial product should be “0”. However, in the case of the conventional type multiplier, the partial product operation is also executed redundantly for “0” bits, and time is wasted. In addition, for arithmetic elements, the general bit length is much shorter than the designed bit length in the system. That is, the value of the high order bit is often “0”, and the computation for these zeros is simply a waste of time.

  FIG. 2 is a graph showing a statistical distribution of the relationship between the number of hits of the multiplier and multiplicand and the effective bit length. Referring to FIG. 2, this graph is a statistic from 6,746,853 data, and the maximum valid bit of one data is generally 16 bits. In other words, almost all bit values exceeding 16 bits are “0”. Therefore, this statistical result proves that there is considerable room for speeding up multiplication operations.

  Based on the above description, an object of the present invention is to provide an asynchronous signed multiplier having a faster multiplication operation.

  Another object of the present invention is to provide an asynchronous signed multiplication algorithm for calculating signed data.

上記［数１］の計算から、第１の演算結果が得られる。その後、演算モジュールは第２の演算結果を得るために第１の演算結果にＤNを加算する。演算モジュールはさらに先行ゼロビット検出器へ結合され、これは乗数及び被乗数をビット順に、ＭＳＢ（最上位ビット）からＬＳＢ（最下位ビット）へとチェックする。チェックの間、最初の「１」ビットに先行する「０」ビットは何れも空ビットとしてカウントされ、対応する部分積値は「０」で出力される。最初の「１」ビットからＬＳＢまでの全てのビットは、有効ビットと呼ばれる。 The asynchronous signed multiplier provided by the present invention is suitable for a signed multiplication operation on a multiplier and a multiplicand, and the multiplier and multiplicand each have N bits and M bits. N and M are positive integers greater than zero, and the multiplier, multiplicand, and product are all two's complement. The asynchronous signed multiplier of the present invention includes N partial product generators (PPG) that are used to generate partial product results with multipliers and multiplicands, where the partial products are denoted by Di, where Di is In the i-th PPG, the partial product obtained by matching the timing of every bit number of the multiplicand with the i-th bit number of the multiplier is displayed. Further, i is an integer of N or less and 1 or more. Each partial product result includes M partial products, and all outputs from the partial product generator are sent to the arithmetic module, and the following [Equation 1] is calculated.

The first calculation result is obtained from the calculation of [Equation 1]. Thereafter, the calculation module adds DN to the first calculation result to obtain the second calculation result. The arithmetic module is further coupled to a leading zero bit detector, which checks the multiplier and multiplicand in bit order, MSB (most significant bit) to LSB (least significant bit). During the check, any “0” bits preceding the first “1” bit are counted as empty bits, and the corresponding partial product value is output as “0”. All bits from the first “1” bit to the LSB are called valid bits.

  In the above embodiment of the present invention, the asynchronous signed multiplier further includes a completion detector coupled to the arithmetic module for determining the second arithmetic result described above.

  On the other hand, the present invention provides an algorithm for an asynchronous signed multiplier suitable for a signed multiplication operation on a multiplier and a multiplicand, where the multiplier and multiplicand have N bits and M bits, respectively. N and M are positive integers greater than zero. The most significant bit of the multiplier or multiplicand is a sign bit. According to the present invention, in order to obtain a plurality of first partial product values, the multiplicand adjusts the timing from the bit number of the multiplier to the first bit number sequentially. Thereafter, the acquired first partial product values are summed to obtain a first calculation result. In addition, the multiplicand is timed with the Nth bit number of the multiplier to obtain a plurality of second partial product values. Next, the first calculation result is added by the second partial product value to obtain a second calculation result. For any “0” bit in the multiplier and multiplicand, the operation associated with the “0” bit is exempted and the associated partial product value is set directly to “0”.

  Since the partial product value associated with the most significant bits of the multiplier is scheduled at the end of the total sum operation to add the final sum, the present invention performs the operation on the signed number to reduce the computation time. Can be saved.

  FIG. 3 is a diagram illustrating 5 × 5 numbered normal multiplication operations with a sign from left to right. Referring to FIG. 3, where M1 and M2 indicate the multiplicand and multiplier, it is assumed that the upper bits of multiplier M2, for example x4, x3 and x2, are "0", and therefore the partial product associated with this "0" bit. The value is “0” regardless of the value of the multiplicand M1. Commonly speaking, operations associated with a “0” bit are exempted to save time, and the associated partial product value is set directly to “0”.

  However, for the signed numbers of multiplicand M1 and multiplier M2, the situation is different from that described above, and the most significant bits y4 and x4 of multiplicand M1 and multiplier M2 are sign bits. From FIG. 3, in the case of a multiplication operation on a signed number, it relates to one most significant bit of the multiplicand M1 / multiplier M2 excluding the partial product (y4x4) related to both the most significant bit of the multiplicand M1 and the multiplier M2. It can be seen that the remaining partial products need to be inverted in phase as shown in the portion enclosed by the broken line. Therefore, the original “0” partial product becomes “1” after phase inversion.

  Furthermore, since the effective bit length is usually not long, the partial product values of the first row, for example, y4x4, (y3x4) ′, (y2x4) ′, (y1x4) ′, and (y0x4) ′ in FIG. It can be seen that the addition operation for the subsequent partial value is executed continuously regardless of whether or not the next partial value is “0”. This wastes a lot of time unnecessarily.

  In order to solve the above problems, the present invention provides a 5 × 5 LR signed multiplication algorithm as shown in FIG. From the idea of reversal, the present invention calculates the partial product value of the original first row in FIG. As a result, the partial product values of the original second row in FIG. 3, ie, (y4x3) ', y3x3, y2x3, y1x3 and y0x3, are advanced to the first row and calculated. Under this new rearrangement, if the higher order bits of multiplicand M1 or multiplier M2 are found as “0”, the associated partial product value may be flagged as zero without calculation. Even if some partial product values associated with the most significant bit after phase inversion become “1”, the actual calculation time is still saved because the inverted partial product values are already scheduled at the end of the calculation. The

  FIG. 5 is a schematic circuit diagram of an asynchronous signed multiplier according to an embodiment of the present invention. Referring to FIG. 5, the multiplier 500 provided by the present embodiment is an 8 × 8 multiplier, which is a signed 8-bit multiplier and a signed 8-bit multiplicand. It can function for multiplication operations on. However, the 8 × 8 multiplier 500 of the present embodiment is merely an example for explaining the present invention, and does not limit the scope of the present invention. As previously mentioned, the asynchronous signed multiplier provided by the present invention is designed to handle multiplication operations on N-bit multipliers and M-bit multiplicands. N and M in this case are positive integers greater than zero. In fact, it is easy for those skilled in the art to construct the desired multiplier according to other specifications without departing from the spirit of the invention based on the principles of the invention.

  The multiplier 500 includes a plurality of partial product generators (PPG) C1 to C8. In the present invention, the PPG number is designated by the same number of bits as the multiplier. Multiplier 500 further includes an arithmetic module 510, a leading zero bit detector 540, and a completion detector 550.

  Referring to FIG. 5, PPGs C1 to C8 generate partial product results according to the multiplier and multiplicand, and the partial product results generated by the i-th PPG are displayed as Di. The subscript i represents the multiplication of the i-th PPG device for all bits of the multiplicand and the i-th bit of the multiplier. For example, D3 means the partial product result from the third PPG C3 in which all bits of the multiplicand are multiplied by the third bit of the multiplier. Each partial product result has a plurality of partial product values, and each partial product value in the PPG is marked with a symbol “·”.

  The arithmetic module 510 includes adder modules 512, 514, 516, 518 and 520. Each adder module includes a plurality of first adders and a plurality of multiplexers, such as a first adder 528 and a multiplexer 530. In this case, each first adder receives the output from the corresponding PPG, i.e. the corresponding partial product value. For example, the first adder 528 receives the first partial product value from the PPG C1. In addition, each multiplexer has a first input end and a second input end. In this case, the first input of the multiplexer receives the output from the corresponding adder, while the second input receives the constant “0” (as shown in FIG. 6). The output from each multiplexer is sent to the next stage adder module. For example, one of the inputs of multiplexer 530 receives the output from first adder 528, while its other input receives a constant “0” and outputs from first adder 528. Is sent to the first adder 532 in the next stage adder module 516.

  FIG. 6 is a partially enlarged view showing the interconnection between the first adder and the multiplexer of the arithmetic module in FIG. Taking the first adder 528 as an example with reference to FIG. 6, the first adder 528 in the present embodiment receives each partial product value and / or output from the operation module at the final stage. It has three inputs A, B and C. The first adder 528 has a total output and a carry output, which is used to output the sum of the values received by the inputs A, B and C. Further, the carry value is output from the carry output terminal as the carry of the first adder 528 is generated.

  One of the input terminals of the multiplexer 530 and one of the input terminals of the multiplexer 531 each receive the output from the total output terminal of the first adder 528 and the output from the carry output terminal. The other end of multiplexers 530 and 531 receives the constant “0”. Multiplexers 530 and 531 each have a selection end Z, which is another end. The selection end Z is coupled to a leading zero bit detector 540 in FIG. 5, for example. In this way, the leading zero bit detector 540 can control and switch the output from the multiplexer 531.

  Referring back to FIG. 5, the arithmetic module 510 further includes a second adder module 522, a third adder module 524, and a final stage adder 526. In this case, the second adder module 522 includes a plurality of second adders for receiving output from a portion of the multiplexers in the adder modules 512, 514, 516, 518 and 520. In the present invention, the second adder module 522 and the partial product generators (PPG) C1 to C7 have the [numerical values] for seven outputs, ie, (N−1) outputs from PPG C1 to PPG C7. 1] is executed to obtain a first calculation result. However, in the case of this embodiment, N in [Expression 1] is 8.

  As the calculation of formula (1) is performed by the adder modules 512, 514, 516, 518, 520 and the second adder module 522, the leading zero bit detector 540 finds leading zero bits in either the multiplier or the multiplicand. Then, all the related outputs of the partial product are set to “0”. In this embodiment, when the leading zero bit detector 540 detects a leading zero bit in either the multiplier or the multiplicand, a control signal is generated and sent to the selection terminal Z of the multiplexer, so that the multiplexer is not operated by the first adder. The constant “0” is output directly to.

  The third adder module 524 also includes a plurality of third adders, each receiving a partial product value generated by the eighth or Nth PPG C8. The third adder module 524 and the final stage adder 526 add D8 to the first operation value, that is, add the first operation value to the partial product result generated by the PPG C8 to obtain the second operation. Get the value. This second calculated value is simply the final product value obtained by multiplying the multiplier and multiplicand.

  In this embodiment, the output from the adder 526 at the final stage is transmitted to the completion detector 550, and it is necessary to complete the detection of the second calculation value using the completion detector 550.

  From the above description, it can be seen that the present invention returns the partial product of the Nth bit in the multiplier for computation in the final stage, so that the present invention still saves computation time when performing signed multiplication. Can do.

  It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, the above specification and examples should be considered as exemplary only, with the true scope and spirit of the invention being indicated by the appended claims and equivalents thereof.

  The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

A sequential carry array multiplier is schematically shown, and the array multiplier has an 8 × 8 left-to-right (LR) architecture. Briefly referring to a carry save array multiplier, the array multiplier has an 8 × 8 left-to-right (LR) architecture. It is a graph which shows the statistical distribution of the relationship between the number of hits of a multiplier and a multiplicand, and effective bit length. It is a figure which shows the normal multiplication operation of the number with the code | symbol of 5x5 from left to right. FIG. 6 is a diagram illustrating a 5 × 5 left-to-right signed number normal multiplication operation according to an embodiment of the present invention. 1 is a schematic circuit diagram of an asynchronous signed multiplier according to an embodiment of the present invention. FIG. It is the elements on larger scale which show the interconnection of the 1st adder and multiplexer of the arithmetic module in FIG.

Explanation of symbols

100 array multiplier 104 LR adder array 108 final stage adder 120 array multiplier 500 multiplier 510 arithmetic module 512 adder module 516 adder module 522 adder module 524 adder module 526 adder 528 adder 530 multiplexer 531 Multiplexer 532 Adder 540 Leading Zero Bit Detector 550 Completion Detector

Claims (5)

An asynchronous signed multiplier for performing a signed multiplication operation on a multiplier and a multiplicand, wherein the multiplier and multiplicand have N bits and M bits, respectively, and N and M are positive integers greater than zero. And the multiplier and multiplicand are signed numbers,
N partial product generators (PPG) used to generate partial product results according to each of the multiplier and multiplicand, wherein the partial product results are denoted by Di, where Di is the i th PPG , Display partial product results by matching the timings of any number of bits of the multiplicand and the i-th number of bits of the multiplier, i is an integer equal to or less than N and equal to or greater than 1, and each of the partial product results is M Including partial product values of
A calculation module that receives the output from the PPG and that is used to execute the calculation of the following formula 1 to obtain a first calculation result;

DN is added to the first calculation result by the calculation module to obtain a second calculation result,
A partial zero value corresponding to the detected "0" bit when the leading zero bit detector is coupled to the arithmetic module and the leading zero bit detector detects a leading zero bit in either the multiplier or multiplicand Asynchronous signed multiplier whose output is set to "0" without operation on zero bits.   The asynchronous signed multiplier of claim 1, further comprising a completion detector coupled to the arithmetic module for checking the second arithmetic result. The arithmetic module further includes
A plurality of first adders each receiving a corresponding partial product value to sequentially accumulate outputs from the (N-1) th PPG, the (N-2) th PPG to the first PPG;
A plurality of multiplexers each having a first input end, a second input end and an output end, wherein the first input ends of each multiplexer each receive an output from a corresponding first adder; The second input of each multiplexer receives a constant “0”, and the multiplexer selects its first input or second input according to the output of the leading zero bit detector and couples it to its output. And the multiplexer transmits the data of the first input terminal or the second input terminal to the first adder combined by the PPG of the next stage,
A plurality of second adders each receiving an output from a portion of the multiplexer;
A plurality of third adders for receiving outputs from the Nth PPG and the first PPG;
2. An asynchronous signed adder as claimed in claim 1, comprising: a final stage adder for receiving an output from a multiplexer that processes an operation associated with an output from the first PPG and calculating a second operation value Multiplier. An algorithm for asynchronous signed multiplication suitable for performing a signed multiplication operation on a multiplier and a multiplicand, wherein the multiplier is an N-bit number and N is a positive integer greater than zero; The most significant bit of the multiplier and multiplicand is a sign bit,
(N-1) a step for acquiring a plurality of first partial product values by matching the timing of the multiplicand with a plurality of bits sequentially from the number of bits to the first number of bits;
Summing the first partial product values to obtain a first calculation result;
A step for obtaining a plurality of second partial product values by matching the timing of the multiplicand with the Nth bit number of the multiplier;
Adding the second partial product value to the first total value to obtain a second calculation result;
If a leading zero bit is detected in the multiplier or multiplicand, the partial product value associated with the “0” bit is directly set to zero without performing an operation on the “0” bit. Phase inversion of the partial product value associated with the most significant bit of the multiplier or associated with the most significant bit of the multiplicand, except for the partial product value between the most significant bit of the multiplier and the most significant bit of the multiplicand The algorithm for an asynchronous signed multiplier according to claim 4, further comprising:

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