JP2007150178A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device wherein the crystal orientation of each layer constituting a ferroelectric capacitor is properly controlled. <P>SOLUTION: The semiconductor device includes a substrate 10, an insulating layer 12 provided on the substrate, a plug 34 penetrated through the insulating layer, a first barrier layer 42 provided on the plug, a metal oxide layer 44 provided on the first barrier layer 42, a second barrier layer 46 provided on the metal oxide layer and having a prescribed orientation, a first electrode 40 provided on the second barrier layer, a ferroelectric layer 50 provided on the first electrode, and a second electrode 60 provided on the ferroelectric layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  As a ferroelectric memory, a structure in which a ferroelectric capacitor is stacked on a selection transistor is known. An insulating layer is interposed between the ferroelectric capacitor and the selection transistor, and the two are electrically connected by a plug embedded in the contact hole of the insulating layer.

In order to maximize the ferroelectric characteristics of the ferroelectric capacitor constituting the ferroelectric memory, the crystal orientation of each layer constituting the ferroelectric capacitor is extremely important.
JP 2000-277701 A

  An object of the present invention is to provide a semiconductor device in which the crystal orientation of each layer constituting a ferroelectric capacitor is well controlled, and a method for manufacturing the same.

(1) A semiconductor device according to the present invention includes:
A substrate;
An insulating layer provided above the substrate;
A plug that penetrates the insulating layer;
A first barrier layer provided above the plug;
A metal oxide layer provided above the first barrier layer;
A second barrier layer provided above the metal oxide layer and having a predetermined orientation;
A first electrode provided above the second barrier layer;
A ferroelectric layer provided above the first electrode;
And a second electrode provided above the ferroelectric layer.

  In the semiconductor device according to the present invention, a first electrode having a desired crystal orientation and a ferroelectric layer are provided on a second barrier layer having a predetermined crystal orientation. Therefore, a semiconductor device having a ferroelectric capacitor having excellent hysteresis characteristics can be provided.

  In the present invention, when a specific B layer (hereinafter referred to as “B layer”) provided above a specific A layer (hereinafter referred to as “A layer”) is referred to as “B” directly on the A layer. This includes the case where the layer is provided and the case where the B layer is provided on the A layer via another layer.

  The semiconductor device according to the present invention can further take the following aspects.

(2) In the semiconductor device according to the present invention,
The first barrier layer may include a first TiN layer and a first TiAlN layer provided on the first TiN layer.

(3) In the semiconductor device according to the present invention,
The metal oxide layer may be an aluminum oxide layer.

(4) In the semiconductor device according to the present invention,
The second barrier layer may have a (111) orientation.

(5) In the semiconductor device according to the present invention,
The second barrier layer may include a second TiN layer and a second TiAlN layer provided on the second TiN layer.

(6) A method for manufacturing a semiconductor device according to the present invention includes:
(A) forming an insulating layer above the substrate;
(B) forming a plug that penetrates the insulating layer;
(C) forming a first barrier layer on the plug;
(D) forming a metal oxide layer on the first barrier layer;
(E) exciting a plasma of ammonia gas to irradiate the surface of the metal oxide layer with the plasma;
(F) forming a second barrier layer having a predetermined orientation at least above the metal oxide layer;
(G) sequentially stacking a first electrode, a ferroelectric layer, and an upper electrode above the second barrier layer.

  According to the method for manufacturing a semiconductor device of the present invention, a barrier layer having a predetermined orientation is formed by forming a second barrier layer on the metal oxide layer after finishing the process (e). can do. The crystal orientation of the second barrier layer is reflected on the first electrode, and consequently on the ferroelectric layer formed above the first electrode. Therefore, the orientation of the ferroelectric layer can be improved by forming the second barrier layer having an orientation that matches the orientation required for the ferroelectric layer (regular arrangement of constituent atoms). As a result, a semiconductor device including a ferroelectric capacitor having excellent hysteresis characteristics can be manufactured.

  The method for manufacturing a semiconductor device according to the present invention can further take the following aspects.

(7) In the method of manufacturing a semiconductor device according to the invention,
Between the step (b) and the step (c), a step of exciting a plasma of ammonia gas and irradiating at least the surface of the insulating layer may be included.

(8) In the method for manufacturing a semiconductor device according to the present invention,
The first barrier layer includes a TiAlN layer,
The metal oxide layer formed in the step (c) can be formed by oxidizing the TiAlN layer.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings.

1. 1. First embodiment 1.1. Semiconductor Device First, a semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to the present embodiment.

  As shown in FIG. 1, the semiconductor device according to the present embodiment includes a base body 10, an insulating layer 12, a contact hole 20, a contact portion 30, and a ferroelectric capacitor 100.

  The base 10 is a semiconductor substrate (for example, a silicon substrate). A plurality of transistors (not shown) are formed on the base 10. The transistor includes an impurity region serving as a source region or a drain region, a gate insulating layer, and a gate electrode. An element isolation region (not shown) is formed between the transistors, and electrical insulation between the transistors is achieved. The semiconductor device according to the present embodiment has, for example, a 1T1C type stack structure.

The insulating layer 12 is formed on the base 10. The insulating layer 12 is formed of, for example, at least one of a silicon oxide layer (SiO ₂ layer), a silicon nitride layer (SiN layer), and a silicon nitride oxide layer (SiON layer), and may be a single layer, Multiple layers may be used.

  The contact hole 20 penetrates the insulating layer 12. A contact portion 30 having electrical conductivity is formed inside the contact hole 20.

  The contact portion 30 is formed to extend in a direction perpendicular to the surface of the base body 10 and penetrates the insulating layer 12. A transistor (either one of the source region and the drain region) of the base 10 is electrically connected to one end of the contact portion 30, and the ferroelectric capacitor 100 is electrically connected to the other end. ing. That is, the contact part 30 electrically connects the transistor and the ferroelectric capacitor 100.

  The contact portion 30 includes a contact hole 20 provided in the insulating layer 12 and a plug 34 provided in the contact hole 20. In the semiconductor device according to the present embodiment, contact portion 30 further includes a barrier layer 32 formed along the inner surface (bottom surface and side surface) of contact hole 20. The barrier layer 32 can be composed of, for example, at least one of a titanium aluminum nitride layer (TiAlN layer) and a titanium nitride layer (TiN layer). By providing the barrier layer 32, the plug 34 can be prevented from diffusing and oxidizing, and the resistance of the contact portion 30 can be reduced.

  The ferroelectric capacitor 100 is formed at least on the contact portion 30 and in a region including the contact portion 30. That is, the planar region of the ferroelectric capacitor 100 includes the plug 34 and its peripheral region (insulating layer 12) in a plan view perpendicular to the surface of the substrate 10.

  The ferroelectric capacitor 100 is formed via a first barrier layer 42, a metal oxide layer 44, and a second barrier layer 46 provided above the contact portion 30 and on the insulating layer 12 around the contact portion 30. ing. That is, a stacked body of the first barrier layer 42, the metal oxide layer 44, and the second barrier layer 46 is provided between the lower electrode 40 and the contact portion 30 and the insulating layer 12.

  The first barrier layer 42 includes a titanium nitride layer (TiN layer) and a titanium aluminum nitride layer (TiAlN layer) provided on the titanium nitride layer (TiN layer). It may be composed of at least one of a titanium nitride layer (TiN layer) or a titanium aluminum nitride layer (TiAlN layer). Further, as the second barrier layer 46, the same configuration and the same material as the first barrier layer 42 can be used. The second barrier layer 46 has a predetermined orientation, and for example, a TiN layer having a (111) orientation can be used as the second barrier layer 46. Here, the predetermined orientation refers to an orientation that can match the orientation required for the ferroelectric layer (regular arrangement of constituent atoms of the ferroelectric layer).

  The first barrier layer 42 and the second barrier layer 46 are layers having partially different orientations in the plane. Specifically, the first portions 42a and 46a located above (above) the insulating layer 12 are different from the second portions 42b and 46b located above (above) the contact portion 30. The difference between the first portions 42a and 46a and the second portions 42b and 46b will be described as an example where the first barrier layer 42 and the second barrier layer 46 are TiN layers. The predetermined orientation in the case of the TiN layer is the (111) orientation, but the ratio of the (111) orientation is different in each layer. The first portions 42a and 46a have a higher (111) orientation ratio than the second portions 42b and 46b. Furthermore, the second portion 46b is a portion having a higher (111) orientation ratio than the second portion 42b.

  As the metal oxide layer 44, for example, an aluminum oxide layer, a germanium oxide layer, a gallium oxide layer, an indium oxide layer, or the like can be used. Particularly preferred is an aluminum oxide layer. The entire metal oxide layer 44 may not be made of the same material. 2 Any layer in which a metal oxide is present on the surface in contact with the barrier layer 46 (the upper surface of the metal oxide layer 44) may be used. For example, a TiAlN layer may be subjected to surface oxidation and a thin aluminum oxide layer may be formed on the surface.

  The ferroelectric capacitor 100 is formed by sequentially laminating a lower electrode (first electrode) 42, a ferroelectric layer 50, and an upper electrode (second electrode) 46. The lower electrode 40 is formed above the contact portion 30, specifically, on the second barrier layer 46. The lower electrode 40 is electrically connected to the contact part 30. Specifically, the lower electrode 40 of the ferroelectric capacitor 100 is electrically connected to either the source region or the drain region of the transistor. In the semiconductor device according to the present embodiment, the lower electrode 40 of the ferroelectric capacitor 100 is electrically connected to the bit line through the transistor, and the upper electrode 60 of the ferroelectric capacitor 100 is electrically connected to the plate line. The gate electrode of the transistor is electrically connected to the word line.

The lower electrode 40 and the upper electrode 60 are made of, for example, Pt, Ir, Ir oxide (IrO _x ), Ru, Ru oxide (RuO _x ), SrRu composite oxide (SrRuO _x ), or the like. Each of the lower electrode 40 and the upper electrode 60 may be formed of a single layer or may be formed of a plurality of layers.

The ferroelectric layer 50 may be formed using a PZT-based ferroelectric made of an oxide containing Pb, Zr, and Ti as constituent elements. Alternatively, Pb (Zr, Ti, Nb) O ₃ (PZTN system) doped with Nb at the Ti site may be applied. Alternatively, the ferroelectric layer 50 is not limited to these materials, and for example, any of SBT, BST, BIT, and BLT systems may be applied.

  In the semiconductor device according to the present embodiment, the lower electrode 40 is formed on the second barrier layer 46 having a predetermined orientation. Therefore, the lower electrode 40 and the ferroelectric layer 50 having a desired orientation can be provided. As a result, it is possible to provide a semiconductor device that has a ferroelectric capacitor with excellent hysteresis characteristics and is miniaturized.

1.2. Semiconductor Device Manufacturing Method Next, a semiconductor device manufacturing method according to the present embodiment will be described with reference to FIGS. 2 to 10 are cross-sectional views schematically showing the manufacturing process of the semiconductor device according to the present embodiment.

  (1) First, as shown in FIG. 2, the insulating layer 12 is formed on the substrate 10. The insulating layer 12 is formed on the surface of the substrate 10 on which a plurality of transistors are formed. The insulating layer 12 can be formed by applying a known technique such as a CVD method.

  (2) Next, as shown in FIG. 3, a contact hole 20 penetrating the insulating layer 12 is formed. In that case, a photolithography technique may be applied. Specifically, a resist layer (not shown) is formed so as to open a part of the insulating layer 12, and the opening from the resist layer is etched to form the contact hole 20 penetrating the insulating layer 12. The base 10 is exposed from the contact hole 20.

  (3) Next, a contact portion 30 (see FIG. 1) is formed in the contact hole 20. In forming the contact portion 30, first, as shown in FIG. 4, a barrier layer (another barrier layer) 31 is formed along the inner surface of the contact hole 20. The barrier layer 31 can be formed by sputtering or the like. The barrier layer 31 is formed on the side surface of the contact hole 20 (end surface of the insulating layer 12) and the bottom surface of the contact hole 20 (upper surface of the base 10), and is continuous with the portion formed on the inner surface of the contact hole 20. It is also formed on the upper surface. However, the barrier layer 31 is formed so as not to fill the contact hole 20.

  (4) Next, as shown in FIG. 5, a first conductive layer 33 is formed inside the contact hole 20 and on the insulating layer 12. The first conductive layer 33 is formed so as to fill the inside of the contact hole 20 (specifically, the inner side surrounded by the barrier layer 31). In the case of forming the barrier layer 31, the first conductive layer 33 is formed on the barrier layer 31. The first conductive layer 33 can be formed by, for example, a CVD method.

  (5) Next, as shown in FIG. 6, the first conductive layer 33 is polished. In this embodiment, a part of the first conductive layer 33 and a part of the barrier layer 31 are polished and removed. That is, the first conductive layer 33 (and the barrier layer 31) is polished until the insulating layer 12 serving as a stopper is exposed. In the polishing process, a process by a chemical mechanical polishing (CMP) method can be applied. The contact part 30 can be formed by the above process.

  Next, the plasma of ammonia gas is excited, and the exposed surface of the insulating layer 12 and the plug 34 is irradiated with the plasma (hereinafter also referred to as “ammonia plasma treatment”). By this ammonia plasma treatment, the surface of the insulating layer 12 is terminated with —NH, and when the barrier layer 41 is formed in a process described later, atoms constituting the barrier layer 41 easily migrate on the surface of the insulating layer 12. Become. As a result, the constituent atoms of the barrier layer 41 are promoted to have a regular arrangement due to the self-orientation, and the barrier layer 41 having excellent crystal orientation can be formed.

  (6) Next, as shown in FIG. 7, the barrier layer 41 is formed on the upper surfaces of the insulating layer 12 and the contact portion 30 (plug 34 and barrier layer 32). The barrier layer 41 is patterned in a process described later to become the first barrier layer 42 (see FIG. 1). As the barrier layer 41, a material capable of improving the role of preventing the oxidation of the plug 34 and the adhesion between the lower electrode described later is used. The case where a TiN layer having a (111) orientation and a TiAlN layer having a (111) orientation are formed as the barrier layer 41 will be specifically described below. First, a Ti layer is formed on the exposed surfaces of the insulating layer 12 and the contact part 30. This Ti layer is a material having self-orientation properties (property of (100) orientation), but a layer having a larger (100) orientation ratio can be formed by the ammonia plasma treatment in the step (5). . Next, heat treatment is performed in a nitrogen atmosphere, the Ti layer can be nitrided, and the TiN layer can be formed. Thereby, a TiN layer having a (111) orientation can be formed. Thereafter, a TiAlN layer having a (111) orientation is formed on the TiN layer. The TiAlN layer can be formed by, for example, a sputtering method. If necessary, the surface may be planarized by CMP polishing at this stage. The (100) orientation of the Ti layer and the (111) orientation of the TiN layer have the same regularity of constituent atom arrangement. In addition, the ammonia plasma treatment in step (5) is a treatment that exerts an effect on the oxide. Therefore, the barrier layer 41 having a different (111) orientation ratio is formed between the first portion 41 a located on the insulating layer 12 and the second portion 41 b located on the contact portion 30. The second portion 41b is a portion having a lower (111) orientation ratio than the first portion 41a.

  (7) Next, as shown in FIG. 8, a metal oxide layer 43 is formed on the barrier layer 41. The metal oxide layer 43 is patterned in a process described later to become a metal oxide layer 44 (see FIG. 1). In this embodiment, the case where the metal oxide layer 43 having only the outermost surface of the aluminum oxide layer is formed as the metal oxide layer 43 will be described as an example. The metal oxide layer 43 can be formed by subjecting the TiAlN layer to surface oxidation treatment. Thereby, the metal oxide layer 43 which has an aluminum oxide layer on the surface can be formed. The TiAlN layer thus formed is a layer having a crystal orientation reflecting the crystal orientation of the barrier layer 41 located below. Further, as the metal oxide layer 43, instead of the TiAlN layer, a TiGeN layer, a TiGaN layer, a TiInN layer, and the like are formed, and then surface oxidation treatment is performed, so that a germanium oxide layer and a gallium oxide layer are formed on each outermost surface. And a layer having an indium oxide layer can be formed.

  Next, the surface of the metal oxide layer 43 is irradiated with ammonia plasma. The ammonia plasma treatment can be performed in the same manner as in the step (5). Thereby, the orientation of the layer formed on the metal oxide layer 43 in a later step can be controlled. The ammonia plasma treatment in this step is performed in order to improve the crystal orientation on the contact portion 30.

  (8) Next, as shown in FIG. 9, a barrier layer 45 is formed on the metal oxide layer 43. The barrier layer 45 is patterned in a process described later to become the second barrier layer 46 (see FIG. 1). The barrier layer 45 can be formed of the same material as the barrier layer 41 described above. Also, the formation method can be performed in the same manner as the barrier layer 41. The barrier layer 45 is located above the insulating layer 12 and includes a first portion 45a having a (111) orientation and a second portion 45b located above the contact portion 30 and having a low degree of (111) orientation. . The second portion 45b of the barrier layer 45 has a higher (111) orientation ratio than the second portion 41b of the barrier layer 41 due to the effect of the ammonia plasma treatment in the step (7).

  (9) Next, as shown in FIG. 10, the ferroelectric capacitor 100 is formed on the barrier layer 45 and on the region including the contact portion 30. Specifically, the lower electrode (first electrode) 40, the ferroelectric layer 50, and the upper electrode (second electrode) 60 are sequentially stacked to form the stacked body 101, and the stacked body 101 is patterned into a predetermined shape.

  As a method for forming the lower electrode 40, a sputtering method, a vacuum deposition method, a CVD method, or the like can be applied. As a formation method of the ferroelectric layer 50, a solution coating method (including a sol-gel method, a MOD (Metal Organic Decomposition) method, etc.), a sputtering method, a CVD method, a MOCVD (Metal Organic Chemical Vapor Deposition) method, etc. are applied. can do. The upper electrode 60 can be formed by applying the same method as the lower electrode 40. Next, for example, a resist layer R <b> 1 is formed on the stacked body 101. The resist layer R1 can be formed by applying a photolithography technique.

  (10) Next, as shown in FIG. 1, the portion of the laminate 101 that is not covered with the resist layer R1 is removed. The stack 101 can be removed by applying a known etching technique. In this step, the first barrier layer 42, the metal oxide layer 44, and the second barrier layer 46 are formed. After the multilayer body 101 is patterned to form the ferroelectric capacitor 100, an annealing process is performed in an oxygen atmosphere in order to stabilize the ferroelectric layer 50 (for example, recovery from etching damage).

  Through the above steps, the semiconductor device according to the present embodiment can be manufactured.

  In the method for manufacturing a semiconductor device according to the present embodiment, the ammonia plasma treatment is performed after the metal oxide layer 43 is formed above the contact portion 30. Therefore, the first barrier layer 42 with an improved desired orientation ratio can be formed even on the contact portion 30. Since the lower electrode 40 and the ferroelectric layer 50 are formed reflecting the orientation of the first barrier layer 42, the orientation of the first barrier layer 42 is entirely in-plane as in the present embodiment. By being able to improve, the ferroelectric layer 50 having a desired orientation can be formed. As a result, the ferroelectric capacitor 100 with good hysteresis characteristics can be formed, and a method for manufacturing a semiconductor device with improved characteristics and miniaturization can be provided.

  In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation is possible. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

1 is a cross-sectional view schematically showing a semiconductor device according to a first embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 1st Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Base | substrate, 12 ... Insulating layer, 20 ... Contact hole, 30 ... Contact part, 31, 32, 41, 45 ... Barrier layer, 33 ... First conductive layer, 34 ... Plug, 40 ... Lower electrode, 42 ... First DESCRIPTION OF SYMBOLS 1 Barrier layer, 43 ... Metal oxide layer, 44 ... Metal oxide layer (aluminum oxide layer), 46 ... Second barrier layer, 50 ... Ferroelectric layer, 60 ... Upper electrode, 100 ... Ferroelectric capacitor, 101 ... Laminated body

Claims (8)

A substrate;
An insulating layer provided above the substrate;
A plug that penetrates the insulating layer;
A first barrier layer provided above the plug;
A metal oxide layer provided above the first barrier layer;
A second barrier layer provided above the metal oxide layer and having a predetermined orientation;
A first electrode provided above the second barrier layer;
A ferroelectric layer provided above the first electrode;
And a second electrode provided above the ferroelectric layer. In claim 1,
The first barrier layer includes a first TiN layer and a first TiAlN layer provided on the first TiN layer. In claim 1 or 2,
The semiconductor device, wherein the metal oxide layer is an aluminum oxide layer. In any of claims 1 to 3,
The semiconductor device, wherein the second barrier layer has a (111) orientation. In any of claims 1 to 4,
The second barrier layer includes a second TiN layer and a second TiAlN layer provided on the second TiN layer. (A) forming an insulating layer above the substrate;
(B) forming a plug that penetrates the insulating layer;
(C) forming a first barrier layer on the plug;
(D) forming a metal oxide layer on the first barrier layer;
(E) exciting a plasma of ammonia gas to irradiate the surface of the metal oxide layer with the plasma;
(F) forming a second barrier layer having a predetermined orientation at least above the metal oxide layer;
(G) a step of sequentially stacking a first electrode, a ferroelectric layer, and an upper electrode above the second barrier layer. In claim 6,
A method for manufacturing a semiconductor device, comprising the step of exciting ammonia gas plasma and irradiating at least the surface of the insulating layer between the step (b) and the step (c). In claim 6 or 7,
The first barrier layer includes a TiAlN layer,
The method for manufacturing a semiconductor device, wherein the metal oxide layer formed in the step (c) is formed by oxidizing the TiAlN layer.

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