JP2007149917A - Field effect transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric gate FET operable at a low voltage and having a long data retention period, and to provide its manufacturing method. <P>SOLUTION: The field effect transistor comprises a semiconductor substrate 1; a gate insulating film 4 formed of a single crystal ferroelectric on the semiconductor substrate 1; a gate electrode 5 provided on the gate insulating film 4; and a source region 7 and a drain region 8 located laterally of the gate insulating film 4 and the gate electrode 5 on the semiconductor substrate 1, and involving impurities formed in a region sandwiching the gate electrode 5 as viewed in a plane. The gate insulating film 4 is composed of a single crystal ferroelectric, so that it is possible to reduce a leakage current on the gate insulating film 4. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a field effect transistor and a manufacturing method thereof.

  A field effect transistor (hereinafter, referred to as “ferroelectric gate FET”) using a ferroelectric as at least a part of a gate insulating film can be miniaturized according to a scaling law and can be operated at a low voltage. It is a non-volatile memory characterized by a point. Therefore, ferroelectric gate FETs are currently being actively researched.

  Ferroelectrics have a charge due to remanent polarization even when the power is turned off, and the direction of this polarization can be switched by the polarity of the voltage applied from the gate electrode to the ferroelectric, and thus is used for a nonvolatile memory. However, in order for the ferroelectric to have remanent polarization, it must be crystallized, and the temperature required for crystallization is generally a high temperature of 600 ° C. or higher.

  FIG. 4 is a cross-sectional view showing a conventional ferroelectric gate FET. As shown in the figure, a conventional ferroelectric gate FET includes a gate insulating film 104 provided on a P-type silicon substrate 101, a gate electrode 105 provided on the gate insulating film 104, and a P-type silicon substrate. 101 includes a source region 107 and a drain region 108 which are formed in regions located on the sides of the gate insulating film 104 and the gate electrode 105 and contain N-type impurities. The gate insulating film 104 includes a silicon oxide film 204 provided on the P-type silicon substrate 101 and a ferroelectric film 205 provided on the silicon oxide film 204 (see Patent Document 1).

In this ferroelectric gate FET, the voltage applied to the gate electrode 105 is divided by the ferroelectric film 205 and the silicon oxide film 204. The applied voltage is V, the relative dielectric constant and film thickness of the ferroelectric film 205 are ε _F and t _F , respectively, and the relative dielectric constant and film thickness of the silicon oxide film 204 are ε _I (= 4) and t _I , respectively. Then, an electric field E _F applied to the ferroelectric film 205 is as equation (1).
E _F = 1 / (t _F + ε _F t _I / ε _I ) × V (1)
The relative dielectric constant of the ferroelectric differs depending on the material, but is generally about several hundreds. In order to switch the direction of the remanent polarization of the ferroelectric, an electric field higher than the coercive electric field is required. Here, the coercive electric field is a minimum electric field necessary for reversing the polarization of the ferroelectric material, and is inherent to the ferroelectric material.

  Next, a conventional manufacturing method of the ferroelectric gate FET will be described. 5A to 5C are cross-sectional views showing a part of a conventional method for manufacturing a ferroelectric gate FET.

  First, as shown in FIG. 5A, after a silicon oxide film 204 is formed on the upper surface of a P-type silicon substrate 101 by a thermal oxidation method or the like, a ferroelectric film 205 is formed on the silicon oxide film 204 by a sputtering method or the like. Form. Next, annealing is performed at 600 ° C. or higher for the purpose of improving the remanent polarization characteristics of the ferroelectric film 205. At this time, if there is no silicon oxide film 204, the constituent elements of the ferroelectric film 205 are diffused into the P-type silicon substrate 101, and the channel characteristics are deteriorated. That is, the silicon oxide film 204 functions as a diffusion barrier.

  Next, as shown in FIG. 5B, a polysilicon layer is formed on the ferroelectric film 205, and a patterned resist 106 is formed thereon. Next, the polysilicon layer, the ferroelectric film 205, and the silicon oxide film 204 are sequentially etched using the resist 106 as a mask. Thereby, a gate electrode 105 made of polysilicon and a gate insulating film 104 are formed.

Next, as shown in FIG. 5C, after removing the resist 106, N-type impurity ions are implanted into the P-type silicon substrate 101 using the gate electrode 105 as a mask to form a source region 107 and a drain region 108. .
JP-A-6-29549

In a conventional ferroelectric gate FET, a certain thickness is required for silicon oxide to function as a diffusion barrier. On the other hand, the relative dielectric constant of silicon oxide is about two orders of magnitude smaller than that of a ferroelectric. Therefore, the second term ε _F t _I / ε _I of the denominator on the right side of Equation (1) is large. Therefore, it is necessary to increase the voltage V in order to the voltage E _F applied to the ferroelectric than coercive electric field. This is inconsistent with the trend of the semiconductor industry in which the power supply voltage is lowered with miniaturization.

  In addition, the ferroelectric gate FET manufactured by the conventional manufacturing method has a problem that the leakage current from the ferroelectric is large and the polarization charge (data) holding period is short.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a ferroelectric gate FET that can operate at a low voltage and has a long data retention period, and a method for manufacturing the same. .

  In order to solve the above problems, a field effect transistor of the present invention includes a semiconductor substrate, a gate insulating film provided on the semiconductor substrate and made of a single crystal dielectric, and a gate provided on the gate insulating film. And an impurity diffusion region formed in regions of the semiconductor substrate located on both sides of the gate insulating film and the gate electrode.

  Since the gate insulating film is composed of a single crystal dielectric, leakage current can be reduced as compared with the case where a polycrystalline dielectric is used. For this reason, for example, when the field effect transistor functions as a nonvolatile memory, it is possible to lengthen the data retention time.

  In particular, when the gate insulating film is made of a single crystal ferroelectric, the field effect transistor can be operated as a nonvolatile memory by utilizing polarization characteristics. Here, examples of the ferroelectric include bismuth titanate, bismuth lanthanum titanate, lead titanate, and strontium bismuth tantalate.

  Further, according to the field effect transistor of the present invention, all the voltages applied to the gate electrode are applied to the single crystal ferroelectric. Therefore, the operating voltage can be reduced when operating as a non-volatile memory.

  The field effect transistor manufacturing method of the present invention includes a step (a) of forming a gate insulating film on a semiconductor substrate and a step (b) of forming a gate electrode on the gate insulating film, wherein the step (a ) Includes a step (a1) of disposing single-crystal dielectric particles as the gate insulating film on the semiconductor substrate.

  This method eliminates the need for a crystallization annealing step after the gate insulating film is formed. In particular, when the dielectric particles are made of a ferroelectric, it is not necessary to provide a ferroelectric material diffusion prevention film, and almost all the voltage applied to the gate electrode is applied to the gate insulating film. . For this reason, the drive voltage can be lowered.

  In the step (a1), an electric pulse is applied to the first scanning probe to bond the dielectric particles to the first scanning probe, and the dielectric particles bonded to the first scanning probe. To the desired position on the semiconductor substrate, and to apply the electric pulse having the opposite sign to the electric pulse to the first scanning probe to place the dielectric particles on the semiconductor substrate; May be included. According to this method, the dielectric particles can be arranged at a desired position using the first scanning probe. In addition, since any size of dielectric particles can be disposed as a gate insulating film, a fine field-effect transistor can be manufactured.

  In addition, the said process (a) may further include the process of heat-processing the said semiconductor substrate at 450 degrees C or less after the said process (a1). Thereby, the adhesion between the gate insulating film and the semiconductor substrate can be improved. Since this heat treatment is performed at a temperature lower than that of the conventional crystallization annealing process, for example, when an insulating film material such as a ferroelectric is used, diffusion of the ferroelectric material to the semiconductor substrate is suppressed.

  According to the method of manufacturing a field effect transistor of the present invention, a gate insulating film made of a single crystal ferroelectric can be realized, and a diffusion barrier between the gate insulating film and the substrate is not necessary, so that low voltage operation is possible. In addition, a ferroelectric gate FET having a long data retention period can be provided.

  FIG. 1 is a cross-sectional view illustrating a field effect transistor according to an embodiment of the present invention.

  As shown in the figure, the field effect transistor of the present embodiment includes a P-type silicon substrate (semiconductor substrate) 1 and a gate insulating film 4 provided on the P-type silicon substrate 1 and made of a single crystal ferroelectric. And a gate electrode 5 made of, for example, nickel (Ni) and on the side of the gate insulating film 4 and the gate electrode 5 of the P-type silicon substrate 1. And a source region 7 containing an N-type impurity and a drain region 8 (impurity diffusion region) formed in a region sandwiching the gate electrode 5. In the field effect transistor of the present embodiment, the material of the gate insulating film 4 is composed of, for example, single crystal bismuth lanthanum titanate (hereinafter abbreviated as “BLT”). The thickness of the gate insulating film 4 is about 65 nm. The thickness of the gate electrode 5 is about 50 nm. In the P-type silicon substrate 1, a region immediately below the gate electrode 5 and sandwiched between the source region 7 and the drain region 8 is a channel region 9 in which carriers travel during operation. The width (channel length) of the channel region 9 in the carrier traveling direction is about 40 nm.

  In the field effect transistor of this embodiment, since the crystallization annealing step is not performed after the formation of the gate insulating film 4 as will be described later, diffusion of the ferroelectric material into the P-type silicon substrate 1 is suppressed. Therefore, it is not necessary to provide a diffusion barrier under the ferroelectric film. Since the diffusion barrier is not provided, almost all of the voltage applied to the gate electrode 5 can be applied to the gate insulating film 4 made of a ferroelectric. Therefore, the field effect transistor according to the present embodiment operates at a low voltage. Is possible. Further, since the gate insulating film 4 is made of a single crystal ferroelectric, the leakage current in the gate insulating film 4 is suppressed to be small, and polarization charges (data) can be held for a long time. .

  In the field effect transistor of this embodiment, the coercive voltage of the gate insulating film 4 is, for example, about 1.0 V, so that the write operation can be performed at about 1.8 V and the read operation can be performed at about 0.3 V. When the same gate voltage is applied, there is a difference in drain current between the state where data is written and the state where data is not written because the direction of remanent polarization in the gate insulating film 4 is different. In the field effect transistor of this embodiment, data can be read by detecting a difference in drain current, for example.

  Next, a method for manufacturing the field effect transistor according to this embodiment will be described. 2A to 2C are views for explaining a method of manufacturing the field effect transistor of this embodiment.

  First, as shown in FIG. 2 (a), an AFM (Atomic Force Microscope) probe 10 is brought close to a layered body 40 of BLT single crystal particles 14 having a rectangular parallelepiped spherical shape with a side of about 65 nm prepared in advance. When an electric pulse is applied to the probe 10, the BLT single crystal particles 14 have remanent polarization and are bonded to the probe 10. Next, the probe 10 to which the BLT single crystal particles 14 are bonded is moved to a desired position on the P-type silicon substrate 1, and an electric pulse having a sign opposite to that applied at the time of bonding is applied. And placed on the P-type silicon substrate 1. Next, heat treatment is performed at 450 ° C. or lower to improve the adhesion between the BLT single crystal particles 14 and the P-type silicon substrate 1. In the subsequent steps, the BLT single crystal particles 14 in close contact with the P-type silicon substrate 1 are referred to as “gate insulating film 4”. In this step, the BLT single crystal particles 14 can be arranged in an orientation in which the polarization of the BLT single crystal particles 14 appears.

  Next, as shown in FIG. 2 (b), the conductive particles having ferromagnetism prepared in advance, for example, a laminated body 50 of nickel particles 15 having a rectangular parallelepiped shape having a side of about 50 nm, the tip is made of nickel. When the AFM probe 11 coated and applied with an appropriate magnetic field is brought close, the nickel particles 15 are adhered to the probe 11 by the magnetic field action. Next, the probe 11 to which the nickel particles 15 are bonded is moved onto the gate insulating film 4, and the probe 11 is heated to 400 ° C. At this time, since the Curie temperature of nickel (the temperature at which ferromagnetism is lost) is 360 ° C., the nickel particles 15 are detached from the probe 11 and disposed on the gate insulating film 4. Thereafter, heat treatment may be performed to improve the adhesion between the nickel particles 15 and the gate insulating film 4. In the subsequent steps, the nickel particles 15 placed on the gate insulating film 4 are referred to as “gate electrodes 5”.

  Next, as shown in FIG. 2C, N-type impurity ions are implanted into the P-type silicon substrate 1 using the gate electrode 5 and the gate insulating film 4 as a mask, and the source region 7, the drain region 8, and the channel region are formed. Form. The width of the channel region in the direction perpendicular to the carrier traveling direction (channel width) is about 40 nm. As described above, the main part of the field effect transistor of this embodiment is manufactured. According to the method of the present embodiment, it is not necessary to perform a crystallization annealing step for sufficiently expressing the remanent polarization after the gate insulating film 4 is formed, so that it is not necessary to provide a ferroelectric diffusion prevention film. Therefore, in the field effect transistor of this embodiment, almost all the voltage applied to the gate electrode 5 is applied to the gate insulating film 4. Therefore, the field effect transistor according to the present embodiment can be driven at a lower voltage than the case where the diffusion prevention film is formed.

  Next, a method for producing the BLT single crystal particle 14 shown in FIG. The production of the BLT single crystal particles 14 is performed independently of the process of FIG. In this embodiment, a manufacturing method using a plasma method is adopted (for example, see “Latest Information on Nanoparticle Production, Evaluation, Application, and Equipment” published in October 2002 by CMC Publishing, Koizumi, Okuyama, and Eye Editing). ). In this method, an organic raw material liquid of BLT is sprayed into oxygen plasma and sintered instantaneously at a high temperature of 1200 ° C. or higher. Since it is produced at a high temperature, it is suitable for obtaining particles having a layered perovskite crystal structure having ferroelectricity and can be produced in a large amount. Moreover, according to this method, the average size of all particles can also be controlled.

  FIG. 3A is a surface observation photograph of a BLT single crystal particle 14 produced by the above method using a scanning electron microscope (SEM). From the figure, it was found that the BLT single crystal particles 14 produced by the above method are almost spherical and their diameters are distributed in the range of 25 to 300 nm. In the method of this embodiment, the BLT single crystal particle 14 having an appropriate diameter can be selected and placed on the P-type silicon substrate 1 using the probe 10 (see FIG. 2).

  FIG. 3B is a diagram showing an X-ray analysis (XRD) pattern of the BLT single crystal particles 14 produced by the above-described method. From the analysis shown in the figure, only the peak related to the index peculiar to the layered perovskite crystal structure of BLT was detected, and it was confirmed that the crystal structure of BLT was almost single. Furthermore, when this crystal particle was observed with a transmission electron microscope (TEM), it was confirmed that the crystal particle 14 was a single crystal.

  If a sedimentation method or a centrifugal separation method is used for the BLT single crystal particles 14 produced by the above-described method, cubic particles having a side of about 65 nm can be classified from these crystal particle groups. it can. Thus, the BLT single crystal particle 14 used for the field effect transistor of this embodiment can be produced.

  Note that the nickel particles 15 having a rectangular parallelepiped shape with a side of about 50 nm used for the field effect transistor of the present embodiment can be manufactured by using the gold particle manufacturing method described in Science (2002) 298, 2176. it can.

  In the above, an example in which single crystal BLT is used as the material of the gate insulating film 4 has been described. However, other ferroelectric single crystals such as bismuth titanate, lead titanate, and strontium bismuth tantalate are used as the gate insulating film. Even if it is used as 4, the effect is similar. Even in this case, ferroelectric crystal particles can be manufactured by the above-described manufacturing method using the plasma method.

  In addition, the field effect transistor of this embodiment can use not only a P-type silicon substrate but also an N-type silicon substrate or a substrate made of a semiconductor material other than silicon.

  The BLT single crystal particles 14 and the nickel particles 15 may be produced by a method other than the method described above.

  In the manufacturing method of the present embodiment, a field effect transistor used as a ferroelectric memory is manufactured. By using a scanning probe to place a dielectric single crystal such as a metal oxide on a semiconductor substrate, the single crystal A field effect transistor having a single-crystal dielectric film such as a metal oxide film as a gate insulating film can be manufactured. Therefore, the field effect transistor of this embodiment is not limited to a single crystal ferroelectric material, and may include a gate insulating film made of a dielectric material such as a single crystal metal oxide.

  The material of the gate electrode is not limited to Ni, and the method of this embodiment using a scanning probe can be applied as long as the material has ferromagnetism.

  The field effect transistor and the manufacturing method thereof of the present invention are useful for a nonvolatile memory transistor using a ferroelectric or the like as a material of a gate insulating film.

It is sectional drawing which shows the field effect transistor which concerns on embodiment of this invention. (A)-(c) is a figure for demonstrating the manufacturing method of the field effect transistor which concerns on embodiment of this invention. (A) is a surface observation photograph of a group of BLT single crystal particles used in the field effect transistor according to the embodiment by a scanning electron microscope (SEM), and (b) is an X of the group of BLT single crystal particles. It is a figure which shows a line analysis (XRD) pattern. It is sectional drawing which shows the conventional ferroelectric gate FET. (A)-(c) is sectional drawing which shows a part of manufacturing method of the conventional ferroelectric gate FET.

Explanation of symbols

1 P-type silicon substrate 4 Gate insulating film 5 Gate electrode 7 Source region 8 Drain region 9 Channel region 10, 11 Probe 14 BLT single crystal particle 15 Nickel particle 40, 50 Laminate

Claims (10)

A semiconductor substrate;
A gate insulating film provided on the semiconductor substrate and made of a single crystal dielectric;
A gate electrode provided on the gate insulating film;
A field effect transistor comprising an impurity diffusion region formed in a region of the semiconductor substrate located on both sides of the gate insulating film and the gate electrode.   2. The field effect transistor according to claim 1, wherein the gate insulating film is made of a single crystal ferroelectric.   The field effect transistor according to claim 1, wherein the ferroelectric is one selected from bismuth titanate, bismuth lanthanum titanate, lead titanate, and strontium bismuth tantalate. A step (a) of forming a gate insulating film on the semiconductor substrate;
And (b) forming a gate electrode on the gate insulating film,
The method (a) includes a step (a1) of disposing single-crystal dielectric particles as the gate insulating film on the semiconductor substrate.   5. The method of manufacturing a field effect transistor according to claim 4, wherein the dielectric particles are made of a ferroelectric material. The step (a1)
Applying an electrical pulse to a first scanning probe to adhere the dielectric particles to the first scanning probe;
Moving the dielectric particles adhered to the first scanning probe to a desired position on the semiconductor substrate;
5. The electric field according to claim 4, further comprising: applying an electric pulse having a sign opposite to that of the electric pulse to the first scanning probe and placing the dielectric particles on the semiconductor substrate. Effect transistor manufacturing method.   5. The method of manufacturing a field effect transistor according to claim 4, wherein the step (a) further includes a step of heat-treating the semiconductor substrate at 450 [deg.] C. or lower after the step (a1).   5. The method of manufacturing a field effect transistor according to claim 4, wherein the step (b) includes a step (b1) of disposing particles made of a conductive material on the gate insulating film as the gate electrode.   9. The method of manufacturing a field effect transistor according to claim 8, wherein the conductor material has ferromagnetism. The step (b1)
Applying a magnetic field to a second scanning probe partially coated with a ferromagnetic material to adhere ferromagnetic particles made of a conductive material to the second scanning probe;
Moving the ferromagnetic particles adhered to the second scanning probe onto the gate insulating film;
9. The field effect according to claim 8, further comprising the step of placing the ferromagnetic particles on the gate insulating film by setting the second scanning probe to be equal to or higher than the Curie temperature of the ferromagnetic particles. A method for manufacturing a transistor.