JP2007149119A - Flash eeprom system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flash EEPROM system. <P>SOLUTION: The flash EEPROM system of the present invention comprises a processor 21 and a memory system. The memory system comprises an array 33 of a nonvolatile floating gate memory cell divided into a plurality of sectors. The sectors each include a definite group of the memory cell array 33 erasable simultaneously as one unit. At least one user data section and overhead section of memory cell is provided in each sector. In response to receiving an address in a format for designating at least one magnetic disc sector from a processor, the address of at least one nonvolatile memory sector corresponding to at least one magnetic disc sector is designated. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates generally to semiconductor electrically erasable program read only memory (EEprom), and more particularly to a system with integrated flash EEprom chip circuitry.

  Computer systems typically use magnetic disks to store large amounts of data. However, disk drives have drawbacks in that they are large and they require a highly precise mechanical drive mechanism. Therefore, they are not rugged and not only have problems with reliability, but also consume considerable power. DRAM and SRAM, which are solid-state storage devices, do not have these drawbacks. However, they are quite expensive, require constant power to maintain their memory (volatile), and are expensive.

EEprom and flash EEprom are solid state storage devices as well. However, it is non-volatile and maintains its memory even after power is removed. However, normal flash EEproms have a finite lifetime in the number of write (or program) / erase times they can withstand. Typically, these devices become unreliable after 10 ² to 10 ³ write / erase cycles. Therefore, such elements are conventionally used in cases where semi-permanent data or program storage is required, and there may be certain restrictions on the need for reprogramming.
US Patent Application No. 204,175

Accordingly, it is an object of the present invention to provide a flash EEprom storage system with enhanced functionality that can withstand and maintain reliability for a significant number of write / erase cycles.
Yet another object is to provide an improved flash EEprom system that can be used as a non-volatile memory in a computer system.
It is still another object of the present invention to provide an improved flash EEprom system that can be used in place of a computer system magnetic disk drive.
It is still another object of the present invention to provide a flash EEprom system with improved erase operation.
It is still another object of the present invention to provide a flash EEprom system that can perform improved error correction.
It is yet another object of the present invention to provide a flash EEprom that can minimize stress on the flash EEprom system by improving the write operation.
It is yet another object of the present invention to provide a flash EEprom system that is improved in write operations.

  These and additional objectives are achieved by improvements in the system structure, circuitry and technology of the EEprom chip.

  One feature of the present invention is that an array of EEprom cells on a chip is organized into sectors and all cells contained in each cell are erased simultaneously. The flash EEprom memory system has one or more flash EEprom chips under the control of the controller. In the present invention, any combination of sectors between chips is selected and allowed to be erased simultaneously. This makes the system according to the present invention faster and more effective than conventional arrangements in which all conventional sectors are erased each time or one sector is erased at a time. In the present invention, any combination for erasing a sector, or any combination not selected in order to prevent further erasure in an erase operation is made possible. This feature is important in stopping the extra erasure of sectors that were initially "erased" exactly, thereby preventing unnecessary stress on the flash EEprom system. . In the present invention, it is possible to prevent all sectors from being selected for erasing by allowing all sectors in all systems not to be selected as a whole. This global reset is an immediate return of the system to the state of selecting the sector to be selected for its original erase. Yet another feature of the present invention is that selection is performed independently of a chip select signal that selects a particular chip for writing, reading or writing operations. Therefore, a chip having an EEprom chip can be selected for erasing a chip that is not included in another chip in which another read or write operation is performed.

  According to another aspect of the invention, an improved error correction circuit or technique is used that is used to correct errors arising from defective flash EEprom memory cells. One feature of the present invention is to allow mapping of defective cells at the cell level, thereby allowing replacement of defective cells with cells in the same sector. A defect pointer for connecting the defective cell to the address of the replaced cell is stored in the defect map. Each time a defective cell is accessed, its bad data is replaced with good data from an alternative cell.

  Yet another feature of the present invention is to allow defect mapping at the sector level. When the number of defective cells in one sector exceeds a certain number, the sector including the defective cell is replaced by another sector.

  An important feature of the present invention is that as soon as defective cells or defective sectors are found, they are remapped. Thus, by appropriately correcting the error correction code, errors that may occur in the system can be minimized.

  According to still another feature of the present invention, the number of writes to the flash EEprom can be minimized by providing a write cache. Thus, the flash EEprom memory is subject to less stress caused by the number of write / erase times, thereby preventing its aging. The most active data file is written to cache memory instead of flash EEprom memory. When the level of activity is reduced to a predetermined level, the data file is written from the cache memory to the flash EEprom memory. Another advantage of the present invention is increased by using faster cache memory.

  According to still another aspect of the present invention, a printed circuit board having a controller and an EEprom circuit chip for non-volatile storage is provided as computer system memory for a long period of time, but provided as an alternative to a hard disk system. is there. The printed circuit card can incorporate various other features of the present invention alone or in combination.

Still other objects, features and advantages of the present invention will be understood by the following description of preferred embodiments of the present invention with reference to the accompanying drawings.

(EEprom system)
A computer system incorporating the various features of the present invention is generally illustrated in FIG. 1A. A typical computer system has a microprocessor 21 connected to bus line 23, thereby allowing random access to main system memory 25, and at least one or more input / output devices 27 such as a keyboard, monitor, modem. And so on. Another major computer element connected to a typical computer system bus 23 is a large amount of long-term non-volatile memory 29. Typically such memory is a disk drive system with a 10 megabyte data storage capability. Data is easily retrieved and utilized in volatile memory 25 in the system and is easily replenished, altered, or modified.

  One aspect of the present invention is to change the disk drive system as described above to a semiconductor memory, in which case it is non-volatile, easy to erase and rewrite data in the memory, access speed, Don't sacrifice cost and reliability. This is accomplished by using an electrically erasable and programmable read only memory (EEprom) semiconductor circuit chip. This type of memory has the additional advantage of being very light in weight and operating power compared to driving a magnetic memory medium with a hard disk, which makes it possible to run on batteries. It can be said that it is suitable for computers.

  The entire storage device 29 comprises a memory controller 31 connected to a computer system bus 23 and an array 33 of EEprom integrated circuit chips. Data and instructions are uniquely communicated from the controller 31 to the EEprom array 33 via the serial data line 35. Similarly, data and status signals are communicated from the EEprom 33 to the controller 30 via the serial data line 37. FIG. 1A does not show other control and status circuits between the controller 31 and the EEprom array 33.

  Referring to FIG. 1B, the controller 31 is preferably formed on one integrated circuit chip. A system address and data bus 39, which is a part of the system bus 23, is connected to a system control line 41. The system control line 41 includes read, write and other normal computer system control lines. .

  The EEprom array 33 includes a plurality of EEprom integrated circuit chips 43, 45, 47, and the like. Each includes a respective chip select and enable line 49, 51, 53 from the interface circuit 40. The interface circuit 40 further functions as an interface between the circuit 57 and the serial data lines 35 and 37. Memory location addresses and data written to or read from the EEprom chips 43, 45, 47 are transmitted to the memory chips 43, 45, 47, etc. through the bus 55, the logic and register circuit 57, and the other bus 59. The

  The entire memory 29 shown in FIGS. 1A and 1B is manufactured in a memory size suitable for one printed circuit card. The various system buses 39 and 41 of FIG. 1B, along with other computer systems, are connected to the connection pins of such a card. In addition, various standard power supply voltages (not shown) are connected to the card and its components.

  For a large amount of memory, what is formed in one array 33 may not be sufficient. In such a case, an additional EEprom array can be connected to the serial data lines 35 and 37 of the control chip 31. This is preferably done by one printed circuit card, but if there is not enough space to do it, one or more EEprom arrays are placed on the second printed circuit card. And can be physically provided on the first one or provided and connected to a common controller chip 31.

(Erase memory structure)
In a system design in which accumulated data is performed as a file or block, the data needs to be periodically revised or new information inserted. Then, it may be desired to accommodate additional information by writing further on information that is no longer needed. In flash EEprom memory, memory cells must first be erased before storing information. That is, this means that an erase operation is always preceded before a write (or program) operation.

  In the conventional flash erase memory device, the erase operation has several methods, one of which is performed. For example, in the case of Intel Corporation 27F-256, CMOS, flash EEprom erases the entire chip at a time. If not all of the information in the chip should be erased, it must first be temporarily rescued. It is then written to other memory (typically RAM). The information is then restored into the non-volatile flash erase memory by reprogramming the device. This is time consuming, expensive and requires work space.

  In other devices, such as Seek Technology Inc.'s Model 48512 Flash EEprom chip, the memory is divided into blocks (or sectors) that can be separately separated and erased. However, one must be done each time. Depending on the selection of the desired sector, an erasing stage is entered and the specified area is erased. Although the need for temporary storage is eliminated, erasing various memory areas still requires time-consuming sequential work.

  In the present invention, the flash EEprom memory is divided into several sectors, in which cells contained in that sector can be erased simultaneously. Each sector is addressed separately and selectively erased. The most important feature is that several sector combinations can be selected to be erased together. This provides a faster erasure system compared to that found in the prior art of erasing each independently.

  FIG. 2 schematically illustrates several sectors selected for erasure. One flash EEprom system includes one or more flash EEprom chips, such as 201, 203, 205, for example. They are in communication with controller 31 via line 209. Typically, the controller 31 itself is in communication with a microprocessor system not shown. The memory in each flash EEprom chip is separated into sectors, and all storage cells in that sector can be erased simultaneously. For example, each sector has 512 bytes (ie, 512 × 8 cells), and one chip has 1024 sectors. Each sector is divided so as to be independently addressable, and a plurality of sectors such as 211, 213, 215, 217, etc. are selected to be erasable. As shown in FIG. 2, a selected sector can be limited to one EEprom chip or can be distributed among several chips in the system. Selected sectors will be erased simultaneously. This capability allows the memory system according to the present invention to operate faster than conventional structures.

  FIG. 3A is a block diagram illustrating a state where one or more sectors are selected or not selected for erasure in a flash EEprom (eg, chip 201 of FIG. 2). In practice, each sector, for example 211 or 213, is provided in relation to each sector, depending on the setting of the state of an erasable register such as 211, 213 or whether a tag is attached or selected by setting , Each sector 221, 223 is selected. The selection and subsequent erasing operation are performed under the control of the controller 31 (see FIG. 2). The circuit 220 is in communication with the controller 31 by a plurality of lines 209. Command information from the control is captured in circuit 220 by command register 225 via serial interface 227. Then, it is decoded by the command decoder 229, and the command decoder 229 outputs various control signals. Similarly, the address information is supplemented by the address register 231 and decoded by the address decoder 233.

  As an example, to select sector 211 for erasure, the controller sends the address of sector 211 to circuit 220. This address is decoded into line 235 and it is used in combination with the erase enable signal on enable bus 237 to set output 239 of register 221 high. As a result, the sector 211 can be continuously erased. Similarly, if sector 213 is required to be erased as well, its associated register 23 in register 223 will be set high.

  FIG. 3B shows the structure of the register 221 or 223 in more detail. The erase enable register 221 is a SET / RESET latch. The set input terminal 241 is obtained from the erase enable signal set of the bus 237 gated by the address decode line 235. Similarly, reset input 243 is derived from clearing the erase enable signal in bus 237 that is gated by address decoding in line 235. In this way, when an erase enable signal or a signal for clearing the erase enable signal is generated in all sectors, the signal is valid only for the addressed sector.

  After all sectors to be erased have been selected, the controller generates a high voltage for erasure along circuit 220, as well as line 209 when all global erase commands are represented by 251. Thus, the device will erase all selected sectors (eg, sectors 211 and 213) simultaneously. In addition to erasing the desired sector in the chip, the structure according to the invention allows the selection of sectors on different types of chips for simultaneous erasure.

  4 (1)-(11) illustrate the algorithm used in connection with the circuit 220 of FIG. 3A. 4 (1), the controller shifts the address to the erase enable register associated with the sector to be erased decoded in circuit 220. FIG. In FIG. 4 (2), the controller decodes to set the erase enable command used to latch the address decoded signal into the erase enable register of the addressed sector. This tag is for subsequent erasure of that sector. In FIG. 4 (3), if more sectors are to be tagged, all of the sectors to be erased will be tagged until (1) to FIG. Repeat the operations described in the related manner shown in (2). After all sectors to be erased are tagged, the controller initiates the erase cycle shown in FIG. 4 (4).

  An optimized erasure configuration is disclosed in a co-pending US patent application. They were filed on June 8, 1988 by Dr. Eriyaho Harari in US Patent Application No. 204,175 (Patent Document 1), which was filed concurrently, and at the same time as this application. Further, it is shown in “Multi-state EEprom read / write circuit and its technology”. The flash EEprom cell is erased by applying an erase pulse, and subsequent reading verifies that the cell is erased and in the erased state. If not, the pulse application and verification is repeated until it is verified that the cell is in the erased state. By erasing in this controlled manner, the cell is not exposed to over-erasing that would age EEprom or make programming difficult.

  Others may reach the erased state earlier when the selected sector group is in the erase cycle. Another important feature of the present invention is the ability to remove verified sectors for erasure from a selected group, thereby preventing over-erasure.

  Referring again to FIG. 4 (4), once all sectors to be erased are tagged, the controller begins an erase cycle for the group of sectors that are tagged. In FIG. 4 (5), a global command called global erase enable is shifted into the tag EEprom chip to be erased. This means that in (5) of FIG. 4, the controller increases the erase voltage (VE) by a certain value for a certain duration. The controller reduces this voltage at the end of the erase period. In (6) of FIG. 4, the controller performs read verification of the sector selected for erasure. If none of the sectors is verified in (7) of FIG. 4, the sequence shown in (5) to (7) of FIG. 4 is repeated. 4 (8) to 4 (9), if it is verified that one or more sectors are erased, they are taken from the sequence. Referring also to FIG. 3A, this lowers the erasable register by clearing the erase command in bus 237 with the address of the controller corresponding to each verified sector. The sequence shown in (5) to (10) of FIG. 4 is repeated until it is verified that the group has been erased as shown in (11) of FIG. Upon completion of that erase cycle, the controller transitions to a no-operation (NOP) instruction and the global erasable command is pulled up to protect it from erroneous erasures.

  The ability to select which sectors should be erased or not erased is as effective as which erasures are effective. As a result, those that have been erased before the sector to be erased later can be protected from being stressed by the device by being separated from the erase sequence. This will improve the reliability of the system. If a sector is bad or cannot be used for some reason, it is advantageous to skip the sector and prevent erasure in that sector. For example, if a sector is defective and there is a short circuit, it will erase more power. By skipping the erase cycle, the present invention can provide a significant system advantage in that the power required for erasing in the chip can be reduced.

  Having the ability to select sectors to be erased in the device leads to another consideration of reducing the power consumption of the system. Due to the elasticity of the erase structure in the present invention, the erase requirement can be adopted according to the power capability of the system. This may be accomplished by providing this system with software, with different erasure states, or with a basic structure with other systems. It could also cause the controller to change the amount of erasure by monitoring the voltage level in a system such as a laptop computer.

  Yet another operational capability of the system in the present invention is the ability to issue a reset command to the flash EEprom chip that clears all erase enable latches, and prevents further erase cycles from occurring. This is illustrated by the reset signal on line 261 in FIGS. 3A and 3B. By performing this operation invariably on all chips, the time to reset all erase enable registers could be shortened.

  Another additional ability is to have the ability to perform an erase operation regardless of chip select. When an erase operation is started in a certain memory chip, the controller can access other memory chips to perform reading and writing operations. In addition, it is selected that the erasing device is erasing and the address of the command for the next erasing can be stored.

(Defect mapping)
Physical defects in the memory device can cause difficult malfunctions. Data is destroyed every time it accumulates in a defective cell. In conventional memory devices, such as RAM and disks, any physical defects that occur during the manufacturing process are corrected at the factory. In RAM, a spare redundant memory cell is provided on a chip, and it is connected instead of a defective cell. When the medium is incomplete in the conventional disk drive device, it is likely to cause a defect. To solve these problems, manufacturers have devised various methods for these existing defects, and the most commonly used is sector defect mapping. In a normal disk system, the medium is divided into cylinders and sectors. A sector is a basic unit in which data is stored. A system that is divided into various sectors and marked as bad is not used in that system. This is realized by various methods. A table of defect maps is provided at a specific location on the disk to be used and is utilized via an interface controller. Further, a defective bad sector is physically given a special ID, and has an ID and a flag marker. When a defective one is addressed, the data is usually located at another alternate location. In order to request this alternative sector, an extra sector is provided at a certain interval or at a certain position apart. This reduces the capacity of the memory and provides the problem of how to provide alternative sectors.

  One important application of the present invention is to replace conventional disk storage with a system implemented by an array of flash EEprom chips. This EEprom system is preferably set to be equal to or greater than a conventional disk and can be considered a “solid disk”.

  In “disk” systems made with such solid state memory devices, consideration must be given that they can be accomplished at low cost in order to efficiently handle defects. Another important feature of the present invention is that it enables error correction so that more memory can be saved as much as possible. As a practical matter, it is to eliminate every time a defect occurs in the whole sector, for example (usually 512 bytes), by finding a defective cell for each cell. This proposal is particularly suitable for flash EEprom media. This is because the majority of errors occur as bit errors and the streams normally found on conventional disk media are not long, close defects.

  In the prior art for both RAM and magnetic disks, once the device is shipped from the factory, there is little or no means to replace the hardware error resulting from physical defects that appear after normal operation. It is. For this reason, defect correction is mainly performed by using an error correction code (ECC).

  Due to the nature of the flash EEprom device, the number of cell defects can be expected to increase gradually as the number of write / erase operations increases. The hardware errors that are accumulated through use eventually overwhelm the ECC, rendering the device unusable. One important feature of the present invention is the ability to correct a hardware error in the system whenever a hardware error occurs in the system. Also during the read operation, defective cells are found and positioned by ECC. As soon as a defective cell is identified, the controller will provide a defect mapping to replace the defective cell with a free cell that normally resides in the same sector. This dynamic hard error correction can effectively extend the lifetime of the device in addition to the normal error correction scheme.

  Another feature of the present invention is that it is suitable for an approach to error correction. The error correction code (ECC) is always used for correcting a soft error and correcting a hardware error that may occur. As soon as a hard error is detected, the defect mapping is used to replace the defective cell with a spare cell present in its same sector block. Only when the number of defective cells exceeds the capability of defect mapping for that particular sector, the entire sector is replaced like a normal disk system. With this scheme, it is possible to stop with minimal loss without compromising credibility.

  FIG. 5 illustrates a memory structure of a scheme for remapping cells. As described above, the flash EEprom memory is divided into sectors, and cells belonging to the sectors can be erased simultaneously. A typical memory structure of the sector 401 is divided into a data part 403 and a spare (or shadow) part 405. The data part 403 is a memory space that can be used by the user. The spare part 405 is further divided into a substitute part area 407 for defect data, a defect mapping area 409, a header area 411, and an ECC and another area 413. These areas contain information that can also be used by the controller to manipulate defective areas and other overhead information, such as headers and ECCs.

  Each time one defective cell is found in the sector, one good cell in the replacement part 407 of the defective data area is assigned to back up the data designated as the defective cell. Thus, even if data is erroneously stored in the defective cell, an error-free copy is stored in the backup cell. The addresses of the defective cell and the backup cell are stored in the defect pointer in the defect map 409.

  It should be understood that the user data area 403 and the spare part 405 need not be strictly distinguished. The relative size of each allocated area can be logically reallocated. Furthermore, the grouping of the various areas is mainly necessary for discussion and not physically necessary. For example, the replacement part 407 of the defect data area only indicates that the area occupied by the spare part 405 cannot be used by the user.

  In a read operation, the controller first reads the header, the defect map, and then the replacement defect data portion. Then read the actual data. It keeps track of defective cells and the position of alternative data by defect map. In order to encounter a defective cell, the controller substitutes the defective data with good data from the defective replacement cell.

  FIG. 6 illustrates read data path control in the preferred embodiment. The memory device 33 includes a plurality of flash EEprom chips under the control of the controller 31. The controller 31 itself forms part of a microprocessor system under the control of a microprocessor (not shown). In starting a sector read, the microprocessor loads an address generator 503 in the controller with an address to start the read operation. This information is loaded through the microprocessor interface port 505. The microprocessor then loads the DMA controller 507 with the starting location of the address bus to which the buffer memory or data read is to be sent. The microprocessor then loads the header information (head, cylinder, sector) into the holding register file 509. Finally, the microprocessor loads the read command to the command sequencer 511 before controlling the controller 31.

  After starting the control, the controller 31 first addresses the header of the sector and verifies that the memory is accessed at the address specified by the user. This is realized by the following sequence. The controller selects one memory chip (chip select) in the memory device 33 and shifts the address of the header area from the output of the address generator 503 to the selected memory of the memory device 33. The controller switches multiplexer 513 and shifts the read command output to memory device 33. The memory device then reads the sent address and begins sending serial data from the sector addressed to the controller. A receiver 515 in the controller receives this data and puts it in parallel form. In one embodiment, one byte (8 bits) is compiled at a time and the header information stored in the holding register file 509 by the microprocessor is compared with the received data. If the result of the comparison is correct, the correct information and the correct position are verified (verified) and the operation continues.

  Next, the controller 31 reads out the defect pointer and loads the positions of these defective addresses into the holding register file 509. This was followed by reading the controller's defective data, and the replacement for the defective data was what was written to replace the wrong bit when it was written. The replacement bits are stored in a replacement file 517 of defective data, which is accessed when the data bits are read.

  When the header matches and the loading of the defective pointer and alternate bit is complete, the controller begins shifting out the lowest address of the desired sector to be read. Data from the sector in the memory device 33 is transferred to the controller chip 31. Receiver 515 converts the data to parallel form and transfers each byte to FIFO 519, which is a temporary holder, to be sent from the controller.

  A pipeline structure is used to start the controller from the receiver 515 to the FIFO 519 to provide effective processing power when data is gated. As each data bit is received from memory, the controller continues to compare the address of the data to be sent (stored in address generator 507) with the defect pointer map (stored in register file 509). . If the match of the output of comparator 521 determines that the address is in a bad location, the bad bit from the memory received by receiver 515 is replaced with the good bit in that location. Good bits are obtained from the defect data replacement file. This is done by switching multiplexer 523 to receive good bits from the defective data replacement file instead of bad bits from receiver 515. When there is corrected data in the FIFO, it is ready to be sent to buffer memory or system memory (not shown). The data is sent from the controller FIFO 519 to the system memory by the controller DMA controller 507. The controller 507 then makes a request to gain access to the system bus, issues an address, and gates data out through the output interface 255 to the system bus. This is done by loading each byte into FIFO 519. When corrected data is loaded into the FIFO, it is also gated to ECC hardware 527 where the data file is processed by ECC.

  As described above, the data read from the memory device 33 is gated to be sent to the system via the controller 31 by the above-described method. This process continues until the last bit of the addressed data has been transferred.

  Despite previously detected defect mapping of defective cells, new hard errors may occur in the last mapping transition. As hard defect mapping permanently pushes out new defect cells, the latest hard errors that will occur during defect mapping are fully handled by the ECC. As data is gated by the controller 31, the controller gates the ECC bits into the ECC hardware 227 to determine if the stored value matches just the remaining value calculated. If it matches, the read operation is completed assuming that the data transferred to system memory is correct. However, if there is an error in the ECC register, a correction calculation is performed on the data sent to the system memory. The corrected data is then retransmitted. The method for calculating the error is performed by a normal method in both hardware and software. The ECC can calculate and locate a defective cell caused by an error. This is used by the controller 31 to update the defect map in relation to the sector where the defective cell was found. In this way, hard errors are always removed from the flash EEprom system.

  FIG. 7 illustrates write data path control in the preferred embodiment. The first part of the writing order is the same as the reading sequence already described. The microprocessor first loads the memory device 33 and the address pointer for the DMA as well as the read sequence. It loads the desired header into the address generator 503 and loads the command queue into the command sequencer 511. The command queue is loaded with the read header command first. Thereafter, control is passed to the controller 31. The controller then gates the address and command to the memory device 33 as well as the read sequence. The memory device returns the header data via the controller receiver 515. The controller compares the received header data with the expected value (stored in the holding register 509). If the result of the comparison is correct, the normal position has been verified and the sequence continues. The controller then loads the defective address pointer from the memory device 33 into the holding register file 509 and loads the replacement data into the defective data replacement file 527.

  Next, the controller starts fetching write data from system memory (not shown). The controller does this by accessing the system bus, outputs the storage or bus address, and performs a read cycle. The controller pulls data into the FIFO 601 via the input input interface 603. The controller then shifts the address of the starting sector (lowest byte address) from the address generator 503 to the selected memory device 33. This is followed by data from the FIFO 601. These data are sent through multiplexers 605 and 513 and converted to serial format before being sent to memory device 33. This sequence continues until all bytes for the write cycle are loaded into the selected memory.

  A pipeline structure is employed to provide effective processing power that is effective when data is gated from the FIFO 601 and gated to the selected memory 33. Data is gated from FIFO 601 and sent to ECC hardware 527, where the remaining values will be calculated in ECC. In the next stage, when data is being sent to the memory device via multiplexers 605 and 513, comparator 521 compares the address from address generator 503 with the address of the defective pointer in holding register file 509. When a match occurs, it indicates that a defect location is about to be written and the controller stores this bit in the defect data substitution file 517. All error bits sent to memory at the same time will be sent as zero.

  After the write cycle byte is loaded into the selected memory device, the controller issues a program command to the memory device to initiate the write cycle. The ideal structure of the write operation for the flash EEprom device is the above-referenced co-pending US Patent Application No. 204,175, one of which is a multi-state EEprom read and write circuit. And what is referred to as technology, the relevant parts of which are hereby incorporated by reference. Simply put, the controller is supplying a program (or write) voltage pulse during the write cycle. This is followed by a verify read to determine if all bits are properly programmed. If the bit is not verified, the controller repeats the program / verify cycle until all bits are programmed correctly.

  If a bit fails verification after extending a program / verify cycle, the controller will designate that bit as a defective bit and update the defect map accordingly. The update is performed dynamically as soon as a defective cell is detected. A similar operation is adopted even when the erase verify fails.

  After all bits are programmed and verified, the controller loads the next data bit from FIFO 601 and addresses the next location in the address sector. The controller then performs another program / verify sequence for the next byte. This sequence is continuously performed until the last data of the sector. Once this occurs, the shadow memory (header area) associated with the sector (see FIG. 5) is addressed and the contents of the ECC register are written into this area.

  In addition, the set of bits flagged as defective and accumulated in the defect data replacement file 516 is written to the replacement defect data location (see FIG. 5), thereby allowing good bits to be used for subsequent reading. Keep the value of. Once these data groups have been written and verified, the sector write is considered complete.

  The present invention has provisions for mapping defects in the entire sector, but after a defect exists that exceeds the defective sector mapping capability of that particular sector. A count is stored as the number of defective cells in each sector. When the number in a sector exceeds a certain amount, the controller maps that sector as a defect to another sector. The defect pointer for the associated sector will be stored in the defective sector map. The sector defect map is provided in the first defective sector when the extra area has no defect, and is provided in the sector. However, when a large number of defects occur in the data area of the sector, there is a strong possibility that the margin area also has many defects at the same time.

  For that reason, in other embodiments, it is preferable to locate the sector map in other memory held in the controller. The memory may be located in the controller hardware or in a portion of the flash EEprom remote from the memory. When a controller is given a multi-region address for access, it compares this address with a sector defect map. If a match occurs, access to the defective sector is denied, and the alternate address present in the defect map is entered, and the corresponding alternate sector is accessed instead.

  In yet another embodiment, sector remapping is performed by a microprocessor. The microprocessor looks at the incoming address and address and compares it to the sector defect map. If there is a match, it substitutes another position as a new command instead of issuing a command to the controller.

  Apart from the faster speed of solid disks, yet another advantage is that there are no mechanical parts. There is no long search time due to the rotational nature inherent in disk drive. In addition, a long synchronization time, a synchronization mark detection time, a write gap and the like are not necessary. Thus, less overhead time is required to access the location where the data to be read exists or where it should be written. These simplicity, and lack of overreaching, appear as a faster system with less overhead. In addition, the files are arranged in any desired address order in memory, and the controller only needs to know how to get the necessary data.

  Yet another feature of the present invention is that defect mapping is configured in a manner that does not need to interfere with the flow of data that is moved into or out of the sector. Data containing errors in the block is nevertheless returned and it is later corrected. By storing sequential addresses, it would be possible to obtain high speeds themselves. Furthermore, it allows the implementation of an effective pipeline structure in the read / write data path of the device.

(Write cache system)
Cache memory is typically used to speed up the system capabilities of slow access devices. For example, data access from a disk storage device is slow in a computer system. And if the data is obtained from a faster ram RAM, the speed will be faster. Typically, the RAM system portion uses a cache to temporarily hold what was most recently accessed from disk. The next time you need that data, you can get it from a faster cache instead of a slower disk. The system works well in situations where the same data is used repeatedly. This is the case in most configurations and programs because computers tend to work only in very small storage areas when running programs. Another example of caching is cheaper than usual, but to make use of a faster SRAM cache to speed up access to slow DRAM.

  Most conventional cache designs are read caches for speeding up reads from memory. In some situations, a write cache is used to speed up writing to memory. However, while being written to the cache at the same time, in the case of writing to system memory (eg, disk), data is written directly each time they occur. This is done because of concerns that files are lost when power is lost. If write data is stored only in cache memory (volatile), the loss of power means that the newly updated data is updated before the old data in system memory (non-volatile) is updated. This means that the updated file is lost from the cache memory. As these files continue to be used, the system will operate on old data. The need to write main memory each time breaks the cache mechanism for writing. In a read cache, there is no concern about this, because data that will disappear from the cache is backed up on disk.

In the present invention, the flash EEprom system is used in place of a system having a conventional disk-type storage device. However, the flash EEprom is exposed to wear due to excessive programming (erase cycles). U.S. Patent Application No. 204,175 (Patent Document 1), concurrently filed with the present invention by Sanjay Mehalopola and Dr. Eliyaho Harari Even in the improved flash EEprom memory device disclosed in this application, the endurance limit is limited to approximately 10 ⁶ program / erase cycles. If the lifetime of this apparatus is extended to 10 years, it is limited to erasing once every 5 minutes. This is a limit in normal computer use.

  In order to solve this problem, cache memory systems are used in a novel way so that they can be decoupled from withstanding numerous program / erase cycles. The primary function of the cache is used for writing to the flash EEprom memory and not for reading from the flash EEprom memory, unlike the use of a conventional cache. Instead of writing to flash EEprom memory, the data will be updated each time and the data will be run several times in the cache before being sent to the flash EEprom memory. As a result, the number of writes to the flash EEprom memory can be reduced. Furthermore, the advantage of writing mainly in faster cache memory is that the number of writes to the slower flash EEprom can be reduced and write efficiency in the overall system can be increased.

  In realizing the present invention, a relatively small cache memory is extremely effective. This helps to overcome the problem of data loss in volatile cache memory during power loss. In such a case, the cache memory must be maintained with a sufficient power supply for a sufficiently long time, and the data is packed in a non-volatile memory that is a specially reserved space in the flash EEprom memory. You can also. In the event of a power loss or power failure in this system, the write cache system is disconnected from the entire system, and the prepared rechargeable power supply is the power source for the cache system and the space prepared in the flash EEprom memory. Used only for

  FIG. 8 schematically shows a cache system 701 forming part of the controller of the device according to the invention. One side of the cache system 701 is connected to the flash EEprom memory array 33. On one side, it is connected to a microprocessor system (not shown) via a host interface 703. This cache system 708 has two memories. One is a cache memory 705 that temporarily holds a write data file. The other is a tag memory 709 for storing information related to the data file held in the cache memory 705. The memory timing / control circuit 713 controls writing of a data file from the cache memory 705 to the flash EEprom memory 33. The memory control circuit 713 is caused to respond to the power detection input 715 connected to the power supply unit of the microprocessor system via the host interface 703 and the line 717 as well as the information stored in the tag memory. Microprocessor system power degradation is detected by the memory control circuit 713, which will download all of the data files in the volatile cache memory 705 to the non-volatile flash EEprom memory 33.

  In the present invention, the flash EEprom memory array 33 is organized into sectors (typically 512 bytes in size), and all the memory cells in each sector can be erased together. Thus, each sector is considered a data file and a write operation on the memory array is performed on one or more such files.

  During the reading of a new sector in the flash EEprom memory 33, the data file is read and sent directly to the controller via the host. This file is not used to fill the cache memory 705 as was done in a normal cache system.

  When the host system has finished processing the data in the file and wishes to write it back into the flash EEprom memory 33, it accesses the cache system 701 by requesting a write cycle. The controller thereby accepts this request and operates on that cycle.

  In one embodiment of the invention, the data file is written to cache memory 705. At the same time, the other two pieces of information related to the data file are written into the tag memory 709. The first is a file pointer that defines a file present in the cache memory 705. The second is a timestamp, which tells the time of the last filed in the cache memory. Whenever the host wants to write to the flash EEprom memory 33 in this way, the data file is the one that was first actually stored in the cache memory 705 with the pointer and the time stamp in the tag memory 709.

  According to yet another embodiment of the present invention, when there is a write from the host, the controller initially either the file was already in the cache memory or the tag memory 709. Check to see if it was one of the tagged ones. If it is not tagged, it is written to the flash memory 33. On the other hand, the mark and the time stamp are written in the tag memory 709. If the file already exists in the cache memory or is tagged, it is updated in the cache memory and not written into the flash memory. Only frequently used data files are written to the flash memory by this method, while frequently used data files are captured in the cache memory.

  According to yet another embodiment of the present invention, when there is a write from the host, it is determined whether the data file is further written somewhere during a predetermined time (for example, only 5 minutes). Look and check. If not, it is written into the flash memory 33. On the other hand, the mark and the time stamp are written in the tag memory 709. If the data file was written within a predetermined time interval, it is written into the cache memory 705 and not written into the flash memory. At the same time, the indicator and time stamp are written into the tag memory 709 in the same manner as in the other embodiments. In this method as well, only rarely used data files are recorded in the flash memory, while frequently used data files are captured in the cache.

  In all embodiments, the cache memory 705 is used to be filled at any time. When the controller detects that it has reached a predetermined fully-filled state, the controller starts saving by writing into the flash memory 33 in preference to the other files in the cache memory 705. .

  In either embodiment, the cache memory 705 is always started in the direction of filling. When the controller detects that a certain filled condition has been reached, the controller writes saves of files in cache memory 705 in preference to others in flash memory 35. Start. The tag bit, which is the file indicator for these files, is then reset. It indicates that these files have been written. This creates a space for new data that is about to enter the cache memory.

  The controller is also responsible for returning the least utilized file that was moved first to the flash memory 33 to make room for new well-behaved files. In order to keep track of the level of activity for each file, the time stamp for each file is accumulated by the controller each time it is operated unless reset for new activity for that file. This timing is provided by a timer 711. At every time step (count), the controller systematically accesses the data file in the cache memory and reads the last written stamp for this data file. The controller then increments this timestamp by another time step (ie, incrementing the count by 1).

  For a file timestamp, two things happen according to the activity of the file. One possibility is that the timestamp is reset by an event that a new activity has occurred. Another possibility is that no new activity is generated for the file and the timestamp is incremented until it is removed from the cache. In fact, the maximum limit is reached when the time stamp increases indefinitely. For example, the system may increment the time stamp up to a maximum inactivity period of 5 minutes. Thus, when a data file is written to cache memory, the file timestamp is set to an initial value. Thereafter, unless the time stamp is reset to the initial value by another write update, the time stamp starts to increment while being incremented at each time step. For example, after 5 minutes of inactivity, the time stamp is incremented to the maximum end count.

  In one embodiment of maintaining a count, a bit may be shifted to a location in the shift register each time a file count increment occurs. If the file is updated (a new activity has occurred), the bit position will be set to the original position of the shift register. On the other hand, in some cases when the file is inactive, the bits will be gradually shifted towards the final shift position. The count value for each file is stored at each time step and then incremented. After each increment, the count value is compared with the master counter, the difference being the time delay in question.

  Thus, if the file is active, the added timestamp is reset to its original value every time the data file is rewritten. With this method, files that are constantly being updated will have a low stamp indicator and will be stored in cache memory until their activity is reduced. After the period of inactivity, they get the largest time stamp indicator. Unused files are gradually stored in flash memory, freeing up space in the cache memory for new, more used files. Even in the tag memory, space is made as these inactive files are moved to the flash memory.

  The space needs to be freed for new data files that are about to enter the cache memory at any time, and the controller removes some old files and stores them in the flash memory 33. Scheduling is done by a memory timing / control circuit 713 in the controller. The decision to save the file is based on various areas. The controller constantly monitors the frequency of writes in the system to see how full the cache is. If there are empty rooms, spaces, and spaces in the cache, there is no need to save them. If more room is required, the file with the fastest time stamp is moved first and stored in flash memory.

  Although the present invention has been described with respect to configuration in hardware within the controller, it should be understood that other configurations are possible. For example, the cache memory may exist anywhere in the system, or may be realized by software used in an existing microprocessor system. Such variations are within the scope of the present invention.

  The profile of how many times data has been written back to the flash memory is determined under various factors. It depends on the size of the cache memory and the frequency of writes in the system. In the case of a small cache memory system, only the most frequent files will be cached. Files that are accessed less frequently will be cached in conjunction with increasing the size of the cache memory. In the present invention, that is, in the case of using a relatively cheap and small amount of cache memory, it is preferable to use a memory having a capacity of about 1 megabyte. By not writing regularly to the most commonly used files (eg top 5%), the flash EEprom write frequency can be reduced from every millisecond to about 5 minutes per second. Let ’s go. As a result, the memory exhaustion time can be extended to be almost permanent. This improvement manifests itself as an improvement in the operating efficiency of the system during the write time.

  Realizing the time tag in the concept of the write cache has the advantage of making the write cache buffer memory relatively small. It is often used to store data files to be written, and other files are written directly to flash EEprom memory. The second feature is that the management of a certain moving data file can be automated by entering and leaving the write cache buffer because it does not require advanced knowledge of which data file is called next.

  The various aspects of the present invention described above relate to a system of flash EEprom memory arrays in which flash EEprom memory can replace conventional non-volatile mass storage devices.

  While the above-described embodiments of the various aspects of the present invention are preferred embodiments, those skilled in the art will recognize that variations thereof are possible. Accordingly, the invention should be protected within the full scope of the appended claims.

1 is a block diagram of a microprocessor system including a flash EEprom memory system according to the present invention. FIG. 1 is a block diagram illustrating a system including a number of flash EEprom memory chips and a controller chip. FIG. 1 is a schematic diagram of a flash EEprom chip system including memory sectors that are selected to be erased. FIG. 3 is a block diagram illustrating a controller circuit for realizing selective erasure of a plurality of sectors according to the present invention. 2B is a circuit diagram illustrating details of an exemplary register used to select one sector for erasure shown in FIG. 2A. FIG. 5 is a flowchart illustrating an erase sequence of a plurality of sector erase selections. 6 is a schematic diagram showing that one flash EEprom sector is divided into a data area and a spare redundant area. FIG. 5 is a block diagram illustrating a data path during a read operation using defect mapping according to the present invention. FIG. 5 is a block diagram illustrating a data control path during writing using defect mapping according to the present invention. 2 is a block diagram illustrating a write cache circuit in a controller. FIG.

Explanation of symbols

21 Microprocessor 23 System bus 25 RAM
27 I / O device 29 Bulk memory 31 Memory controller 33 EEprom array (memory)
35, 37 Serial data line 39 Data bus 40 Interface circuit 41 System control lines 43, 45, 47 EEprom chips 49, 51, 53 Chip select (enable)
57 Logic and register circuit 59 Bus 201, 203, 205 EEprom chip 209 Line 211, 213 Sector 221, 223 Register 225 Command register 227 Serial interface 229 Command decoder 231 Address register 233 Address decoder 503 Memory address generator 505 Port (μp interface)
507 DMA controller 509 holding register file 511 command sequencer 513 multiplexer 515 receiver 517 defective data replacement file 519 FIFO
521 Comparator 523 Multiplexer 525 Output interface 527 ECC hardware 601 FIFO
603 Interface 605 Multiplexer

Claims (2)

In a memory system having electrical terminals for establishing a connection with a host computer system,
A non-volatile floating gate memory cell array, wherein the array is divided into a plurality of sectors, each sector having a distinct group of memory cells that can be simultaneously erased as one unit, and storing user data A nonvolatile floating gate memory cell array that is further divided into a spare part for storing data of the spare part and the spare part;
A memory controller connected between the electrical terminals and the memory cell array to control the operation of the array, the controller comprising:
Addressing means responsive to receiving an address of one or more mass memory storage blocks via the terminal to address one or more non-volatile memory sectors, the addressing means being unusable Addressing means including means for responding to the identification of any non-volatile memory sector and means for replacing with another usable sector;
Means for reading spare portion data stored in the addressed sector;
Means for responding to spare portion data read for either reading user data from the addressed sector or writing user data to the sector;
Means for selecting a plurality of sectors for an erasing operation and simultaneously performing an erasing operation only on the selected plurality of sectors;
Including memory system. In a memory system having electrical terminals for establishing a connection with a host computer system,
A non-volatile floating gate memory cell array, wherein the array is divided into a plurality of sectors, each sector having a distinct group of memory cells that can be simultaneously erased as one unit, and storing user data A nonvolatile floating gate memory cell array that is further divided into a spare part for storing data of the spare part and the spare part;
A memory controller connected between the electrical terminals and the memory cell array to control the operation of the array, the controller comprising:
Addressing means responsive to receiving an address of one or more mass memory storage blocks via the terminal to address one or more non-volatile memory sectors, the addressing means being unusable Addressing means including means for responding to the identification of any non-volatile memory sector and means for replacing with another usable sector;
Means for reading spare portion data stored in the addressed sector, the means for reading one address of the addressed sector from the spare portion data of the addressed sector; Means for reading spare portion data including means for identifying that the desired sector has been addressed by comparing the address of the sector with the address of the read spare portion data;
Means for responding to spare portion data read for either reading user data from the addressed sector or writing user data to the sector;
Including memory system.

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