JP2007148753A - Multiprocessor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To match the transmitting order of request packets with the starting order of execution of request packets in a multiprocessor system in which at least two nodes of a plurality of nodes connected by a loop-shaped communication path are configured of processors, and data communication between nodes can be performed by transmitting a packet onto the communication path from a transmitting source node toward a transmitting destination node. <P>SOLUTION: Each node stores, when a request packet showing a certain processing request is transmitted to a transmitting destination node, information showing the transmitting destination node, and prohibits transmission of a new request packet to the transmitting destination node until a response packet showing the response to the processing request is received from the transmitting destination node. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  In the present invention, at least two or more nodes among a plurality of nodes connected by a loop communication path are configured by a processor, and a packet is transmitted from the transmission source node to the transmission destination node on the communication path. The present invention relates to a multiprocessor system capable of performing data communication between nodes by sending it out.

  A multiprocessor system uses a communication path (also referred to as a “loop bus” or “ring bus”) that connects each processor as a node in a loop as a communication path for performing data communication between a plurality of processors. (For example, refer to Patent Documents 1 and 2).

Japanese Patent Laid-Open No. 9-91262 JP 2001-125875 A

  However, there is a problem described below in data communication between nodes when a loop bus is used.

  12 and 13 are explanatory diagrams showing problems in data communication between nodes when a loop bus is used.

  FIG. 12 and FIG. 13 show a case where three nodes of node 1 to node 3 are connected via a loop bus for easy explanation.

  An example will be described in which a packet indicating three requests in succession (hereinafter referred to as “request packet”) is transmitted from the node 1 to the node 2 as an example.

  Here, in the present specification and drawings, a request packet to be transmitted is described as [RD-Req # 1: 12], and a packet indicating a response to the response (hereinafter referred to as “response”). Packet)) is described as [RD-Rsp # 1: 21]. “RD” before “−” indicates the type of request, “RD” for a read request, and “WR” for a write request. “Req # 1: 12” after “−” indicates the first request from the node 1 to the node 2. Similarly, “Rsp # 1: 21” indicates the first response from the node 2 to the node 1. Of “Req # 1: 12”, “: 12” indicates that the transmission source is the node 1 and the transmission destination is the node 2, and “Req # 1” is the first request transmitted from the node 1. It shows that there is. Similarly, of “Rsp # 1: 21”, “: 21” indicates that the transmission source is the node 2 and the transmission destination is the node 1, and “Rsp # 1” is the first response transmitted from the node 2. It is shown that.

  In FIG. 12 and FIG. 13, specifically, the node 1 transmits a read request [RD-Req # 1: 12] to the node 2 as three request packets, and sends the second request. A write request [WR-Req # 2: 12] is transmitted as a packet, and a read request [RD-Req # 3: 12] is transmitted as a third request packet.

  FIGS. 12 and 13 show eight stages of operation states. Each operation state indicates a state where a packet has arrived at each node.

  First, in the operation state 1, three request packets are generated in the node 1, and the first request packet [RD-Req # 1: 12] is in a transmission waiting state.

  Next, in the operation state 2, the first request packet [RD-Req # 1: 12] is transmitted from the node 1 to the node 2, and the first request packet transmitted from the node 1 [ RD-Req # 1: 12] arrives. Then, in the node 1, the second request packet [WR-Req # 2: 12] enters a transmission waiting state. Also, the node 2 receives the first request packet [RD-Req # 1: 12] that has arrived, and executes the corresponding processing.

  In the operation state 3, the second request packet [WR-Req # 2: 12] is sent from the node 1 to the node 2, and the second request packet [WR] sent from the node 1 is sent to the node 2. -Req # 2: 12] arrives. In the node 1, the third request packet [RD-Req # 3: 12] is in a transmission waiting state.

  However, at this time, the process corresponding to the first request packet [RD-Req # 1: 12] is being executed in the node 2, and the second request packet [WR-Req # 2: 12] is received. Therefore, the corresponding process cannot be executed.

  Therefore, in the next operation state 4, in the node 2, the second request packet [WR-Req # 2: 12] is sent to the node 3 as it is, and the second request packet sent from the node 2 is sent to the node 3. A request packet [WR-Req # 2: 12] arrives.

  In the operation state 4, the third request packet [RD-Req # 3: 12] is sent from the node 1 to the node 2, and the third request packet [RD-RD] sent from the node 1 is sent to the node 2. -Req # 3: 12] arrives.

  At this time, the first request packet [RD-Req # 1: 12] being executed in the operation state 3 has ended, and a response packet [RD-Rsp # 1: indicating a response to the first request packet]. 21] is generated and the transmission wait state occurs, the node 2 receives the arrived third request packet [RD-Req # 3: 12] and executes the corresponding processing.

  Next, in the operation state 5, the first response packet [RD-Rsp # 1: 21] is transmitted from the node 2 to the node 3, and the first response packet transmitted from the node 2 is transmitted to the node 3. [RD-Rsp # 1: 21] arrives. Further, the second request packet [WR-Req # 2: 12] arriving in the operation state 4 is transmitted from the node 3 to the node 1, and the second request packet transmitted from the node 3 is transmitted to the node 1. [WR-Req # 2: 12] arrives.

  In the operation state 6, the second request packet [WR-Req # 2: 12] that arrived in the operation state 5 is sent from the node 1 to the node 2, and is sent to the node 2 from the node 1. The second request packet [WR-Req # 2: 12] arrives.

  Also, a response packet [RD-Rsp # 3: 21] corresponding to the third request packet waiting for transmission is sent from node 2 to node 3, and 3 sent from node 2 to node 3. The second response packet [RD-Rsp # 3: 21] arrives. Then, the node 2 receives the arrived second request packet [WR-Req # 2: 12], executes a corresponding process, and responds to the second request packet [WR-Rsp # 2]. : 21] occurs, and the transmission is awaited.

  In addition, the first response packet [RD-Rsp # 1: 21] that arrives in the operation state 5 is sent from the node 3 to the node 1, and the first response packet sent from the node 3 is sent to the node 1. [RD-Rsp # 1: 21] arrives.

  Then, in the operation state 7, the second response packet [WR-Rsp # 2: 21] is sent from the node 2 to the node 3, and the second response packet sent from the node 2 to the node 3 [ WR-Rsp # 2: 21] arrives.

  Also, the third response packet [RD-Rsp # 3: 21] that arrived in the operation state 6 is sent from the node 3 to the node 1, and the third response sent from the node 3 is sent to the node 1. The packet [RD-Rsp # 3: 21] arrives.

  In the operation state 8, the second response packet [WR-Rsp # 2: 21] that arrived in the operation state 7 is sent from the node 3 to the node 1, and 2 sent from the node 3 to the node 1. The second response packet [WR-Rsp # 2: 21] arrives.

  As can be seen from the operation description described above, the request packet received and executed by the node 2 is the first request packet [RD-Req # 1: 12], the third request packet [WR-Req # 3: 12] The order of the second request packet [RD-Req # 3: 12] may be different from the order of transmission.

  As described above, if the order in which request packets are sent out and the order in which request packets are executed are different, problems may occur when, for example, processes that must follow the order of operations are executed in order. is there. For this reason, as described above, it is desirable that the transmission order of request packets and the start order of execution of request packets do not differ.

  Also, even when request packets are sent in order from one node to a plurality of other nodes, it is desirable that the order in which request packets are sent and the order in which request packets are executed match, regardless of the node. .

  The present invention has been made to solve the above-described problem, and at least two or more nodes among a plurality of nodes connected by a loop communication path are configured by a processor. In a multiprocessor system capable of data communication between nodes by sending packets to the destination node on the communication path, the order in which request packets are sent and the order in which request packets are started are matched. The purpose is to provide technology.

In order to solve at least a part of the above problems, the present invention provides:
Among the plurality of nodes connected by a loop communication path, at least two or more nodes are configured by a processor, and by sending a packet on the communication path from the transmission source node to the transmission destination node A multiprocessor system capable of performing data communication between nodes,
When each node transmits a request packet indicating a request for a process to the destination node, each node stores information indicating the destination node, and the process from the destination node Prohibit sending a new request packet to the destination node until receiving a response packet indicating a response to the request;
It is characterized by that.

  According to the above configuration, the request packet transmission order and the request packet execution start order can be matched.

Each of the nodes is
In order to store the information indicating the destination node, it is preferable to include a plurality of storage units smaller than (total number of nodes −1).

  Even with the above configuration, it is possible to maintain the same processing performance as when the storage units (total number of nodes−1) are provided.

  Further, the information indicating the destination node may be composed of a transmitted request packet and a flag indicating that the transmitted request packet has been transmitted.

  In the above case, for example, by using a transmission buffer for storing request packets waiting to be transmitted, the transmitted request packets are stored in the transmission buffer until the corresponding response packet is received after transmission. In this case, it can be easily realized by preparing a storage unit with a small capacity for setting the transmitted flag.

  The multiprocessor system can be integrated on a single semiconductor substrate.

  The present invention can be configured as various image processing apparatuses including the multiprocessor system in addition to the configuration as the multiprocessor system. In addition, the present invention is not limited to the above-described aspects of the device invention, and can also be realized by a method invention aspect such as a data communication method. It should be noted that the various additional elements described above can also be applied in the embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in the following order based on examples.
A. Example:
A1. Multiprocessor system configuration:
A2. Configuration and operation of communication controller:
A3. Operation of the transmission / reception controller:
A4. Specific example of communication operation:
A4.1. Example 1:
A4.2. Example 2:
A5. Effects of the embodiment:
B. Variation:

A. Example:
A1. Multiprocessor system configuration:
FIG. 1 is an explanatory diagram showing a schematic configuration as an embodiment of the multiprocessor system of the present invention. The multiprocessor system MPS includes three processors 20A to 20C as first to fifth nodes (indicated as “node 1” to “node 5” in the figure) connected via the communication path 10. A memory controller 20D and an I / O interface 20E are provided. The multiprocessor system MPS is a microprocessor in which each component is integrated on one semiconductor substrate.

  The processors 20A to 20C as first to third nodes mean units including peripheral circuits such as a cache memory, a ROM, a RAM, and a communication control unit in addition to the CPU. Similarly, the memory controller 20D as the fourth node and the I / O interface as the fifth node mean units including peripheral circuits such as a communication control unit.

  In the following description, the processors 20A to 20C as the first to third nodes, the memory controller 20D as the fourth node, and the I / O interface as the fifth node are respectively connected to the loop communication path 10. In the following description, the reference numerals of the first to fifth nodes are 20A to 20E.

  The communication path 10 is a loop by sequentially connecting the inputs and outputs of the communication control units (indicated as “RBC” in the drawing) 22A to 22E included in each of the first to fifth nodes 20A to 20E. It is formed in a shape. And between each node 20A-20E, while receiving the data which show predetermined | prescribed communication content from the input of a communication control part via the communication control part 22A-22E connected to the loop-shaped communication path 10, respectively. By transmitting from the output of the communication control unit and transmitting only in one direction, mutual communication is executed.

  The predetermined communication content includes a write request message for writing data to a destination node, a read request message for reading data from a destination device, a response message for these request messages, and the like. And the data transmitted / received between each node are comprised as what is called a packet.

  FIG. 2 is an explanatory diagram showing a data structure of a packet transmitted / received between the nodes.

  As shown in FIG. 2, a packet transmitted via the communication path 10 has a fixed length of 64 bits, and is roughly divided into a header part of the first half 32 bits and a payload part of the second half 32 bits. Composed.

  The header part further comprises a control information part of the first 16 bits and an address part of the second 16 bits. The control information part includes, in order from the top, a field indicating the type of communication content (read request message, write request message, etc.) (indicated as “TYPE” in the figure), and a field indicating data size (in the figure, “Dsize”). ), A field indicating the transmission destination (destination) ID (denoted as “DID” in the figure), and a field indicating the transmission source ID (denoted as “SID” in the figure). Is composed of a field indicating the address of a communication memory area secured in a memory (not shown) for writing data to be written to the destination device and data to be read from the destination device.

  The payload part is a field for storing communication data to be transmitted and received in all 32 bits.

  Here, the communication path 10 includes two communication lines for transmitting the packet and two lines for transmitting 2-bit state control data indicating the state of data transferred in parallel by the 32 communication lines. The communication wiring is composed of a total of 34 communication wirings.

  Accordingly, the communication control units 22A to 22E of the nodes 20A to 20E receive the 2-bit status control data and the 32-bit data among the 64-bit data constituting one packet in one cycle of the system clock. Parallel transfer is possible. That is, when viewed from the communication control unit of a certain node, the 32-bit header portion and 32-bit payload portion of the 64-bit packet are alternately transmitted from the communication control portion of the preceding node every cycle. It will be. In the following description, a bit corresponding to 2-bit status control data is referred to as a “status control bit”, and a bit corresponding to 32-bit data is referred to as a “packet bit”.

  Here, one of the two status control bits is a bit (H) indicating whether the data of the 32-bit packet bits in the same cycle is data representing the header portion or data representing the payload portion. Bit).

  Specifically, for example, when the H bit is “1”, it indicates that the packet bit data in the same cycle is data representing the header portion, and when the H bit is “0”, It indicates that the packet bit data in the same cycle is not data representing the header portion, that is, data representing the payload portion.

  Therefore, when viewed from the communication control unit of a certain node, “1” and “0” are alternately transmitted as the H bit every cycle of the system clock from the communication control unit of the preceding node.

  The other 1 bit of the 2 state control bits is a bit (V bit) indicating whether or not the data of the 32-bit packet bit in the same cycle is data constituting an empty packet.

  Specifically, for example, when the V bit is “0”, it indicates that the 32-bit packet bit data in the same cycle is data constituting an empty packet, and the V bit is “1”. Indicates that the data of 32-bit packet bits in the same cycle is not data constituting an empty packet but data constituting a normal packet. Note that the normal packet means a packet in which control information such as a transmission destination ID is stored in the header portion and communication data corresponding to communication contents is stored in the payload portion.

  In this embodiment, each functional block such as a processor, a memory controller, and an I / O interface constituting a multiprocessor is described as a node. However, a communication control unit provided in each block is regarded as a node. Is also possible.

A2. Configuration and operation of communication controller:
FIG. 3 is an explanatory diagram illustrating a configuration example of the communication control unit provided in the node. In FIG. 3, a configuration example of the communication control unit 22A of the first node 20A is shown on behalf of the communication control units 22A to 22E of each node, but the communication control units 22B to 22E of other nodes are also illustrated. Basically the same configuration.

  The communication control unit 22A includes an input register 221, an output register 222, a transmission / reception control unit 223, a transmitted flag unit 224, a transmission buffer 225, a reception data buffer 226, and a processor I / F control unit 227. I have.

  As will be described later, the transmission buffer 225 includes a plurality of transmission registers that store packets requested to be transmitted from the processor I / F via the processor I / F control unit 227. Specifically, the number of transmission registers is set to “3”, which is smaller than a value “4” obtained by subtracting the number of nodes from the total number of nodes connected to the communication path 10, and the three registers 225A to 225C. It has.

  As will be described later, the reception buffer 226 includes one reception register 226A that stores packets input from the input register 221 via the transmission / reception control unit 223. However, a plurality of reception registers may be provided.

  The processor I / F control unit 227 controls delivery of a packet to be transmitted via the communication path 10 and a packet received via the communication path 10, which is executed with a processor I / F (not shown). To do. For example, data indicating a packet requested to be transmitted from a processor I / F (not shown) (for example, a write request packet, a read request packet, etc.) is empty among the three transmission registers 225A to 225C prepared in the transmission buffer 225. If there is no free register, the program waits until a free register is generated and then writes to that register. When new data is written in the reception register 226A prepared in the reception buffer 226, the data is transferred to the processor I / F.

  Note that the communication control unit 22A in this example is a communication control unit provided in the node 20A as a processor, and thus includes a processor I / F control unit 227 that controls data exchange with the processor I / F. However, in the case of the node 20D as a memory controller and the node 20E as an I / O interface, an I / F control unit that appropriately controls data exchange with the corresponding I / F is provided. .

  The input register 221 is a register having a storage area with the number of bits equal to the 34-bit wiring width of the communication path 10 connected to the input side of the communication control unit. Similarly, the output register 222 is a register having a storage area with the number of bits equal to the 34-bit wiring width of the communication path 10 connected to the output side of the communication control unit.

  The input register 221 writes 34-bit data transmitted from the previous node via the communication path 10 on the input side at the write timing of each cycle of the system clock SCK. Similarly, the output register 222 writes 34-bit data output from the transmission / reception control unit 223 at the same writing timing of each cycle of the system clock SCK as the input register 221.

  Therefore, the communication control unit 22A receives and transmits one packet for every two cycles of the system clock. Specifically, in the input register 221, one packet is received in the first cycle in which the packet header portion is written and in the second cycle in which the packet payload portion is written. The output register 222 will be described based on the first and second cycles in the input register 221. The second cycle in which the header portion of the packet is written with a delay of one cycle with respect to the input register 221, and the payload portion of the packet is One packet is transmitted in the first cycle to be written. In the following description, the cycle in which the packet header portion is written in the input register 221 will be described as the first cycle, and the second cycle in which the packet payload portion is written.

  The transmission / reception control unit 223 operates as described in detail later to control reception of packets addressed to itself, transfer of packets not addressed to itself, and transmission of untransmitted packets.

  Specifically, the transmission / reception control unit 223 determines whether the packet is addressed to itself based on the destination described in the header part written in the input register 221 in the first cycle, and is not a packet addressed to itself. In this case, the 64-bit packet written to the input register 221 in the first cycle and the second cycle is output to the output register 222 as it is, and the second cycle and the first cycle shifted by one cycle are output. To write to the output register 222.

  On the other hand, if the packet is addressed to itself, the 64-bit packet written in the input register 221 in the first cycle and the second cycle is output to the reception buffer 226, and the second cycle is shifted by one cycle. In the first cycle, the data is written in the reception register 226A of the reception buffer 226.

  In addition, when the packet written in the input register 221 is a packet addressed to itself or an empty packet, the transmission / reception control unit 223 determines whether an untransmitted packet written in the three transmission registers 225A to 225C of the transmission buffer 225 is received. Of these, the oldest packet is written to the output register 222 in the second cycle and the first cycle shifted by one cycle. Note that the three transmitted flags 224A to 224C prepared in the transmitted flag section 224 are provided corresponding to the three transmission registers 225A to 225C, for example, packets written in the corresponding registers, respectively. Is set to “1” when it has been transmitted, and is reset to “0” when it has not been transmitted. Therefore, the presence / absence of an untransmitted packet can be determined by examining the state of the transmitted flag.

A3. Operation of the transmission / reception controller:
As will be described below, the transmission / reception control unit 223 controls reception of packets addressed to itself, transfer of packets not addressed to itself, and transmission of untransmitted packets.

  4 and 5 are explanatory diagrams showing a procedure of transmission / reception control executed by the transmission / reception control unit.

  When the transmission / reception control unit 223 starts operation, first, the transmission registers 225A to 225C of the transmission buffer 225, the reception register 226A of the reception buffer 226, and the transmitted flags 224A to 224C of the flag unit 224 are cleared (initialized) ( Step S102).

  Then, packet arrival monitoring is started (step S104). The arrival of the packet can be determined by monitoring the state of the H bit among the state control bits written in the input register 221 in the first cycle. For example, the H bit in the first cycle is “1” indicating that the packet bit data in the same cycle is data representing the header portion, and the H bit in the second cycle is “0”. Therefore, the arrival of the packet can be monitored by determining whether the H bit is “1” or “0”.

  If the packet has arrived (step S104: YES), it is determined whether the arrived packet is an empty packet (step S106). An empty packet can be determined by monitoring the state of the V bit among the state control bits written to the input register 221 in the first cycle. For example, the V bit is “0” when the packet bit data in the same cycle indicates data constituting an empty packet, and the packet bit data in the same cycle constitutes a normal packet. Since it is “1” when indicating that it is data, it is possible to monitor an empty packet by monitoring whether the V bit is “0” or “1”.

  If the arrived packet is not an empty packet (step S106: NO), the processing after step S130 is executed as described later.

  On the other hand, if the arrived packet is an empty packet (step S106: YES), it is determined whether there is untransmitted data (step S110). The presence / absence of untransmitted data can be determined by examining the states of the transmitted flags 224A to 224C of the transmitted flag section 224. For example, the transmitted flags 224A to 224C are set to “1” when the data written in the corresponding transmission registers 225A to 225C have been transmitted, and cleared to “0” when the data has not been transmitted. Therefore, it can be determined by checking whether the transmitted flags 224A to 224C are “1” or “0”.

  If there is no untransmitted data (step S110: NO), data representing an empty packet is output to the output register 222 and written to the output register 222, thereby transmitting the empty packet (step S112). Then, returning to step S104, the arrival of the next packet is monitored.

  On the other hand, if there is untransmitted data (step S110: YES), it is determined whether there is data that can be transmitted (step S114). Whether there is data that can be transmitted can be determined by checking whether the destination of the untransmitted data is the same as the destination of the transmitted data. Specifically, when the destination is the same as the transmitted data. It is determined that transmission is not possible, and if the destination is different, it is determined that transmission is possible.

  If there is no data that can be transmitted (step S114: NO), the process returns to step S112 to transmit an empty packet to another node, and then returns to step S104 to monitor the arrival of the next packet.

  On the other hand, if there is data that can be transmitted (step S114: YES), the oldest data that has been written to the transmission register is selected from the untransmitted data (step S116). This selection can be easily performed by storing the order of writing to the three transmission registers 225A to 225C, for example. Alternatively, it is easily possible by using a FIFO-type register.

  Then, the selected untransmitted data is output to the output register 222 and written to the output register 222, so that the packet represented by the data is transmitted to the destination described in the header part (step S118).

  Further, it is determined whether or not the packet represented by the transmitted data is a response packet to the request packet transmitted from the transmission destination (step S120). Whether or not it is a response packet can be determined by examining the description of the field (TYP) indicating the communication content of the header part.

  If the packet representing the transmitted data is a response packet (step S124: YES), the transmission register in which the transmitted data is stored (written) is released (step S124). Then, returning to step S104, the arrival of the next packet is monitored.

  On the other hand, if the packet representing the transmitted data is not a response packet (step S124: NO), the transmitted flag corresponding to the transmission register in which the transmitted data is stored is set to “1” (step S126). Then, returning to step S104, the arrival of the next packet is monitored.

  By the way, when the arrived packet is not an empty packet (step S106: NO), it is further determined whether or not the destination of the packet is addressed to itself (step S130). The destination can be determined by checking whether or not the description of the field (DID) indicating the transmission destination ID of the header part constituting the arrived packet is addressed to itself.

  If the arrived packet is not addressed to itself (step S130: NO), the packet bit data written in the input register 221 in the first cycle and the input register 221 in the second cycle after one cycle are written. The packet bit data to be output is output to the output register 222 and written to the output register 222, whereby the packet written to the input register 221 is transferred to another node (step S132). Then, returning to step S104, the arrival of the next packet is monitored.

  On the other hand, when the arrived packet is a packet addressed to itself (step S130: YES), it is determined whether or not the packet is a write response (WR response) packet (step S134). Whether or not the packet is a write response packet can be determined by examining the description of the field (TYP) indicating the communication content of the header portion.

  When the arrived packet is a write response packet (step S134: YES), among the three transmission registers 225A to 225C of the transmission buffer 225, the transmission register storing the corresponding write request packet is released, Of the three transmitted flags 224A to 224C of the transmitted flag section 224, the transmitted flag set corresponding to the transmission register is cleared (step S136). And it returns to step S110 and performs the process of step S110-S126.

  On the other hand, if the arrived packet is not a write response packet (step S134: NO), it is determined whether the reception register 226A of the reception buffer 226 is open and can be received (step S138).

  If the reception register 226A is not open and cannot be received (step S138: NO), the process returns to step S132, and after the packet written in the input register 221 is transferred to another node Returning to step S104, the arrival of the next packet is monitored.

  On the other hand, when the reception register 226A is opened and reception is possible (step S138: YES), the packet bit data written to the input register 221 in the first cycle and the second cycle after one cycle. The packet bit data written to the input register 221 is output to the reception buffer 226 to update the reception register 226A and to the processor I / F via the processor I / F control unit 227. The reception is notified (step S140).

  Then, it is determined whether or not the received packet is a write request (WR request) packet (step S142). It is possible to determine whether the packet is a write request packet by checking the description of the field (TYP) indicating the communication content of the header part.

  If the received packet is a write request packet (step S142: YES), data representing the write response packet is output to the output register 222 and written to the output register 222, thereby writing the write response packet. Transmission is performed toward the transmission source of the request packet (step S144). Then, returning to step S104, the arrival of the next packet is monitored.

  On the other hand, if the received packet is not a write request packet (step S142: NO), it is further determined whether or not the received packet is a read response (RD response) packet (step S146). Whether or not the packet is a read response packet can be determined by examining the description of the field (TYP) indicating the communication content in the header part.

  When the received packet is a read response packet (step S146: YES), among the three transmission registers 225A to 225C of the transmission buffer 225, the transmission register storing the corresponding read request packet is released, Of the three transmitted flags 224A to 224C of the transmitted flag section 224, the transmitted flag set corresponding to the transmission register is cleared (step S148). And it returns to step S110 and performs the process of step S110-S126.

  On the other hand, when the arrived packet is not a read response packet (step S146: NO), the process returns to step S110, and the processes of steps S110 to S126 are executed.

  As described above, the transmission / reception control unit 223 controls reception of packets addressed to itself, transfer of packets not addressed to itself, and transmission of untransmitted packets.

A4. Specific example of communication operation:
Below, the communication operation performed between each node 20A-20E via the communication path 10 is demonstrated using a specific example. For ease of explanation, the configuration shown in FIG. 1 is omitted, and a description will be given assuming that only three nodes, node 1 to node 3, out of the five nodes are shown.

  Similarly to FIG. 12 and FIG. 13 described in “Problems to be Solved by the Invention”, a request packet to be transmitted is described as [RD-Req # 1: 12]. A response packet to be responded is described as [RD-Rsp # 1: 21].

  Specific example 1 will be described using an example in which three request packets are transmitted from node 1 to node 2 with reference to FIGS. Specific example 2 is an example in which two request packets are transmitted from node 1 to node 2 and one request packet is transmitted from node 1 to node 3 with reference to FIGS. 10 and 11. Explained.

  6 to 9 show ten stages of operating states, and FIGS. 10 and 11 show six stages of operating states. As described above, each node has a system clock. Since one packet is transmitted and received every two cycles, each operation state is a state that changes in units of a system clock of two cycles in order from the first operation state (state 1), and a packet arrives at each node Will be shown.

  In addition, when there is no need to distinguish between communication contents such as a write request packet, a read request packet, a write response packet, and a read response packet, these may be simply referred to as “request packet” or “response packet”. .

A4.1. Example 1:
6 to 9 are explanatory diagrams showing a specific example 1 of the communication operation executed between the nodes.

  First, in the first operation state 1, packets [RD-Req # 1: 12], [WR-Req # 2: 12], [RD-Req # 3: 12] are stored in the transmission registers 225A to 225C of the node 1. The three request packets are stored in order. Since these three request packets are untransmitted packets, all the transmitted flags 224A to 224C corresponding to the respective transmission registers 225A to 225C are in a clear state.

  Although not shown, each node transmits an empty packet to the next node, and the empty packet arrives at the next node. In the description of Specific Example 1 and Specific Example 2, the illustration and description of empty packet transmission and arrival are omitted unless particularly required.

  In the figure, the correspondence between the transmission register and the transmitted flag is shown by connecting the rectangular figure indicating the transmission register and the rectangular figure indicating the transmitted flag with a line. In addition, the clear state of the transmitted flag is indicated by making the symbol of the rectangular figure blank, and the set state of the transmitted flag is indicated by hatching the symbol of the rectangular figure.

  Then, in the operation state 2, in the node 1, the request packet [RD-Req # 1: 12] stored in the first transmission register 225A is transmitted to the node 2, and the corresponding transmitted flag 224A is set. The At this time, the first request packet [RD-Req # 1: 12] transmitted from the node 1 arrives at the node 2. The packet arriving at the node 2 is received because it is addressed to itself, and stored in a reception buffer (not shown). Then, the corresponding process is executed.

  Next, in the operation state 3, since the node 1 has not yet returned a response to the first request packet [RD-Req # 1: 12], the second request packet [WR-Req # 2: 12] The third request packet [RD-Req # 3: 12] cannot be transmitted to the node 2. That is, there is no data that can be transmitted. For this reason, an empty packet (not shown) is transmitted to the node 2. The node 2 is executing a process corresponding to the received first request packet [RD-Req # 1: 12]. When the process is completed, the first request packet [RD-Req # 1: 12] is executed. Response packet [RD-Rsp # 1: 21] is generated and stored in a transmission register (not shown).

  In the operation state 4, since the node 1 has not yet returned a response to the first request packet [RD-Req # 1: 12], as in the operation state 3, the second request packet [WR- Req # 2: 12] and the third request packet [RD-Req # 3: 12] cannot be transmitted to the node 2. For this reason, an empty packet (not shown) is transmitted to the node 2.

  Further, the node 2 sends a response packet [RD-Rsp # 1: 21] to the completed first request packet [RD-Req # 1: 12] toward the node 3. At this time, the first response packet [RD-Rsp # 1: 21] transmitted from the node 2 arrives at the node 3. The packet arriving at node 3 is not addressed to itself and is transferred to node 1.

  Next, in the operation state 5, the node 3 sends the response packet [RD-Rsp # 1: 21] arriving in the operation state 4 to the node 1 as it is because it is not a packet addressed to itself. Is done. At this time, the response packet [RD-Rsp # 1: 21] for the first request packet [RD-Req # 1: 12] arrives at the node 1. The packet arriving at the node 1 is received because it is addressed to itself, and stored in a reception buffer (not shown). Then, the corresponding process is executed.

  In the node 1, when the first response packet [RD-Rsp # 1: 21] is received, the first transmission register 225A storing the first request packet [RD-Req # 1: 12] It is released and the corresponding transmitted flag 224A is cleared. As a result, the request packet can be transmitted to the node 2.

  Therefore, in the node 1, the second request packet [WR-Req # 2: 12] stored in the second transmission register 225B is transmitted to the node 2, and the corresponding transmitted flag 224B is set. . At this time, the second request packet [WR-Req # 2: 12] transmitted from the node 1 arrives at the node 2. The packet arriving at the node 2 is received because it is addressed to itself, and stored in a reception buffer (not shown). Then, the corresponding process is executed. Since the second request packet is a write request, when it is stored in the reception buffer, the second request packet [WR-Req # 2: 12] is sent to the transmission register (not shown) accordingly. A response packet [WR-Rsp # 2: 21] is generated and written to an output register (not shown).

  Next, in the operation state 6, in the node 2, the response packet [WR-Rsp # 2: 21] to the second request packet [WR-Req # 2: 12] received in the operation state 5 is sent to the node 3. Are sent out. At this time, the second response packet [WR-Rsp # 2: 21] transmitted from the node 2 arrives at the node 3. The packet arriving at node 3 is not addressed to itself and is transferred to node 1.

  In the node 1, since the response to the second request packet [WR-Req # 2: 12] has not yet been returned as in the operation state 3, the third request packet [RD-Req # 3: 12] is not returned. Cannot be sent to node 2. Further, the transmission register 225A released in the operation state 5 is empty. That is, no transmittable data exists in the transmission register. For this reason, an empty packet (not shown) is transmitted to the node 2.

  Next, in the operation state 7, the node 3 sends the response packet [WR-Rsp # 2: 21] arriving in the operation state 6 to the node 1 as it is because it is not a packet addressed to itself as described above. Is done. At this time, the response packet [WR-Rsp # 2: 21] for the second request packet [WR-Req # 2: 12] arrives at the node 1. The packet arriving at node 1 is received because it is addressed to itself, and is stored in a reception buffer (not shown). Then, the corresponding process is executed.

  In the node 1, when the second response packet [WR-Rsp # 2: 21] is received, the second transmission register 225B storing the second request packet [WR-Req # 2: 12] It is released and the corresponding transmitted flag 224B is cleared. As a result, the request packet can be transmitted to the node 2.

  Therefore, in the node 1, the third request packet [RD-Req # 3: 12] stored in the third transmission register 225C is transmitted to the node 2, and the corresponding transmitted flag 224C is set. . At this time, the third request packet [RD-Req # 3: 12] transmitted from the node 1 arrives at the node 2. The packet arriving at the node 2 is received because it is addressed to itself, and stored in a reception buffer (not shown). Then, the corresponding process is executed.

  Next, in the operation state 8, as in the operation state 6, the node 1 has not yet returned a response to the third request packet [RD-Req # 3: 12]. Cannot be sent to. Further, the transmission registers 225A and 225B opened in the operation states 5 and 7 are empty. That is, no transmittable data exists in the transmission register. For this reason, an empty packet (not shown) is transmitted to the node 2. The node 2 is executing a process corresponding to the received third request packet [RD-Req # 3: 12]. When the process is completed, the third request packet [RD-Req # 1: 12] is executed. Response packet [RD-Rsp # 3: 21] is generated and stored in a transmission register (not shown).

  Then, in the operation state 9, since the node 1 has not yet returned a response to the third request packet [RD-Req # 3: 12] as in the operation state 8, another request packet is sent to the node 2. Cannot be sent to. Further, the transmission registers 225A and 225B opened in the operation states 5 and 7 are empty. For this reason, an empty packet (not shown) is transmitted to the node 2.

  Further, the node 2 sends a response packet [RD-Rsp # 3: 21] to the completed third request packet [RD-Req # 3: 12] toward the node 3. At this time, the third response packet [RD-Rsp # 3: 21] transmitted from the node 2 arrives at the node 3. The packet arriving at node 3 is not addressed to itself and is transferred to node 1.

  Next, in the operation state 10, the node 3 sends the response packet [RD-Rsp # 3: 21] arriving in the operation state 9 to the node 1 as it is because it is not a packet addressed to itself, as described above. Is done. At this time, the response packet [RD-Rsp # 1: 21] for the third request packet [RD-Req # 3: 12] arrives at the node 1. The packet arriving at node 1 is received because it is addressed to itself, and is stored in a reception buffer (not shown). Then, the corresponding process is executed.

  In the node 1, when the third response packet [RD-Rsp # 3: 21] is received, the third transmission register 225C storing the third request packet [RD-Req # 3: 12] It is released and the corresponding transmitted flag 224C is cleared. As a result, the request packet can be transmitted to the node 2.

  As described above, the three request packets [RD-Req # 1: 12], [WR-Req # 2: 12], [WR] stored in the transmission registers 225A to 225C are transmitted from the node 1 to the node 2. RD-Req # 3: 12] are transmitted in order, and the node 2 receives them in the order of the transmitted request packets, and executes the corresponding processes in order.

A4.2. Example 2:
10 and 11 are explanatory diagrams showing a specific example 2 of the communication operation executed between the nodes.

  First, in the first operation state 1, packets [WR-Req # 1: 12], [WR-Req # 2: 13], [WR-Req # 3: 12] are stored in the transmission registers 225A to 225C of the node 1. The three request packets are stored in order. Since these three request packets are untransmitted packets, all the transmitted flags 224A to 224C corresponding to the respective transmission registers 225A to 225C are in a clear state.

  Then, in the operation state 2, in the node 1, the request packet [WR-Req # 1: 12] stored in the first transmission register 225A is transmitted to the node 2, and the corresponding transmitted flag 224A is set. The At this time, the first request packet [WR-Req # 1: 12] transmitted from the node 1 arrives at the node 2. The packet arriving at the node 2 is received because it is addressed to itself, and stored in a reception buffer (not shown). Then, the corresponding process is executed. Since the first request packet is a write request, when it is stored in the reception buffer, a transmission register (not shown) responds to the second request packet [WR-Req # 2: 12] accordingly. A response packet [WR-Rsp # 2: 21] is generated and written to an output register (not shown).

  Next, in the operation state 3, the node 2 sends a response packet [WR-Rsp # 1: 21] to the first request packet [WR-Req # 1: 12] received in the operation state 2 to the node 3. Sent out. At this time, the first response packet [WR-Rsp # 1: 21] transmitted from the node 2 arrives at the node 3. The packet arriving at node 3 is not addressed to itself and is transferred to node 1.

  Here, the destination of the second request packet [WR-Req # 2: 13] stored in the second transmission register 225B is the node 3, and the first transmission packet 224A is already set. Is different from the node 2 which is the transmission destination of the request packet [WR-Req # 1: 12]. Therefore, the second request packet [WR-Req # 2: 13] can be transmitted.

  Therefore, in the node 1, the request packet [WR-Req # 2: 12] stored in the second transmission register 225B is transmitted to the node 2, and the corresponding transmitted flag 224B is set. At this time, the second request packet [WR-Req # 2: 13] transmitted from the node 1 arrives at the node 2. The packet arriving at node 2 is not addressed to itself and is transferred to node 3.

  Then, in the operation state 4, in the node 2, as described above, the second request packet [WR-Req # 2: 13] arriving in the operation state 3 is not a packet addressed to itself, so Sent out. At this time, the second request packet [WR-Req # 2: 13] arrives at the node 3. The packet arriving at the node 3 is received because it is addressed to itself, and is stored in a reception buffer (not shown). Then, the corresponding process is executed. Since the second request packet is also a write request, when it is stored in the reception buffer, a transmission register (not shown) responds to the second request packet [WR-Req # 2: 13] accordingly. A response packet [WR-Rsp # 2: 31] is generated and written to an output register (not shown).

  Further, as described above, since the response packet [WR-Rsp # 1: 21] that arrived in the operation state 3 is not a packet addressed to itself, the node 3 transmits the response packet to the node 1 as it is. At this time, the response packet [WR-Rsp # 1: 21] for the first request packet [WR-Req # 1: 12] arrives at the node 1. The packet arriving at the node 1 is received because it is a packet addressed to itself, and is stored in a reception buffer (not shown). Then, the corresponding process is executed.

  In the node 1, when the first response packet [WR-Rsp # 1: 21] is received, the first transmission register 225A in which the first request packet [WR-Req # 1: 12] is stored is stored. It is released and the corresponding transmitted flag 224A is cleared. As a result, the request packet can be transmitted to the node 2.

  Therefore, in the node 1, the third request packet [WR-Req # 3: 12] stored in the third transmission register 225C is transmitted to the node 2, and the corresponding transmitted flag 224C is set. . At this time, the third request packet [WR-Req # 3: 12] transmitted from the node 1 arrives at the node 2. Since the packet arriving at the node 2 is a packet addressed to itself, it is stored in a reception buffer (not shown). Then, the corresponding process is executed. Since the third request packet is also a write request, when it is stored in the reception buffer, the transmission register (not shown) responds to the third request packet [WR-Req # 3: 12] accordingly. A response packet [WR-Rsp # 3: 21] is generated and written to an output register (not shown).

  Next, in the operation state 5, the node 2 sends a response packet [WR-Rsp # 3: 21] to the third request packet [WR-Req # 3: 12] received in the operation state 4 toward the node 3. Are sent out. At this time, the third response packet [WR-Rsp # 3: 21] transmitted from the node 2 arrives at the node 3. The packet arriving at node 3 is not addressed to itself and is transferred to node 1.

  In addition, the node 3 sends a response packet [WR-Rsp # 2: 31] to the second request packet [WR-Req # 2: 13] received in the operation state 4 toward the node 1. At this time, the second response packet [WR-Rsp # 2: 31] transmitted from the node 3 arrives at the node 1. The packet arriving at node 1 is received because it is addressed to itself, and is stored in a reception buffer (not shown). Then, the corresponding process is executed.

  In the node 1, when the second response packet [WR-Rsp # 2: 31] is received, the second transmission register 225B storing the second request packet [WR-Req # 2: 13] It is released and the corresponding transmitted flag 224B is cleared. Thereby, the request packet can be transmitted to the node 3.

  Then, in the operation state 6, in the node 3, the response packet [WR-Rsp # 3: 21] arriving in the operation state 5 is not addressed to itself, and thus is sent to the node 1 as it is. At this time, the response packet [WR-Rsp # 3: 21] for the third request packet [WR-Req # 3: 12] arrives at the node 1. The packet arriving at node 1 is received because it is addressed to itself, and is stored in a reception buffer (not shown). Then, the corresponding process is executed.

  In the node 1, when the third response packet [WR-Rsp # 3: 21] is received, the third transmission register 225C in which the third request packet [WR-Req # 3: 12] is stored is stored. It is released and the corresponding transmitted flag 224C is cleared. As a result, the request packet can be transmitted to the node 2.

  As described above, the three request packets [WR-Req # 1: 12] and [WR-Req # 2: 13] stored in the transmission register are transmitted from the node 1 to the node 2 and from the node 1 to the node 3. ], [WR-Req # 3: 12] are transmitted in order, received at the respective nodes in the order of the transmitted request packets, and the corresponding processes are executed in order.

A5. Effects of the embodiment:
As described in the first specific example, in the present embodiment, when a plurality of request packets are sequentially transmitted from a certain transmission source node to a certain transmission destination node, the transmission source node Request packets can be received in the order transmitted from the nodes, and the corresponding processing can be executed.

  Further, as described in the specific example 2, in this embodiment, even when request packets are sequentially transmitted from a certain node to a plurality of different nodes, the transmission order is the same regardless of the destination node. It is possible to execute processing corresponding to the above.

  In addition, by providing one transmitted flag for a plurality of request packets transmitted from one node, the request packets are sequentially transmitted to a plurality of different nodes as in the embodiment, It is possible to execute corresponding processing in the order of transmission regardless of the destination node.

  However, in this case, if one request packet is sent to any node, the sent flag will be set until a response to this is returned. The request packet cannot be transmitted. For this reason, in this case, the execution efficiency of processing for a plurality of request packets is worse than in the case of the present embodiment.

  In other words, this embodiment can execute processing for a plurality of request packets at high speed.

  In the description of the above specific example, the configuration illustrated in FIG. 1 is omitted and the configuration illustrated in FIG. 1 is illustrated as only a configuration in which only three nodes 1 to 3 are included in the five nodes. The same applies to the five nodes shown in FIG.

B. Variation:
As mentioned above, although embodiment of this invention was described, this invention is not limited to such embodiment at all, In the range which does not deviate from the summary, it is possible to implement in various aspects. . For example, the following modifications are possible.

B1. Modification 1:
In the multiprocessor system of the above-described embodiment, the case where five nodes are provided is shown as an example. However, the present invention is not limited to this, and the present invention can be applied to a case where a plurality of nodes are provided.

B2. Modification 2:
In the multiprocessor system of the above-described embodiment, the number of transmission registers included in each transmission buffer 225 is set to 3 for five nodes, and the number of transmitted flags included in the transmitted flag unit 224 corresponding to this is set. The case of 3 is shown as an example. However, the present invention is not limited to this, and the number of transmission registers and the number of transmitted flags may be two or more, and may be equal to or less than the number obtained by subtracting itself from the total number of nodes connected to the communication path.

  By providing the number of transmission registers and the number of transmitted flags minus the number of all connected nodes, it is possible to transfer from one node to another node to another node other than another node. The request can be transmitted regardless of whether the request has already been transmitted. However, considering the possibility of a situation where requests are continuously sent to all nodes, it depends on the number of nodes and the contents of the process executed, but the possibility is very small. Conceivable. Therefore, it is less necessary to have a configuration including the number of transmission registers and the number of transmitted flags obtained by subtracting the number of nodes from the total number of nodes. And efficient.

B3. Modification 3:
In the above embodiment, until the response packet for the request packet transmitted to a certain node is returned, the transmitted request packet is stored in the transmission register, and the request packet is transmitted to the certain node. The case where the transmitted flag is set is shown as an example, but the present invention is not limited to this. The transmitted flag indicates that the request packet has been transmitted to the node indicated by the transmission destination ID among the data stored in the transmission register. Accordingly, at least information indicating a destination node, in the embodiment, a destination ID is stored, and transmission of a request packet to that node is prohibited until a response packet is received from the destination node. A configuration is also possible.

It is explanatory drawing which shows the general | schematic structure as one Example of the multiprocessor system of this invention. It is explanatory drawing which shows the data structure of the packet transmitted / received between each node. It is explanatory drawing which shows the example of 1 structure of the communication control part with which a node is equipped. It is explanatory drawing shown about the procedure of the transmission / reception control performed in a transmission / reception control part. It is explanatory drawing shown about the procedure of the transmission / reception control performed in a transmission / reception control part. It is explanatory drawing which shows the specific example 1 of the communication operation performed between each node. It is explanatory drawing which shows the specific example 1 of the communication operation performed between each node. It is explanatory drawing which shows the specific example 1 of the communication operation performed between each node. It is explanatory drawing which shows the specific example 1 of the communication operation performed between each node. It is explanatory drawing which shows the specific example 2 of the communication operation performed between each node. It is explanatory drawing which shows the specific example 2 of the communication operation performed between each node. It is explanatory drawing shown about the problem of the data communication between nodes in the case of using a loop bus. It is explanatory drawing shown about the problem of the data communication between nodes in the case of using a loop bus.

Explanation of symbols

10 ... Communication path 20A ... Processor (node)
20B ... Processor (node)
20C ... Processor (node)
20D ... Memory controller (node)
20D ... I / O interface (node)
22A to 22E ... Communication control unit 221 ... Input register 222 ... Output register 223 ... Transmission / reception control unit 224 ... Transmitted flag unit 224A-224C ... Transmitted flag 225 ... Transmission Buffers 225A to 225C ... Transmission register 226 ... Reception data buffer 226A ... Reception register 227 ... Processor I / F control unit SCK ... System clock MPS ... Multiprocessor system

Claims (5)

Among the plurality of nodes connected by a loop communication path, at least two or more nodes are configured by a processor, and by sending a packet from the transmission source node to the transmission destination node on the communication path A multiprocessor system capable of data communication between nodes,
When each node transmits a request packet indicating a request for a process to the destination node, each node stores information indicating the destination node, and the process from the destination node Prohibit sending a new request packet to the destination node until receiving a response packet indicating a response to the request;
A multiprocessor system characterized by that. A multiprocessor system according to claim 1, wherein
Each of the nodes
In order to store information indicating the destination node, a plurality of storage units smaller than (total number of nodes −1) are provided.
A multiprocessor system characterized by that. A multiprocessor system according to claim 1 or 2, wherein
The information indicating the destination node includes a transmitted request packet and a flag indicating that the transmitted request packet has been transmitted.
A multiprocessor system characterized by that. A multiprocessor system according to any one of claims 1 to 3,
The device system according to claim 1, wherein the multiprocessor system is integrated on a single semiconductor substrate. In a multiprocessor system in which at least two nodes among a plurality of nodes connected by a loop communication path are constituted by processors, packets are transmitted from the transmission source node to the transmission destination node on the communication path. A data communication method for performing data communication between nodes,
At each node
Sending a request packet indicating a request for processing to the destination node;
Storing information indicating the destination node when the request packet is transmitted;
Prohibiting transmission of a new request packet to the destination node until a response packet indicating a response to the processing request is received from the destination node;
A data communication method comprising:

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