JP2007148215A - Light-emitting device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a drive transistor of desired characteristics, without disadvantages, such as decrease in aperture ratio. <P>SOLUTION: The drive transistor Tdr for controlling the amperage that is supplied to the light-emitting device E from a power line 15 is formed on a surface of a substrate 10. The drive transistor Tdr includes a semiconductor layer 31, where a channel region 31c is formed between the source region 31s and the drain region 31d, and a gate electrode 511 facing the channel region 31c across a gate insulating layer Lg. The power line 15 extends therethrough, so as to overlap with the channel region 31c, when viewed from a direction perpendicular to the substrate 10. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a structure of a light emitting device provided with a light emitting layer made of various light emitting materials such as an organic EL (ElectroLuminescent) material.

2. Description of the Related Art Conventionally, an active matrix light emitting device in which a transistor for controlling the amount of current supplied to a light emitting element (hereinafter referred to as “driving transistor”) is arranged for each light emitting element has been proposed. For example, Patent Document 1 discloses a configuration in which a driving transistor is arranged on a path from a power supply line to a light emitting element. The semiconductor layer of the driving transistor includes a channel region facing the gate electrode with the gate insulating layer interposed therebetween, and a drain region and a source region located on both sides of the channel region. An electrode (for example, an anode) of the light-emitting element is electrically connected to a drain region of the semiconductor layer through a contact hole in an insulating layer that covers the transistor. In addition, a power supply line overlapping with the source region of the semiconductor layer is formed on the surface of the insulating layer. This power supply line is conducted to the source region through a contact hole in the insulating layer.
JP 2000-356963 A (FIG. 1)

Incidentally, the channel width and channel length of the driving transistor are determined in accordance with the amount of current supplied to the light emitting element. For example, in order to supply a sufficient current to the light emitting element, it is necessary to secure a channel width corresponding to the amount of current in the driving transistor. However, the configuration of Patent Document 1 inevitably increases the area of the drive transistor when the channel width is increased. In particular, in the bottom emission type light emitting device, since the driving transistor is arranged on the emission side of the emitted light by the light emitting element, an increase in the area directly leads to a decrease in the aperture ratio. Against this background, an object of the present invention is to solve the problem of creating a drive transistor having desired characteristics without a disadvantage such as a decrease in aperture ratio.

In order to solve this problem, a light-emitting device according to the present invention is a light-emitting device in which a driving transistor that controls the amount of current supplied from a power supply line to a light-emitting element is formed on a substrate, and the driving transistor is a source A semiconductor layer in which a channel region is formed between the region and the drain region;
And a gate electrode facing the channel region with the gate insulating layer interposed therebetween, and the power supply line overlaps with the channel region. Note that it does not matter in the present invention whether the power supply line overlaps with a part or all of the channel region. Further, the power supply line in the present invention is a wiring to which a predetermined potential (for example, a power supply potential on a higher side or a lower side) is supplied.

In this configuration, since the power supply line is formed so as to overlap with the channel region of the drive transistor, the drive transistor can be selected regardless of the channel width or the channel length as long as it is within the region covered by the power supply line. And the total area of the power lines (further, the aperture ratio in the bottom emission type light emitting device) does not change. Therefore, various disadvantages (for example, a decrease in aperture ratio) due to the total area of the drive transistor and the power supply line can be eliminated.

For example, in a bottom emission type light emitting device, if the channel width of the driving transistor is expanded to the desired size within the range covered by the power supply line, the power supply line supplies the light emitting element without reducing the aperture ratio. It is possible to secure a sufficient amount of current. Also,
The fact that the aperture ratio is maintained at a high level means that the electrical energy to be supplied to the light emitting layer for emitting the desired amount of light from the light emitting device is reduced. Light emitting layer (especially organic EL
Since the deterioration of characteristics progresses as the higher electrical energy is supplied to the material), according to the present invention, which can reduce the electrical energy supplied to the light emitting layer, the lifetime of the light emitting layer (characteristic values such as light emission amount and light emission efficiency). There is an advantage that it is possible to extend the time length until the value decreases to a predetermined value.

In a specific aspect of the present invention, a source region, a drain region, and a channel region are formed in the semiconductor layer so that a direction in which the power supply line extends has a channel length. According to this aspect, since a sufficient channel length can be secured along the power supply line, when the drive transistor is operated in the saturation region (typically, the drive transistor is selectively turned on or off). Particularly when controlled). For example, when the drive transistor is operated in the saturation region, the amount of light (gradation) of the light-emitting element is controlled by controlling the ratio of the length of time that the drive transistor is kept on and the length of time it is kept off. (Tone control by pulse width modulation). In addition, the specific example of this aspect is later mentioned as 2nd Embodiment or 5th Embodiment, for example.

In another embodiment, a source region, a drain region, and a channel region are formed in the semiconductor layer so that a direction in which the power supply line extends has a channel width. According to this aspect, a sufficient channel width can be secured along the power supply line, which is particularly suitable when the driving transistor is operated in a linear region. In the case where the driving transistor is operated in a linear region, for example, the light amount (gradation) of the light emitting element is controlled by controlling the current between the source and the drain of the driving transistor in any of a plurality of stages according to the potential of the gate electrode. May be controlled. In addition, the specific example of this aspect is later mentioned, for example as 1st Embodiment, 3rd Embodiment, and 4th Embodiment.

In the aspect in which the power supply line extends in the channel width direction of the driving transistor, more preferably, a first insulating layer covering the semiconductor layer and the gate electrode is provided, and the gate electrode extends in the same direction as the power supply line. The line conducts to either the source region or the drain region via a plurality of contact holes formed in the first insulating layer, and the plurality of contact holes are arranged along the gate electrode. According to this aspect, a plurality of contact hole spaces can be easily ensured in the longitudinal region along the gate electrode. Since the power supply line is connected to the semiconductor layer through a plurality of contact holes, for example, the reliability of conduction between the power supply line and the semiconductor layer is ensured as compared with a configuration in which only one contact hole is formed. Furthermore, the resistance of the contact portion between the two can be reduced. A specific example of this aspect is the fourth embodiment (FIG. 15).
) Will be described later. The contact hole is a portion for electrically connecting an element located on one side of the insulating layer and an element located on the other side of the insulating layer. It is a portion (hole or hole) penetrating in the thickness direction. The planar shape of the contact hole is arbitrary.

In a preferred embodiment of the present invention, the first electrode (for example, the electrode Ea1 in FIG. 1 or the electrode Eb1 in FIG. 19) is used.
) And a second electrode (for example, the electrode Ea2 in FIG. 1 and the electrode Eb2 in FIG. 19),
The driving transistor and the capacitor are arranged in a direction in which the power supply line extends, the gate electrode and the second electrode are electrically connected, and the power supply line overlaps with the channel region and the capacitor. The capacitive element in this aspect may be a means for holding the potential of the gate electrode of the driving transistor (for example, the capacitive element C1 in FIG. 1), or the gate electrode of the driving transistor may be set to a desired value by capacitive coupling. Means for setting the potential (for example, the capacitive element C2 in FIG. 19)
It may be.

According to this aspect, the power supply line is formed so as to overlap not only the channel region of the driving transistor but also the capacitive element. Therefore, the total area of the driving transistor, the power supply line, and the capacitive element can be reduced as compared with a configuration in which the power supply line and the capacitive element do not overlap. For example, a capacitive element having a sufficient capacitance is configured by enlarging the area of each electrode of the capacitive element within the range covered by the power line. In a more preferred aspect, the first electrode is formed of the same material as the semiconductor layer, and the second electrode is formed of the same material as the gate electrode. According to this aspect, the first electrode and the semiconductor layer (or the second electrode and the gate electrode) can be collectively formed by selectively removing the common conductive film, so that each is formed of a separate material. Compared with the configuration thus configured, the manufacturing process can be simplified and the manufacturing cost can be reduced.

The light emitting device of the present invention is applied to both a top emission type and a bottom emission type. In the bottom emission type light emitting device, the substrate side (from the light emitting element side)
That is, a driving transistor is disposed on the emission side of the emitted light from the light emitting element. In this configuration, the form (size and shape) of the channel region of the driving transistor is directly connected to the aperture ratio.
Therefore, the present invention capable of producing a drive transistor having desired characteristics without reducing the aperture ratio is particularly preferably employed for a bottom emission type light emitting device.

Further, the driving transistor in the present invention may have either a bottom gate structure or a top gate structure. In the bottom gate structure, a gate electrode is formed on the substrate side with respect to the semiconductor layer. In the top gate structure, a gate electrode is formed on the opposite side of the substrate from the semiconductor layer. In this top gate structure, if a power supply line is formed on the opposite side of the semiconductor layer across the gate electrode, the capacitance formed by the gate electrode and the power supply line can be held to hold the potential of the gate electrode of the driving transistor. Can be used. Therefore,
The area of the capacitor formed separately from the gate electrode can be reduced (ideally, a capacitor separate from the gate electrode is not necessary).

The light emitting device according to the present invention is used in various electronic devices. A typical example of this electronic device is a device that uses a light emitting device as a display device. Examples of this type of electronic device include a personal computer and a mobile phone. However, the use of the light emitting device according to the present invention is not limited to image display. For example, the light emitting device of the present invention can also be applied as an exposure device (exposure head) for forming a latent image on an image carrier such as a photosensitive drum by irradiation of light.

<A: Electrical configuration of light emitting device>
FIG. 1 is a circuit diagram showing an electrical configuration of the light emitting device according to the first to fourth embodiments of the present invention. As shown in the figure, the light emitting device D includes a plurality of selection lines 11 and a plurality of signal lines 13 that intersect each other. A pixel P is disposed at each intersection of the selection line 11 and the signal line 13. Therefore, these pixels P are arranged in a matrix. Each pixel P is supplied with a power supply potential Vdd via a power supply line 15.

On the path from the power supply line 15 to the ground line (ground potential Gnd), the light emitting element E and the drive transistor Tdr are arranged. The light emitting element E includes a light emitting layer 23 made of an organic EL material and a first electrode 21.
This is an element interposed between the (anode) and the second electrode 22 (cathode). The first electrodes 21 are formed so as to be separated from each other for each pixel P. On the other hand, the second electrode 22 is continuously formed over a plurality of pixels P and grounded (Gnd). The light emitting layer 23 emits light with a light amount corresponding to the amount of current flowing from the first electrode 21 to the second electrode 22.

The drive transistor Tdr is an n-channel thin film transistor for controlling the amount of current supplied to the light emitting element E. The source electrode of the drive transistor Tdr is connected to the first electrode 21 of the light emitting element E. The drain electrode of the drive transistor Tdr is connected to the power supply line 15.
Between the drain electrode and the gate electrode, a capacitive element C1 for holding the potential of the gate electrode is interposed. The capacitive element C1 includes an electrode Ea1 connected to the drain electrode of the drive transistor Tdr and an electrode Ea2 connected to the gate electrode of the drive transistor Tdr.

The selection transistor Tsl in FIG. 1 is an n-channel thin film transistor that is interposed between the gate electrode (electrode Ea2) of the driving transistor Tdr and the signal line 13 to control the electrical connection between them. The gate electrode of the selection transistor Tsl is connected to the selection line 11. Note that the conductivity types of the drive transistor Tdr and the selection transistor Tsl are appropriately changed.

When the selection signal S supplied to the selection line 11 changes to the active level (high level) and the selection transistor Tsl changes to the on state, the data potential Vdata corresponding to the gradation specified for the pixel P is output from the signal line 13. The voltage is supplied to the gate electrode of the driving transistor Tdr via the selection transistor Tsl. At this time, charges corresponding to the data potential Vdata are accumulated in the capacitive element C1, and therefore, even if the selection line 11 changes to the inactive level and the selection transistor Tsl changes to the off state, the gate electrode of the drive transistor Tdr Is maintained at the data potential Vdata. Therefore, a current corresponding to the potential of the gate electrode of the driving transistor Tdr (current corresponding to the data potential Vdata) is continuously supplied to the light emitting element E. By supplying this current, the light emitting element E emits light with a luminance corresponding to the data potential Vdata.

<B-1: First Embodiment>
Next, a specific configuration of the pixel P of the light emitting device D according to the first embodiment of the present invention will be described. FIG. 2 is a plan view showing a configuration of one pixel P, and FIG. 3 is a cross-sectional view taken along line III-III in FIG. As shown in FIG. 3, the driving transistor Tdr and the light emitting element E such as FIG.
These elements are formed on the surface of the substrate 10. The substrate 10 is a plate-like member made of various insulating materials such as glass and plastic. Each element of the pixel P may be formed using an insulating film body (for example, a film body such as silicon oxide or silicon nitride) covering the substrate 10 as a base.

As shown in FIG. 2, the selection line 11 extends in the X direction, and the signal line 13 and the power supply line 15 extend in the Y direction orthogonal to the X direction. The first electrode 21 constituting the light emitting element E is formed in the gap between the signal line 13 and the power supply line 15. 4 to 6 are plan views showing how the elements shown in FIG. 2 are sequentially formed. 4 to 6, a region A (hereinafter referred to as “electrode formation region”) A in which the first electrode 21 is formed in the subsequent processes is illustrated by a two-dot chain line.

As shown in FIGS. 2 to 4, a semiconductor layer 31 and a semiconductor layer 41 are formed for each pixel P on the surface of the substrate 10. The semiconductor layer 31 and the semiconductor layer 41 are collectively formed in the same process by patterning a film body of a semiconductor material (for example, silicon) formed over the entire area of the substrate 10. In the following, it is simply “formed from the same layer” that a plurality of elements are formed in the same process by selectively removing one film body as in the relationship between the semiconductor layer 31 and the semiconductor layer 41. Is written. Each element formed from the same layer is made of the same material.

As shown in FIGS. 2 and 4, the semiconductor layer 31 is a portion that is formed in a substantially L shape. More specifically, the semiconductor layer 31 includes an element portion 311 constituting the drive transistor Tdr and an extending portion 313 extending in the X direction from the element portion 311 in a negative region in the Y direction when viewed from the electrode formation region A. And an electrode Ea1 continuous from the element portion 311 to the positive side in the Y direction. A cutout portion 315 extending in the X direction is formed in an intermediate portion in the Y direction of the element portion 311. The first portion 311a shown in FIG. 4 is a region located on the extending portion 313 side when viewed from the notch portion 315, and the second portion 311b is a region located on the electrode Ea1 side when viewed from the notch portion 315. On the other hand, the semiconductor layer 41 is formed on the opposite side of the extending portion 313 with the electrode formation region A sandwiched in the Y direction.
Extend in the direction.

As shown in FIG. 3, the surface of the substrate 10 on which the semiconductor layer 31 and the semiconductor layer 41 are formed is covered with the gate insulating layer Lg over the entire area. As shown in FIGS. 2, 3 and 5, the intermediate conductor 51 and the selection line 11 are formed from the same layer on the surface of the gate insulating layer Lg. As shown in FIG. 5, the intermediate conductor 51 includes an electrode Ea2, a gate electrode 511, and a connection portion 513. The electrode Ea2 is a portion overlapping the electrode Ea1 when viewed from the direction perpendicular to the substrate 10. As shown in FIG. 3, the electrode Ea1 and the electrode Ea2 face each other with the gate insulating layer Lg interposed therebetween, whereby the capacitive element C1 of FIG. 1 is formed. The connection portion 513 is a portion extending in the X direction from the electrode Ea2 in the positive region in the Y direction when viewed from the electrode formation region A.

The gate electrode 511 is a portion of the electrode Ea2 that extends from the center in the X direction to the negative side in the Y direction (a portion that is narrower than the electrode Ea2). The gate electrode 511 straddles the notch 315 and the first portion 311a and the first It overlaps with the two portions 311b. As shown in FIGS. 2 and 3, a portion of the semiconductor layer 31 that faces the gate electrode 511 across the gate insulating layer Lg is a channel region 31c. The semiconductor layer 31 includes a source region 31s and a drain region 31 so as to sandwich the channel region 31c.
d is formed. The source region 31s is a region on the extending portion 313 side as viewed from the channel region 31c, and the drain region 31d is a region on the electrode Ea1 side with respect to the channel region 31c. Therefore, as shown in FIG. 5, the line width (dimension in the X direction) of the gate electrode 511 corresponds to the channel length L of the drive transistor Tdr, and the dimension in the Y direction of the first portion 311a is the channel width W of the drive transistor Tdr. It corresponds to. The drive transistor Tdr and the capacitive element C1 are arranged in the Y direction. As described above, the configuration in which the notch 315 is formed in the semiconductor layer 31 electrically separates the source region 31s of the semiconductor layer 31 and the electrode Ea1,
The drain region 31d of the semiconductor layer 31 and the electrode Ea1 are electrically connected.

The selection line 11 extends in the X direction in the vicinity of the semiconductor layer 41. A portion 111 that branches from the selection line 11 to the negative side in the Y direction and overlaps the semiconductor layer 41 functions as a gate electrode of the selection transistor Tsl. That is, the portion 11 of the semiconductor layer 41 across the gate insulating layer Lg.
A portion facing 1 is a channel region of the selection transistor Tsl.

As shown in FIG. 3, the surface of the gate insulating layer Lg on which the intermediate conductor 51 (gate electrode 511 or electrode Ea2) and the selection line 11 are formed is covered with the first insulating layer L1. As shown in FIGS. 2, 3 and 6, the signal line 13, the connecting portion 611, the power supply line 15, and the electrode connecting portion 68 are formed from the same layer on the surface of the first insulating layer L1.

The signal line 13 is a wiring extending in the Y direction in the negative region in the X direction when viewed from the electrode formation region A. As shown in FIGS. 5 and 6, a portion 131 that branches from the signal line 13 in the X direction and overlaps the semiconductor layer 41 is a semiconductor through a contact hole CH1 that penetrates the first insulating layer L1 and the gate insulating layer Lg. Conducting to the drain region of layer 41. Thereby, the portion 131 functions as a drain electrode of the selection transistor Tsl.

The connection portion 611 extends in the X direction and extends from the semiconductor layer 41 and the connection portion 513 (intermediate conductor 51).
) That overlaps both. As shown in FIG. 5 and FIG.
The semiconductor layer 41 via a contact hole CH2 penetrating the insulating layer L1 and the gate insulating layer Lg.
Conductive to the source region. Thereby, the connection portion 611 functions as a source electrode of the selection transistor Tsl. Further, the connection portion 611 is electrically connected to the connection portion 513 through a contact hole CH3 penetrating the first insulating layer L1. With the above configuration, the selection transistor Tsl and the electrode Ea2 (and the gate electrode 511 of the driving transistor Tdr) are electrically connected.

The electrode connecting portion 68 is a substantially rectangular portion formed so as to partially overlap the extending portion 313 of the semiconductor layer 31. As shown in FIGS. 3, 5, and 6, the electrode connection portion 68 includes the first
Extending portion 313 through contact hole CH4 penetrating insulating layer L1 and gate insulating layer Lg
It conducts to (source region 31s of semiconductor layer 31). That is, the electrode connecting portion 68 functions as a source electrode of the driving transistor Tdr.

As shown in FIGS. 2, 3, and 6, the power supply line 15 is a wiring that overlaps with the channel region 31 c (gate electrode 511) of the driving transistor Tdr when viewed from the direction perpendicular to the substrate 10. In the present embodiment, the power supply line 15 extends in the Y direction so as to overlap both the drive transistor Tdr and the capacitor C1 arranged in the Y direction. Furthermore, in this embodiment,
The shape and position of the channel region 31c, the source region 31s, and the drain region 31d (in other words, the gate electrode 511) so that the extending direction (Y direction) of the power supply line 15 coincides with the channel width W direction of the driving transistor Tdr. Is selected. As shown in FIGS. 5 and 6, the gate electrode 511 is placed in the region overlapping with the second portion 311 b of the element portion 311.
Contact holes CH5 penetrating the first insulating layer L1 and the gate insulating layer Lg are formed at positions sandwiched in the direction. The power supply line 15 is electrically connected to the drain region 31d of the semiconductor layer 31 through each contact hole CH5. That is, the portion of the power supply line 15 that overlaps with the second portion 311b functions as the drain electrode of the drive transistor Tdr.

As shown in FIG. 3, the surface of the first insulating layer L1 on which the electrode connecting portion 68 and the power supply line 15 are formed is covered with the second insulating layer L2. A first electrode 21 is formed on the surface of the second insulating layer L2. The first electrode 21 is a substantially rectangular electrode formed of a light-transmitting conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), and is a contact hole CH6 penetrating the second insulating layer L2. Conduction to the electrode connection 68 through the.

On the surface of the second insulating layer L2 on which the first electrode 21 is formed, a shape that partitions the boundary of each pixel P (
A grid-like partition wall 25 is formed. The partition wall 25 plays a role of electrically insulating the adjacent first electrodes 21 (that is, a role enabling individual control of the potential of the first electrode 21). The light emitting layer 23 is disposed in a recess surrounded by the inner peripheral surface of the partition wall 25 and having the first electrode 21 as a bottom surface. Various functional layers (a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, a hole block layer, and an electron block layer) for promoting or improving the light emission by the light emitting layer 23 are the light emitting layers. It is good also as a structure laminated | stacked on 23. FIG.

As shown in FIG. 3, the second electrode 22 is an electrode that is formed continuously over the plurality of pixels P and covers the light emitting layer 23 and the partition 25. Therefore, the partition wall 25 electrically insulates the first electrode 21 and the second electrode 22 in the gap region between the light emitting elements E. In other words, the partition wall 25
Defines a region where current flows between the first electrode 21 and the second electrode 22 (that is, a region where light is actually emitted). The second electrode 22 is formed of a light-reflective conductive material such as a single metal such as aluminum or silver or an alloy containing these as a main component. Therefore, the light emitting layer 2
The light emitted from 3 to the substrate 10 side and the light emitted from the light emitting layer 23 to the opposite side of the substrate 10 and reflected from the surface of the second electrode 22 are the first electrode 21 and each insulating layer (L 2 · L 1・ Lg) and substrate 10
And then pass through. That is, the light emitting device D of the present embodiment is a bottom emission type.

As described above, in the present embodiment, since the power supply line 15 is formed so as to overlap the channel region 31c of the drive transistor Tdr and the capacitive element C1, the power supply line 15 is different from the drive transistor Tdr and the capacitive element C1. Compared to the conventional configuration formed so as not to overlap, the total area of the drive transistor Tdr, the capacitive element C1, and the power supply line 15 can be reduced. Therefore, the aperture ratio can be improved in the bottom emission type light emitting device D. In addition, an improvement in the aperture ratio means that the electrical energy required to emit the desired amount of light from the light emitting device D is reduced. Light emitting layer 23 (especially organic EL
The material) is deteriorated in optical characteristics as the higher electric energy is applied. Therefore, according to the present embodiment in which the aperture ratio is improved, there is an effect that the life of the light emitting layer 23 can be extended. The

By the way, in order to stabilize the power supply potential Vdd supplied to each pixel P and to supply a sufficient current to the light emitting element E, it is desirable that the power supply line 15 is wide. However, the power line 15
However, in the configuration in which the driving transistor Tdr and the capacitive element C1 do not overlap with each other, there is a problem that the increase in the line width of the power supply line 15 directly leads to a decrease in the aperture ratio. On the other hand, in this embodiment, even if the power supply line 15 is enlarged within a range overlapping with the driving transistor Tdr (channel region 31c) and the capacitive element C1, there is no influence on the aperture ratio. Therefore, according to the present embodiment, there is an advantage that the power supply potential Vdd can be stabilized by securing a sufficient line width for the power supply line 15 without reducing the aperture ratio.

In the configuration where the area of the contact hole CH5 is small, the contact hole CH5
In some cases, the power supply line 15 and the drive transistor Tdr are not sufficiently conducted due to the poor formation of the transistor, or the resistance of the contact portion between the power supply line 15 and the drive transistor Tdr (semiconductor layer 31) may increase. Further, when a large current flows from the power supply line 15 to the drive transistor Tdr, the contact portion between the power supply line 15 and the drive transistor Tdr may be destroyed. On the other hand, according to the present embodiment, as described above, the line width of the power supply line 15 is expanded as compared with the conventional configuration, so that the total number of contact holes CH5 and the area of each are sufficiently secured. be able to. That is, in the configuration exemplified in this embodiment, two contact holes CH5 are formed, and each contact hole CH5 secures an area necessary for reliable conduction between the power supply line 15 and the drive transistor Tdr. Therefore, the power supply line 15 and the driving transistor Tdr can be reliably conducted, the resistance of the contact portion between them can be reduced, and further, the destruction of the contact portion between both can be prevented.

In the above description, the line width of the power supply line 15 is focused. However, when focusing on the characteristics of the drive transistor Tdr, the present embodiment also has the following advantages. That is, in the present embodiment, the aperture ratio does not change regardless of the channel length L and the channel width W of the driving transistor Tdr as long as they are within the region covered by the power line 15. Therefore, it is possible to create the drive transistor Tdr having desired characteristics while maintaining a high aperture ratio. In particular, in the present embodiment, the channel region 31c (form of the gate electrode 511) is defined so that the extending direction (Y direction) of the power supply line 15 becomes the channel width W. The width W can be easily secured. Therefore, the driving transistor Tdr that can supply a sufficient amount of current to the light emitting element E is realized.

Since the drive transistor Tdr having a large channel width W has a wide linear region, this embodiment capable of sufficiently securing the channel width W is particularly suitable for the light-emitting device D of the type in which the resistance value of the drive transistor Tdr should be changed stepwise. Is preferred. As such a method, for example, each pixel P
There is a method in which the amount of current to the light emitting element E is controlled stepwise by changing the potential of the gate electrode of the drive transistor Tdr stepwise in accordance with the gradation specified in FIG.

Further, according to the present embodiment, the area of the gate electrode 511 (the area of the channel region 31c) is expanded without reducing the aperture ratio, so that the gate capacitance of the drive transistor Tdr can be easily ensured. Since this gate capacitance is used for holding the data potential Vdata (holding the potential of the gate electrode 511), according to the present embodiment, the capacitance required for the capacitive element C1 can be reduced. Therefore, the area of the capacitive element C1 can be reduced (ideally, the capacitive element C1 is unnecessary). However, in the present embodiment, the power supply line 15 is formed so as to overlap not only the drive transistor Tdr but also the capacitive element C1, so that the electrode Ea1 and the electrode are within the range covered by the power supply line 15. No matter how the area of Ea2 is selected, the aperture ratio is not affected. Therefore, from another point of view, there is also an advantage that a sufficient capacitance can be secured in the capacitive element C1 without reducing the aperture ratio.

In the present embodiment, elements for connecting the first electrode 21 to the drive transistor Tdr (extension part 313 and electrode connection part 68) and elements constituting the selection transistor Tsl (part 131 of the signal line 13 and semiconductor layer 41). And the connecting portion 611) are formed at respective positions sandwiching the light emitting layer 23 along the Y direction. In addition, the signal line 13 is disposed on one side in the X direction when viewed from the light emitting layer 23, and the driving transistor Tdr and the capacitor element C1 are disposed on the other side, and the power line 15
Is formed so as to overlap with both. As described above, in the present embodiment, the light emitting layer 2
Since various elements and wirings are arranged so as to surround the four sides, there is an advantage that the shape of the light emitting layer 23 is simplified and the area thereof is sufficiently secured. Signal line 1
3 part 131, semiconductor layer 41, connection part 611 and connection part 513 are arranged along the X direction, and contact holes (CH 1, CH 2, CH 3) for conducting each of them are linearly formed along the X direction. Arrange. According to this configuration, compared with a configuration in which the portion 131, the semiconductor layer 41, the connection portion 611, and the connection portion 513 are not linearly arranged, the shape and area of the light emitting layer 23 can be simplified more easily. can do.

<B-2: Second Embodiment>
Next, a specific configuration of the pixel P of the light emitting device D according to the second embodiment of the present invention will be described. FIG. 7 is a plan view showing the configuration of the pixel P in the present embodiment. 8 to 10 are shown in FIG.
It is a top view which shows a mode that the element shown by is formed sequentially. In the following embodiments, the same elements as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and detailed description thereof is omitted as appropriate.

As shown in FIGS. 7 and 8, the semiconductor layer 32 and the semiconductor layer 42 are formed from the same layer on the surface of the substrate 10. The semiconductor layer 32 is similar to the semiconductor layer 31 of the first embodiment in the element portion 32.
1, an extending portion 323, and an electrode Ea 1. However, the notch portion 315 is not formed in the element portion 321 in the present embodiment. In addition, the semiconductor layer 42 of the present embodiment is an island-shaped portion having the Y direction as a longitudinal direction. The surface of the substrate 10 on which the semiconductor layer 32 and the semiconductor layer 42 are formed is covered with the gate insulating layer Lg.

As shown in FIGS. 7 and 9, the selection line 11 and the intermediate conductor 5 are formed on the surface of the gate insulating layer Lg.
2 are formed from the same layer. The selection line 11 extends in the X direction and intersects the semiconductor layer 42.
A portion of the semiconductor layer 42 that faces the selection line 11 with the gate insulating layer Lg interposed therebetween becomes a channel region of the selection transistor Tsl.

The intermediate conductor 52 includes an electrode Ea2 that forms a capacitive element C1 facing the electrode Ea1, and an electrode Ea2
The gate electrode 521 adjacent to the negative side in the Y direction as viewed from the side, the connecting portion 522 connecting the electrode Ea2 and the gate electrode 521, and the connecting portion 5 having the same form as the connecting portion 513 in the first embodiment.
23. The gate electrode 521 is an electrode that overlaps the element portion 321 of the semiconductor layer 32, and extends in the X direction from the connecting portion 522 over substantially the entire width (dimension in the X direction) of the element portion 321. As shown in FIG. 7, the gate electrode 521 sandwiching the gate insulating layer Lg in the semiconductor layer 32.
The portion opposite to is the channel region 32c. A source region 32s and a drain region 32d are formed so as to sandwich the channel region 32c. Therefore, in this embodiment,
As shown in FIG. 9, the dimension in the Y direction of the gate electrode 521 corresponds to the channel length L, and the dimension in the X direction of the gate electrode 521 corresponds to the channel width W.

The surface of the gate insulating layer Lg on which the selection line 11 and the intermediate conductor 52 are formed is covered with the first insulating layer L1. As shown in FIGS. 7 and 10, the signal line 13, the connection portion 621, the electrode connection portion 68, and the power supply line 15 are formed on the surface of the first insulating layer L1. Similarly to the first embodiment, the signal line 13 is electrically connected to the electrode Ea2 via the portion 131, the semiconductor layer 42, and the connection portion 621.

As shown in FIG. 10, the power supply line 15 extends in the Y direction so as to overlap both the drive transistor Tdr (particularly the channel region 31c) and the capacitive element C1 when viewed from the direction perpendicular to the substrate 10. In the portion of the element portion 321 that does not overlap with the intermediate conductor 52 (more specifically, the gap between the gate electrode 521 and the electrode Ea2), two pieces penetrating the first insulating layer L1 and the gate insulating layer Lg are provided. A contact hole CH5 is formed. The power supply line 15 is electrically connected to the drain region 32d of the semiconductor layer 32 through each contact hole CH5.

The electrode connection portion 68 is electrically connected to the extension portion 323 of the semiconductor layer 32 through the contact hole CH4, as in the first embodiment. As shown in FIGS. 7 and 10, the first electrode 21 of the light emitting element E is electrically connected to the electrode connection portion 68 through the contact hole CH6 of the second insulating layer L2 covering the signal line 13 and the power supply line 15. The structure of the light emitting layer 23, the partition 25, and the 2nd electrode 22 is the same as that of 1st Embodiment.

As described above, also in this embodiment, the channel region 32c (
Since the power supply line 15 is formed so as to overlap with the gate electrode 521) and the capacitive element C1, the same operations and effects as the first embodiment are exhibited. In the present embodiment, the power line 1
Since the channel region 32c, the source region 32s, and the drain region 32d are defined so that the extending direction 5 (Y direction) becomes the channel length L, a sufficient channel length L is easily secured for the drive transistor Tdr. be able to. Driving transistor T having a large channel length L
Since dr has a wide saturation region, this embodiment is particularly suitable for a light emitting device D of a type in which the on state and the off state of the drive transistor Tdr should be clearly distinguished. As such a system, for example, the amount of light (grayscale) of the light emitting element E is changed by changing the ratio between the on-state period and the off-state period of the driving transistor Tdr according to the gradation designated for each pixel P. ) (Tone control by a pulse width modulation method).

Also in this embodiment, as in the first embodiment illustrated in FIG. 2, the portion 131 of the signal line 13, the semiconductor layer 41, the connection portion 621, and the connection portion 523 are arranged along the X direction. A configuration in which the contact holes (CH1, CH2, CH3) are arranged linearly along the X direction can be employed. According to this configuration, it is possible to more easily realize the simplification of the shape of the light emitting layer 23 and the increase in area.

<B-3: Third Embodiment>
Next, a specific configuration of the pixel P of the light emitting device D according to the third embodiment of the invention will be described. FIG. 11 is a plan view showing the configuration of the pixel P in the present embodiment. As shown in the figure, in the present embodiment, the selection line 11 extends in the Y direction, and the signal line 13 and the power line 15
Extends in the X direction. 12 to 14 are plan views showing how the elements shown in FIG. 11 are sequentially formed.

As shown in FIGS. 11 and 12, a semiconductor layer 33 and a semiconductor layer 43 are formed from the same layer on the surface of the substrate 10. The semiconductor layer 33 is a substantially U-shaped (substantially U-shaped) part. More specifically, the semiconductor layer 33 includes an electrode Ea1 extending in the X direction, an element portion 331 continuous from the electrode Ea1 to the positive side in the X direction, and a gap between the electrode Ea1 and the element portion 331 and the electrode formation region A. And an extending portion 333 extending in the X direction, and a connecting portion 335 that connects the element portion 331 and the extending portion 333 to each other at the end on the positive side in the X direction.

The semiconductor layer 43 includes four portions (431 to 434) each extending in the X direction and a connection portion 436 extending in the Y direction. The portion 431 and the portion 432 are connected to each other at the negative end in the X direction. The portion 432 and the portion 433 are connected to each other at the positive end in the X direction. Further, the portion 433 and the portion 434 are connected to each other at the negative end in the X direction. The connecting portion 436 is connected to the positive end of the portion 434 in the X direction.

As shown in FIGS. 11 and 13, the selection line 11 and the intermediate conductor 53 are formed from the same layer on the surface of the gate insulating layer Lg covering the semiconductor layer 33 and the semiconductor layer 43. Select line 11 is Y
It extends in the direction and intersects with the portions 431 to 434 of the semiconductor layer 43. In this configuration, a portion of each of the portions 431 to 434 that overlaps the selection line 11 becomes a channel region of the selection transistor Tsl. That is, the selection transistor Tsl in this embodiment has a configuration in which a dual-gate transistor including the portion 431 and the portion 432 and a dual-gate transistor including the portion 433 and the portion 434 are arranged in series. According to this configuration, current leakage through each channel region of the semiconductor layer 43 can be suppressed as compared with a configuration in which a single transistor including only a single channel region is used as the selection transistor Tsl. .

As shown in FIG. 13, the intermediate conductor 53 includes an electrode Ea2 whose longitudinal direction is the X direction, a gate electrode 531 extending from the electrode Ea2 to the positive side in the X direction, and a peripheral edge on the negative side in the X direction of the electrode Ea2. And a connecting portion 533 extending in the Y direction. The electrode Ea2 and the electrode Ea1 face each other with the gate insulating layer Lg interposed therebetween, so that the capacitive element C1 is formed.

The gate electrode 531 is an electrode that overlaps the element portion 331 of the semiconductor layer 33, and the connection portion 3.
It extends in the X direction over substantially the entire width of 35. As shown in FIGS. 11 and 13, the portion of the semiconductor layer 33 that faces the gate electrode 531 across the gate insulating layer Lg is the channel region 33c of the drive transistor Tdr. In the semiconductor layer 33, a region located on the electrode Ea2 side with the channel region 33c interposed therebetween is a drain region 33d, and a region located on the extending portion 333 side is a source region 33s. Therefore, as shown in FIG. 13, the line width (dimension in the Y direction) of the gate electrode 531 corresponds to the channel length L, and the dimension in the X direction of the connecting portion 335 corresponds to the channel width W. The drive transistor Tdr and the capacitive element C1 are arranged in the X direction.

The surface of the gate insulating layer Lg on which the selection line 11 and the intermediate conductor 53 are formed is covered with the first insulating layer L1. As shown in FIGS. 11 and 14, the signal line 13, the connection part 631, the electrode connection part 68, and the power supply line 15 are formed from the same layer on the surface of the first insulating layer L1. The signal line 13 is connected to the semiconductor layer 4 via a contact hole CH1 penetrating the first insulating layer L1 and the gate insulating layer Lg.
3 connection part 436 is conducted. The form of the electrode connection portion 68 and the connection relationship with other elements are the same as those in the first embodiment and the second embodiment.

The connection portion 631 extends in the Y direction so as to overlap the positive end portion in the X direction of the portion 431 of the semiconductor layer 43 and the connection portion 533 of the intermediate conductor 53. As shown in FIGS. 13 and 14, the connection portion 631 is electrically connected to the portion 431 via the contact hole CH2, and is electrically connected to the connection portion 533 of the intermediate conductor 53 via the contact hole CH3. That is, the source electrode (part 431) of the selection transistor Tsl and the electrode Ea2 of the capacitive element C1 (and the gate electrode 531 of the driving transistor Tdr) are electrically connected via the connection portion 631.

The power line 15 is connected to the channel region 3 of the driving transistor Tdr when viewed from the direction perpendicular to the substrate 10.
It extends in the X direction so as to overlap both 3c and the capacitive element C1. A contact hole CH5 penetrating the first insulating layer L1 and the gate insulating layer Lg is formed in a region of the element portion 331 that does not overlap with the intermediate conductor 52. The power supply line 15 is electrically connected to the drain region 33d of the semiconductor layer 33 through the contact hole CH5.

As described above, also in this embodiment, the channel region 3 of the drive transistor Tdr
Since the power supply line 15 is formed so as to overlap with 3c (gate electrode 531) and the capacitive element C1, the same operations and effects as in the first embodiment are exhibited. In the present embodiment, the channel region 33c, the source region 33s, and the drain region 33d are defined so that the direction in which the power supply line 15 extends and the direction of the channel width W coincide with each other. Similarly to the above, there is an advantage that a sufficient channel width W can be secured for the drive transistor Tdr.

In the present embodiment, the driving transistor Tdr is disposed in the gap region between the electrode connection portion 68 and the signal line 13 when viewed from the direction perpendicular to the substrate 10, and the power supply line 15 covering the driving transistor Tdr is connected to the signal line 13. And the same layer. In this configuration, since the signal line 13 and the power supply line 15 are close to each other, noise generated in the signal line 13 is caused by the drive transistor Tdr and the electrode connection portion regardless of the configuration in which the drive transistor Tdr and the signal line 13 are adjacent to each other. 68 can be reduced or prevented.

In the first embodiment and the second embodiment, the configuration in which the signal line 13 and the capacitive element C1 (drive transistor Tdr) are arranged at each position sandwiching the light emitting layer 23 along the X direction is illustrated. In this configuration, elements (part 131, semiconductor layer 41, connection part 611 (621) and connection part 513 (52) related to the selection transistor Tsl between the signal line 13 and the capacitive element C 1.
3)) needs to be disposed over the entire width of the light emitting layer 23 in the X direction. On the other hand, in the present embodiment, elements related to the selection transistor Tsl (semiconductor layer 43 and connection portion 6).
31) can be arranged independently of the light emitting layer 23, so that the aperture ratio can be increased by the amount that, for example, the portion 131 and the connecting portion 611 can be omitted, as compared with the first and second embodiments. .

In the present embodiment, the contact holes CH2, CH3, CH4, and CH6 are disposed close to each other in the region on the light emitting layer 23 side as viewed from the drive transistor Tdr. According to this configuration, for example, compared to a configuration in which the contact holes CH2 and CH3 are formed on one side in the X direction as viewed from the driving transistor Tdr, a region where the power supply line 15 extends in the X direction can be sufficiently secured. There is an advantage.

<B-4: Fourth Embodiment>
Next, a specific configuration of the pixel P of the light emitting device D according to the fourth embodiment of the present invention will be described. FIG. 15 is a plan view showing the configuration of the pixel P in the present embodiment. As shown in the figure, in this embodiment, the selection line 11 extends in the Y direction and the signal line 13 and the power supply line 15 extend in the X direction, as in the third embodiment. 16 to 18 are plan views showing how the elements shown in FIG. 15 are sequentially formed. In addition, the same code | symbol is attached | subjected about the element similar to 3rd Embodiment among this embodiment, and the detailed description is abbreviate | omitted suitably.

As shown in FIGS. 15 and 16, the semiconductor layer 34 and the semiconductor layer 44 are formed from the same layer on the surface of the substrate 10. The semiconductor layer 34 is a substantially rectangular portion located on the positive side in the Y direction when viewed from the electrode formation region A. The semiconductor layer 44 has the same shape as the semiconductor layer 43 of the third embodiment.

As shown in FIGS. 15 and 17, the select line 11 and the intermediate conductor 54 are formed from the same layer on the surface of the gate insulating layer Lg covering the semiconductor layer 34 and the semiconductor layer 44. The selection line 11 is the third
This is the same as the embodiment. As shown in FIG. 17, the intermediate conductor 54 includes a gate electrode 541 and a connection portion 543. The gate electrode 541 is a portion that overlaps the semiconductor layer 34 with the gate insulating layer Lg interposed therebetween, and extends in the X direction over substantially the entire width of the semiconductor layer 34. The connection portion 543 extends from the end portion of the gate electrode 541 in the Y direction, similarly to the connection portion 533 of the third embodiment.

As shown in FIG. 15, the gate electrode 541 is sandwiched between the gate insulating layers Lg in the semiconductor layer 34.
The portion opposite to is the channel region 34c of the drive transistor Tdr. In addition, the semiconductor layer 3
4, the region located on the electrode forming region A side with the channel region 34c interposed therebetween is the source region 34s.
The region located on the opposite side is the drain region 34d. Accordingly, as shown in FIG. 17, the line width (dimension in the Y direction) of the gate electrode 541 corresponds to the channel length L, and the dimension in the X direction of the semiconductor layer 34 corresponds to the channel width W.

As shown in FIG. 18, on the surface of the first insulating layer L1 covering the selection line 11 and the intermediate conductor 54, the signal line 13, the connection part 641, the electrode connection part 68, and the power supply line 15 are formed from the same layer. It is formed. Each form of the signal line 13 / connection part 641 and the electrode connection part 68 and the connection relationship with other elements are the same as those of the signal line 13 / connection part 631 and the electrode connection part 68 in the third embodiment.

As in the third embodiment, the power supply line 15 extends in the X direction so as to overlap the channel region 34c of the drive transistor Tdr when viewed from the direction perpendicular to the substrate 10. 15 and 18
As shown in FIG. 2, the power line 15 includes a plurality of (through the first insulating layer L1 and the gate insulating layer Lg (
Conduction to the drain region 34d of the semiconductor layer 34 through the five contact holes CH5.
The plurality of contact holes CH5 are arranged in the X direction along the gate electrode 541.

As described above, also in this embodiment, the channel region 3 of the drive transistor Tdr
Since the power supply line 15 is formed so as to overlap with 4c (the gate electrode 541), the same operation and effect as the first embodiment and the third embodiment are exhibited. In the present embodiment, a plurality of contact holes CH5 are formed along the gate electrode 541. Therefore, as compared with the third embodiment, the driving transistor Tdr and the power supply line 15 are reliably conducted and both of them are connected. The resistance of the contact portion can be reduced. In the present embodiment, the capacitive element C1 of FIG. 1 is not formed independently, but the gate electrode 541 is formed over the entire width of the semiconductor layer 34 to ensure a sufficient capacitance for holding the data potential Vdata. Is possible.

<C: Fifth Embodiment>
<C-1: Pixel Electrical Configuration>
Next, the structure of the light-emitting device D which concerns on 5th Embodiment of this invention is demonstrated. FIG. 19 is a circuit diagram showing an electrical configuration of one pixel P in the light emitting device D. As shown in the figure, in the present embodiment, the source electrode of the p-channel type driving transistor Tdr is connected to the power supply line 15 and the drain electrode is connected to the first electrode 21 of the light emitting element E. The point that the gate electrode of the selection transistor Tsl is connected to the selection line 11 and the drain electrode is connected to the signal line 13 is the same as the configuration of FIG.

As shown in FIG. 19, the gate electrode and the drain electrode (light emitting element E) of the driving transistor Tdr.
Between the first electrode 21), an n-channel transistor (hereinafter referred to as "initializing transistor") Tint for controlling the electrical connection therebetween is interposed. The gate electrode of the initialization transistor Tint is connected to the initialization line 12 to which the initialization signal INT is supplied. The initialization line 12 is shared by, for example, a plurality of pixels P arranged in the X direction.

Further, the pixel P of the present embodiment includes a capacitive element C2 composed of the electrode Eb1 and the electrode Eb2. The electrode Eb1 is connected to the source electrode of the selection transistor Tsl. The electrode Eb2 is connected to the gate electrode of the drive transistor Tdr. Although not shown in FIG. 19, a capacitive element C 1 that holds the potential of the gate electrode of the drive transistor Tdr is disposed between the gate electrode and the power supply line 15, as in the configuration illustrated in FIG. May be.

Next, the operation of one pixel P will be described by dividing it into an initialization period, a writing period, and a driving period. First, in the initialization period, a predetermined potential Vref is supplied to the signal line 13, and
The selection signal S of the selection line 11 and the initialization signal INT of the initialization line 12 maintain the active level (high level). Therefore, the potential Vref is supplied from the signal line 13 to the electrode Eb1 of the capacitive element C2 via the selection transistor Tsl. Further, when the initialization transistor Tint is turned on, the drive transistor Tdr is diode-connected. Therefore,
The potential Vg of the gate electrode of the drive transistor Tdr converges to a difference value (Vg = Vdd−Vth) between the power supply potential Vdd of the power supply line 15 and the threshold voltage Vth of the drive transistor Tdr.

Next, in the writing period after the lapse of the initialization period, the initialization signal INT transitions to the inactive level (low level), and the diode connection of the drive transistor Tdr is released. Then, the potential Vref supplied from the signal line 13 to the electrode Eb1 is changed to the data potential Vdata corresponding to the gradation of the pixel P while the selection transistor Tsl is maintained in the on state. Since the impedance of the gate electrode of the driving transistor Tdr is sufficiently high, when the electrode Eb1 changes from the potential Vref to the data potential Vdata by a change amount ΔV (= Vref−Vdata), the potential of the electrode Eb2 is caused by capacitive coupling in the capacitive element C2. It fluctuates from the immediately preceding potential Vg (= Vdd−Vth). The amount of change in the potential of the electrode Eb2 at this time depends on the capacitive element C2 and other parasitic capacitances (
For example, it is determined according to the gate capacitance of the driving transistor Tdr, the capacitance parasitic to other wiring, or the capacitance ratio with the capacitance element C1) when the pixel P includes the capacitance element C1. More specifically, when the capacitance of the capacitive element C2 is “C” and the capacitance of the parasitic capacitance is “Cs”, the amount of change in the potential of the electrode Eb2 is expressed as “ΔV · C / (C + Cs)”. Is done. Therefore, at the end of the writing period, the potential Vg of the driving transistor Tdr is stabilized at the level of the following formula (1).
Vg = Vdd−Vth−k · ΔV (1)
However, k = C / (C + Cs)

In the driving period after the writing period elapses, the selection signal S transits to an inactive level and the selection transistor Tsl changes to an off state. A current corresponding to the potential Vg of the gate electrode of the drive transistor Tdr is supplied from the power supply line 15 via the drive transistor Tdr to the light emitting element E.
To be supplied. By supplying this current, the light emitting element E emits light with a light amount corresponding to the data potential Vdata.

Assuming that the driving transistor Tdr operates in the saturation region, the current I supplied to the light emitting element E in the driving period is expressed by the following equation (2). However, “β” is a gain coefficient of the driving transistor Tdr, and “Vgs” is a gate-source voltage of the driving transistor Tdr.
I = (β / 2) (Vgs−Vth) ² (2)
= (Β / 2) (Vdd−Vg−Vth) ²
By substituting equation (1), equation (2) is transformed as follows.
I = (β / 2) (k · ΔV) ²
That is, in the present embodiment, the current I supplied to the light emitting element E is the driving transistor Tdr.
It does not depend on the threshold voltage Vth. Therefore, it is possible to suppress an error (luminance unevenness) in the light amount of the light emitting element E due to the variation in the threshold voltage Vth of each drive transistor Tdr.

<C-2: Structure of Pixel P>
Next, a specific structure of the pixel P in the present embodiment will be described with reference to FIGS. FIG. 20 is a plan view showing the configuration of one pixel P, and FIGS.
It is a top view which shows a mode that each element shown by FIG. 20 is formed sequentially.

As shown in FIGS. 20 and 21, the semiconductor layer 35 and the semiconductor layer 45 are formed from the same layer on the surface of the substrate 10. The semiconductor layer 35 includes a substantially rectangular first element portion 351 constituting the drive transistor Tdr, a second element portion 352 connected to the first element portion 351, and a first element portion 35.
1 and an extending portion 353 extending to the negative side in the X direction. The second element part 352 is a part constituting the initialization transistor Tint of FIG. 19, and a part 352a protruding from the first element part 351 to the negative side in the Y direction and a positive side in the X direction as viewed from the part 352a. A portion 35 extending in the Y direction
2b are connected to each other at the negative ends in the Y direction.

The semiconductor layer 45 includes an electrode Eb1 and an element portion 451. The electrode Eb1 is the capacitive element C in FIG.
2 is a substantially rectangular electrode. The element portion 451 is a portion constituting the selection transistor Tsl, a portion 451a protruding from the electrode Eb1 to the positive side in the Y direction, and a portion 451b extending in the Y direction on the positive side in the X direction as viewed from the portion 451a. Are connected to each other at the positive ends in the Y direction.

As shown in FIGS. 20 and 22, the selection line 11, the initialization line 12, and the intermediate conductor 55 are formed from the same layer on the surface of the gate insulating layer Lg covering the semiconductor layer 35 and the semiconductor layer 45. . The selection line 11 extends in the X direction and overlaps with the element portion 451 of the semiconductor layer 45. Semiconductor layer 45
Of each of the portions 451a and 451b, a region facing the selection line 11 via the gate insulating layer Lg becomes a channel region. Further, the initialization line 12 extends in the X direction and extends to the semiconductor layer 3.
5 overlaps with the second element portion 352. Of each of the portion 352a and the portion 352b of the semiconductor layer 35, a region facing the initialization line 12 via the gate insulating layer Lg becomes a channel region.
As described above, the selection transistor Tsl and the initialization transistor Tin in this embodiment.
t is a dual-gate transistor.

The intermediate conductor 55 includes a substantially rectangular electrode Eb2, a gate electrode 551 that is adjacent to the negative side in the Y direction as viewed from the electrode Eb2, and a connecting portion 55 that connects the electrode Eb2 and the gate electrode 551.
2 is included. Electrode Eb1 and electrode Eb2 are opposed to each other with gate insulating layer Lg interposed therebetween, so that capacitive element C2 in FIG. 19 is configured.

The gate electrode 551 is an electrode that overlaps the first element portion 351 of the semiconductor layer 35, and extends from the connecting portion 552 in the X direction over substantially the entire width of the first element portion 351. As shown in FIG. 20, the gate electrode 55 is sandwiched between the gate insulating layer Lg in the semiconductor layer 35 (first element portion 351).
A portion facing 1 is a channel region 35c of the drive transistor Tdr. The semiconductor layer 35 includes a drain region 35d located on the extending portion 353 side with the channel region 35c interposed therebetween,
A source region 35s located on the semiconductor layer 45 side is formed. Therefore, as shown in FIG. 22, the dimension of the gate electrode 551 in the Y direction is the channel length L of the drive transistor Tdr.
The dimension in the X direction of the first element portion 351 corresponds to the channel width W. The drive transistor Tdr and the capacitive element C2 are arranged in the Y direction.

The surface of the gate insulating layer Lg on which the selection line 11, the initialization line 12, and the intermediate conductor 55 are formed is covered with the first insulating layer L1. As shown in FIGS. 20 and 23, the signal line 13, the connection portion 651, the electrode connection portion 68, and the power supply line 15 are formed on the surface of the first insulating layer L1. The signal line 13 extending in the Y direction has a contact hole C penetrating the first insulating layer L1 and the gate insulating layer Lg.
The portion 451b (that is, the drain electrode of the selection transistor Tsl) is conducted through H1.
The form of the electrode connection portion 68 and the connection relationship with other elements are the same as in the first embodiment.

The power supply line 15 extends in the Y direction so as to overlap both the channel region 35c (gate electrode 551) of the driving transistor Tdr and the capacitive element C2. As shown in FIGS. 22 and 23, two contact holes CH5 are formed in a portion of the first element portion 351 that does not overlap with the intermediate conductor 55 (more specifically, a gap between the gate electrode 551 and the electrode Eb2). Is formed. The power supply line 15 is electrically connected to the source region 35s of the semiconductor layer 35 through the contact hole CH5.

A notch 151 is formed in the peripheral edge on the positive side in the X direction of the power supply line 15. The connection portion 651 is a portion formed inside the cutout portion 151 and spaced from the power supply line 15, and is overlapped with the portion 352 b of the second element portion 352 and the gate electrode 551 of the intermediate conductor 55 in the Y direction. Extend to. As shown in FIGS. 22 and 23, the connecting portion 651 is connected to the second element portion 352 (part 352) via a contact hole CH2 that penetrates the first insulating layer L1 and the gate insulating layer Lg.
Conducting to b) and conducting to the intermediate conductor 55 (gate electrode 551) through a contact hole CH3 penetrating the first insulating layer L1. That is, the initialization transistor Tint and the gate electrode 551 of the driving transistor Tdr are electrically connected via the connection portion 651.

As described above, also in this embodiment, the channel region 3 of the drive transistor Tdr
Since the power supply line 15 is formed so as to overlap with 5c (gate electrode 551) and the capacitive element C2, the same operations and effects as the first embodiment are exhibited. The direction in which the power line 15 extends (
Since (Y direction) coincides with the channel length L direction of the drive transistor Tdr, there is an advantage that the channel length L can be sufficiently secured as in the second embodiment.

<D: Modification>
Various modifications can be made to each of the above embodiments. An example of a specific modification is as follows. In addition, you may combine each following aspect suitably.

(1) Modification 1
In the above embodiment, the top-gate driving transistor Tdr in which the gate electrodes (511, 521, 531, 541, 551) are formed in the upper layer of the semiconductor layer (31, 32, 33, 34, 35) is exemplified. However, a bottom-gate transistor in which a gate electrode is formed in a lower layer of a semiconductor layer (that is, a gate electrode is interposed between the semiconductor layer and the substrate 10) may be employed as the driving transistor Tdr. When the driving transistor Tdr has a top gate structure as in each of the above embodiments, a portion where the gate electrode and the power supply line 15 face each other with the first insulating layer L1 interposed therebetween is the gate electrode of the driving transistor Tdr. It functions as a capacitor for holding a potential. According to this configuration, since the capacitance required for the capacitive element C1 is reduced, the capacitive element C1 is reduced in size (ideally, as illustrated in the fourth and fifth embodiments). C1 is omitted).

(2) Modification 2
In each of the above embodiments, the bottom emission type light emitting device D is illustrated, but the present invention is also applied to a top emission type light emitting device in which the emitted light from the light emitting element is emitted to the side opposite to the substrate 10. When the space required for the arrangement of the drive transistor Tdr and the power supply line 15 is large, there are various disadvantages such as high definition of the pixel P being restricted even in the top emission type light emitting device. According to the present invention, since the total area of the drive transistor Tdr and the power supply line 15 is reduced, there is an advantage that these disadvantages can be eliminated when applied to a top emission type light emitting device. However, in the bottom emission type light emitting device D, the driving transistor Tdr and the power source line 15 are disposed on the emission side of the emitted light from the light emitting element E (that is, the substrate 10 side as viewed from the light emitting element E). Line 15
An increase in the area directly leads to a decrease in the aperture ratio. Therefore, the drive transistor Tdr and the power line 1
The present invention capable of reducing the area of 5 is a bottom emission type light emitting device D in which the aperture ratio is a problem.
It can be said that this is particularly suitable.

(3) Modification 3
In the above embodiments, the channel region (31c, 32c, 33) of the drive transistor Tdr
The configuration in which the power supply line 15 is formed so as to overlap with the entire area of c, 34c, and 35c) is illustrated, but a configuration in which the power supply line 15 is formed so as to overlap with a part of the channel region may be adopted. A configuration in which the power supply line 15 is formed so as to overlap not only the channel region but also the source region (31s, 32s, 33s, 34s, 35s) and the drain region (31d, 32d, 33d, 34d, 35d) is also employed. .

(4) Modification 4
You may combine the above each form suitably. For example, in the pixel P that compensates the threshold voltage Vth of the drive transistor Tdr as in the fifth embodiment, the direction in which the power supply line 15 extends is the same as in the first embodiment, the third embodiment, and the fourth embodiment. The configuration of the channel region 35c, the source region 35s and the drain region 35d in the semiconductor layer 35 and the direction of the power supply line 15 may be selected so that the direction of the channel width W of the drive transistor Tdr matches.

(5) Modification 5
In each of the above embodiments, the configuration in which the light emitting layer 23 is formed only in the inner region of the inner periphery of the partition wall 25 is exemplified. However, light emission is performed over the entire surface of the substrate 10 (more specifically, the entire surface of the second insulating layer L2). The layer 23 may be formed continuously. According to this configuration, for example, there is an advantage that an inexpensive film forming technique such as a spin coating method can be adopted for forming the light emitting layer 23. In addition,
Since the first electrode 21 is individually formed for each light emitting element E, the light emitting layer 23 includes a plurality of light emitting elements E.
Although it is continuous, the light amount of the light emitting layer 23 is individually controlled for each light emitting element E. As described above, in the configuration in which the light emitting layer 23 is continuous over the plurality of light emitting elements E, the partition walls 25 may be omitted.

In the case where the light emitting layer 23 is formed by the ink jet method (droplet discharge method) in which the droplets of the light emitting material are discharged in the spaces partitioned by the partition walls 25, the second insulating layer L2 as in the above embodiments. The structure which has arrange | positioned the partition 25 on this surface is employ | adopted suitably. However, the method for forming the light emitting layer 23 for each light emitting element E is appropriately changed. More specifically, a method of selectively removing a film of a light emitting material formed over the entire area of the substrate 10 or a laser transfer (LITI: Laser-Induced Therma)
The light emitting layer 23 is formed for each light emitting element E by various patterning techniques such as l Imaging). In this case, the light emitting layer 23 can be formed independently for each light emitting element E without forming the partition wall 25. As described above, the partition 25 is not necessarily a necessary element in the light emitting device of the present invention.

(6) Modification 6
In each of the above embodiments, the light emitting element E including the light emitting layer 23 made of an organic EL material has been exemplified, but the light emitting element in the present invention is not limited to this. For example, various light emitting elements such as a light emitting element including a light emitting layer made of an inorganic EL material and an LED (Light Emitting Diode) element can be employed. The light-emitting element in the present invention may be an element that emits light by supplying electric energy (typically supplying current), and its specific structure and material are not limited.

<E: Application example>
Next, specific modes of electronic devices using the light-emitting device according to the present invention will be described. FIG. 24 is a perspective view showing the configuration of a mobile personal computer that employs the light emitting device D according to any one of the embodiments described above as a display device. The personal computer 2000 includes a light emitting device D as a display device and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002. This light emitting device D is organic E
Since the light emitting layer 23 of the L material is used for the light emitting element E, a screen with a wide viewing angle and easy to see can be displayed.

FIG. 25 shows a configuration of a mobile phone to which the light emitting device D according to each embodiment is applied. Mobile phone 3
000 includes a plurality of operation buttons 3001, scroll buttons 3002, and a light emitting device D as a display device. By operating the scroll button 3002, the screen displayed on the light emitting device D is scrolled.

FIG. 26 shows a personal digital assistant (PDA: Personal Digit) to which the light emitting device D according to each embodiment is applied.
al Assistants). The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and a light emitting device D as a display device. When the power switch 4002 is operated, various kinds of information such as an address book and a schedule book are displayed on the light emitting device D.

Electronic devices to which the light emitting device according to the present invention is applied include those shown in FIGS. 24 to 26, digital still cameras, televisions, video cameras, car navigation devices, pagers, electronic notebooks, electronic papers, calculators. , Word processor, workstation,
Examples include a video phone, a POS terminal, a printer, a scanner, a copying machine, a video player, and a device equipped with a touch panel. Further, the use of the light emitting device according to the present invention is not limited to the display of images. For example, in an image forming apparatus such as an optical writing type printer or an electronic copying machine, a writing head that exposes a photosensitive member according to an image to be formed on a recording material such as paper is used. The light emitting device of the present invention can also be used.

It is a circuit diagram which shows the electrical structure of a light-emitting device. It is a top view which shows the structure of the pixel in 1st Embodiment. It is sectional drawing seen from the III-III line in FIG. It is a top view which shows the step in which the semiconductor layer was formed. It is a top view which shows the stage in which the selection line and the intermediate conductor were formed. It is a top view which shows the stage in which the signal line and the power source line were formed. It is a top view which shows the structure of the pixel which concerns on 2nd Embodiment. It is a top view which shows the step in which the semiconductor layer was formed. It is a top view which shows the stage in which the selection line and the intermediate conductor were formed. It is a top view which shows the stage in which the signal line and the power source line were formed. It is a top view which shows the structure of the pixel which concerns on 3rd Embodiment. It is a top view which shows the step in which the semiconductor layer was formed. It is a top view which shows the stage in which the selection line and the intermediate conductor were formed. It is a top view which shows the stage in which the signal line and the power source line were formed. It is a top view which shows the structure of the pixel which concerns on 4th Embodiment. It is a top view which shows the step in which the semiconductor layer was formed. It is a top view which shows the stage in which the selection line and the intermediate conductor were formed. It is a top view which shows the stage in which the signal line and the power source line were formed. It is a circuit diagram which shows the electric constitution of the pixel of the light-emitting device which concerns on 5th Embodiment of this invention. It is a top view which shows the structure of the pixel which concerns on 5th Embodiment. It is a top view which shows the step in which the semiconductor layer was formed. It is a top view which shows the stage in which the selection line and the intermediate conductor were formed. It is a top view which shows the stage in which the signal line and the power source line were formed. It is a perspective view which shows the specific form of the electronic device which concerns on this invention. It is a perspective view which shows the specific form of the electronic device which concerns on this invention. It is a perspective view which shows the specific form of the electronic device which concerns on this invention.

Explanation of symbols

D: Light emitting device, E: Light emitting element, P: Pixel, 11: Selection line, 12: Initialization line, 1
3 ... Signal line, 15 ... Power supply line, 21 ... First electrode, 22 ... Second electrode, 23 ... Light emitting layer, 25 ... Partition wall, Lg ... Gate insulating layer, L1 ... First insulation Layer, L2 ... second insulating layer, 31
, 32, 33, 34, 35, 41, 42, 43, 44, 45... Semiconductor layer, 31c, 32c
, 33c, 34c, 35c ... channel region, 31s, 32s, 33s, 34s, 35s ... source region, 31d, 32d, 33d, 34d, 35d ... drain region, 51, 52, 53, 5
4, 55 ... intermediate conductor, 511, 521, 531, 541, 551 ... gate electrode, 6
8: Electrode connection portion, L: Channel length, W: Channel width.

Claims (9)

A light-emitting device in which a driving transistor for controlling the amount of current supplied from a power supply line to a light-emitting element is formed on a substrate,
The drive transistor is
A semiconductor layer in which a channel region is formed between a source region and a drain region;
A gate electrode facing the channel region across a gate insulating layer,
The power supply line overlaps with the channel region. The light emitting device according to claim 1, wherein the source region, the drain region, and the channel region are formed in the semiconductor layer so that a direction in which the power supply line extends has a channel length. The light emitting device according to claim 1, wherein the source region, the drain region, and the channel region are formed in the semiconductor layer so that a direction in which the power supply line extends has a channel width. Comprising a first insulating layer covering the semiconductor layer and the gate electrode;
The gate electrode extends in the same direction as the power line,
The power line is electrically connected to either the source region or the drain region through a plurality of contact holes formed in the first insulating layer;
The light emitting device according to claim 3, wherein the plurality of contact holes are arranged along the gate electrode. Comprising a capacitive element including a first electrode and a second electrode;
The drive transistor and the capacitive element are arranged in a direction in which the power supply line extends,
The gate electrode and the second electrode are electrically connected;
The light-emitting device according to claim 1, wherein the power line overlaps the channel region and the capacitor. The first electrode is formed of the same material as the semiconductor layer,
The light emitting device according to claim 5, wherein the second electrode is formed of the same material as the gate electrode and faces the first electrode with the gate insulating layer interposed therebetween. The light-emitting device according to claim 1, wherein the emitted light from the light-emitting element is transmitted through the substrate and emitted. The semiconductor layer is interposed between the gate electrode and the substrate;
The light emitting device according to claim 1, wherein the power supply line is formed on a side opposite to the semiconductor layer with the gate electrode interposed therebetween. The electronic device which comprises the light-emitting device in any one of Claims 1-8.

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