JP2007143261A - Inverter and method of driving same, and light emitting apparatus and liquid crystal television using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To flexibly set timing of a switching operation in an inverter. <P>SOLUTION: An H-bridge circuit is controlled based on a triangular waveform signal Vosc and an error voltage Verr. A first high-side transistor MH1 and a second low-side transistor ML2 are turned on for a first period until the triangular waveform signal reaches the error voltage. The first high-side transistor MH1 is turned on for a second period until the triangular waveform signal reaches a peak edge. A second high-side transistor MH2 is turned on for a third period until the triangular waveform signal reaches a bottom edge. A first low-side transistor ML1 and the second high-side transistor MH2 are turned on for a fourth period until the triangular waveform signal reaches the error voltage again. The second high-side transistor MH2 is turned on for a fifth period until the triangular waveform signal reaches the peak edge again. The first high-side transistor MH1 is turned on for a sixth period until the triangular waveform signal reaches the bottom edge again. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an inverter that supplies a drive voltage to a fluorescent lamp or the like, and more particularly, to an inverter drive system.

  In recent years, instead of cathode-ray tube televisions, liquid crystal televisions that can be made thin and large have become popular. A liquid crystal television has a plurality of cold cathode fluorescent lamps (hereinafter referred to as CCFL) and external electrode fluorescent lamps (hereinafter referred to as EEFL) arranged on the back of a liquid crystal panel on which images are displayed. The light is emitted as a backlight.

  For driving CCFL and EEFL, an inverter (DC / AC converter) that boosts a DC voltage of about 12 V and outputs it as an AC voltage, for example, is used. The inverter converts the current flowing through the CCFL into a voltage and feeds it back to the control circuit, and controls on / off of the switching element based on the fed back voltage. For example, Patent Literature 1 discloses a CCFL driving technique using such an inverter.

JP 2003-323994 A

  In order to generate the alternating voltage boosted by the inverter, it is necessary to intermittently apply a switching voltage to the primary coil of the transformer to store energy. In order to apply a switching voltage to the primary coil of the transformer, a method is adopted in which four switching transistors are arranged in a configuration called an H-bridge circuit or a full-bridge circuit and the switching voltage is applied to both ends of the primary coil. There is.

  When a switching voltage is generated using such an H-bridge circuit, the on / off timing of each switching transistor greatly affects the efficiency of the inverter. Further, among the switching transistors constituting the H-bridge circuit, when a pair of transistors connected in series between the input voltage and the ground are simultaneously turned on, a through current flows, so that switching control is performed with dead time. There is a need.

  The present invention has been made in view of these problems, and an object thereof is to provide an inverter that can flexibly set the ON / OFF timing of the switching transistor of the inverter using the H-bridge circuit.

  An inverter according to an aspect of the present invention includes a transformer, a first high-side transistor having one end connected to an input terminal to which an input voltage is applied, and the other end connected to a first terminal of a primary coil of the transformer, A first low-side transistor having one end connected to a fixed potential terminal having a fixed potential and the other end connected to the first terminal of the primary side coil; one end connected to the input terminal; the other end connected to the primary side coil A second high-side transistor connected to the second terminal, a second low-side transistor having one end connected to the potential fixing terminal and the other end connected to the second terminal of the primary coil, and the secondary side of the transformer A current-voltage converter that converts the coil current into a voltage and outputs it as a detection voltage, a triangular wave signal generator that generates a triangular wave signal, and an error that outputs an error voltage corresponding to the error between the detected voltage and a predetermined reference voltage An amplifier, and a logic control unit for controlling on / off of the first and second high-side transistors and the first and second low-side transistors based on the error voltage output from the error amplifier and the triangular wave signal generated by the triangular wave signal generating unit; . The logic control unit turns on the first high-side transistor and the second low-side transistor in the first period until the triangular wave signal reaches the error voltage from the bottom edge, and then the second period until the triangular wave signal reaches the peak edge. In the third period until the first high-side transistor is turned on and then the triangular wave signal reaches the bottom edge, the second high-side transistor is turned on, and the fourth time until the triangular wave signal reaches the error voltage again. In the period, the first low-side transistor and the second high-side transistor are turned on, and then the second high-side transistor is turned on in the fifth period until the triangular wave signal reaches the peak edge again. In the sixth period until reaching the edge, the first high-side transistor is turned on.

  In this aspect, the first and second high-side transistors and the first and second low-side transistors constituting the H-bridge circuit are driven by monitoring the current flowing in the secondary coil of the transformer and comparing it with the triangular wave signal. . As a result, the on / off timing of each transistor can be adjusted by adjusting the shape of the triangular wave signal.

  The logic control unit turns off the first high-side transistor during a period from when the triangular wave signal reaches the error voltage until a predetermined first off time elapses in the fifth period, and after the first off time elapses, One high side transistor may be turned on.

  If the first high-side transistor is kept off during the fifth period, the current flows through the body diode (parasitic diode) of the first high-side transistor, so that a voltage drop corresponding to the forward voltage Vf occurs, resulting in a large power loss. . Therefore, in the fifth period, after a predetermined first off-time has elapsed, the first high-side transistor is turned on, so that the current flowing through the body diode flows through the first high-side transistor, thereby reducing the power loss. Can be reduced. In addition, by appropriately setting the first off time, it is possible to prevent the through current from flowing due to the first high-side transistor and the first low-side transistor being simultaneously turned on.

  The logic control unit turns off the second high-side transistor during a period from when the triangular wave signal reaches the error voltage until a predetermined second off time elapses in the second period, and after the second off time elapses, 2 The high-side transistor may be turned on.

  Even in the second period, if the second high-side transistor is kept off, a current flows through the body diode and power loss increases. Therefore, power loss can be reduced by switching on the second high-side transistor after a predetermined second off time has elapsed. In addition, by appropriately setting the second off time, it is possible to prevent the through current from flowing due to the second high side transistor and the second low side transistor being simultaneously turned on.

  The transition time from the bottom edge to the peak edge of the triangular wave signal may be set in the range of 2 to 100 times, more preferably in the range of 5 to 15 times the transition time from the peak edge to the bottom edge. In this case, the ratio of the dead time to the energization time and the non-energization time of the primary coil can be suitably set.

  The logic control unit may invert the peak edge and the bottom edge to control on / off of the first and second high-side transistors and the first and second low-side transistors. Further, the first and second high-side transistors and the first and second low-side transistors may be constituted by MOSFETs.

  The triangular wave signal generation unit, the error amplifier, and the logic control unit may be integrated on a single semiconductor substrate. “Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate. By integrating these circuit elements as one LSI, the circuit area can be reduced.

  Another embodiment of the present invention is a light-emitting device. The light emitting device includes a fluorescent lamp and the above-described inverter that supplies a driving voltage to the fluorescent lamp. Two inverters may be provided at both ends of the fluorescent lamp, and drive voltages having opposite phases may be supplied. The fluorescent lamp may be a cold cathode fluorescent lamp or an external electrode fluorescent lamp.

  According to this aspect, since the luminous efficiency of the fluorescent lamp can be adjusted together with the efficiency of the inverter, the efficiency of the entire apparatus can be improved.

  Yet another embodiment of the present invention is a liquid crystal television. This liquid crystal television includes a liquid crystal panel and a plurality of the above-described light emitting devices disposed on the back surface of the liquid crystal panel.

  It should be noted that any combination of the above-described constituent elements, or those obtained by replacing constituent elements and expressions of the present invention with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  According to the inverter of the present invention, the on / off timing of the switching transistor of the inverter using the H bridge circuit can be set flexibly.

  FIG. 1 is a circuit diagram showing a configuration of a light emitting device 200 according to an embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of a liquid crystal television 300 on which the light emitting device 200 of FIG. 1 is mounted. The liquid crystal television 300 is connected to the antenna 310. The antenna 310 receives a broadcast wave and outputs a reception signal to the reception unit 304. The receiving unit 304 detects and amplifies the received signal and outputs it to the signal processing unit 306. The signal processing unit 306 outputs image data obtained by demodulating the modulated data to the liquid crystal driver 308. The liquid crystal driver 308 outputs image data to the liquid crystal panel 302 for each scanning line, and displays video and images. On the back surface of the liquid crystal panel 302, a plurality of light emitting devices 200 are arranged as a backlight. The light emitting device 200 according to this embodiment can be suitably used as a backlight of such a liquid crystal panel 302. Hereinafter, returning to FIG. 1, the configuration and operation of the light emitting device 200 will be described in detail.

  The light emitting device 200 according to the present embodiment includes an EEFL 210, a first inverter 100a, and a second inverter 100b. The EEFL 210 is disposed on the back surface of the liquid crystal panel 302. The first inverter 100a and the second inverter 100b are DC / AC converters, which convert an input voltage Vin output from a DC power source into an AC voltage and boost the voltage to the first terminal 212 and the second terminal 214 of the EEFL 210. The first drive voltage Vdrv1 and the second drive voltage Vdrv2 are supplied, respectively. The first drive voltage Vdrv1 and the second drive voltage Vdrv2 are alternating voltages that have opposite phases.

  Although one EEFL 210 is shown in FIG. 1, a plurality of EEFLs 210 may be arranged in parallel. Hereinafter, the configuration of the first inverter 100a and the second inverter 100b according to the present embodiment will be described. Since the first inverter 100a and the second inverter 100b have the same configuration, the following description will be made generically as the inverter 100 without distinguishing both.

  The inverter 100 includes an H bridge circuit 10, a transformer 12, a current-voltage conversion unit 14, a control circuit 20, and a capacitor C10.

  The H bridge circuit 10 includes four power transistors: a first high side transistor MH1, a first low side transistor ML1, a second high side transistor MH2, and a second low side transistor ML2.

  One end of the first high-side transistor MH1 is connected to the input terminal 102 to which the input voltage is applied, and the other end is connected to the first terminal of the primary side coil 12a of the transformer 12. The first low-side transistor ML1 has one end connected to a ground terminal having a fixed potential and the other end connected to the first terminal of the primary coil 12a. The second high-side transistor MH2 has one end connected to the input terminal 102 and the other end connected to the second terminal of the primary coil via the DC blocking capacitor C10. The second low-side transistor ML2 has one end connected to the ground terminal and the other end connected to the second terminal of the primary coil 12a via the DC blocking capacitor C10.

  The current-voltage converter 14 is provided between the secondary coil 12b of the transformer 12 and the ground. The current-voltage conversion unit 14 converts the current flowing through the secondary coil 12b, that is, the current flowing through the EEFL 210, into a voltage and outputs it as a detection voltage Vdet '. The current-voltage conversion unit 14 includes a rectifier circuit 16 and a filter 18.

  The rectifier circuit 16 includes a first diode D1, a second diode D2, and a resistor R1. The first diode D1 has an anode grounded and a cathode connected to one end of the secondary coil 12b. The anode of the second diode D2 is connected to the cathode of the first diode D1. The resistor R1 is provided between the cathode of the second diode D2 and the ground. The alternating current flowing through the secondary coil 12b is half-wave rectified by the first diode D1 and the second diode D2, and flows through the resistor R1. A voltage drop proportional to the current flowing through the secondary coil 12b occurs in the resistor R1. The rectifier circuit 16 outputs the voltage drop generated at the resistor R1 as the detection voltage Vdet.

  The filter 18 is a low-pass filter including a resistor R2 and a capacitor C1. The filter 18 feeds back the detection voltage Vdet ′ from which the high-frequency component of the detection voltage Vdet has been removed to the control circuit 20.

  The control circuit 20 controls on / off of the first high-side transistor MH1, the first low-side transistor ML1, the second high-side transistor MH2, and the second low-side transistor ML2 of the H bridge circuit 10 based on the feedback detection voltage Vdet ′. . A switching voltage is supplied to the primary coil 12 a of the transformer 12 by the control of the H-bridge circuit 10. As a result, energy conversion is performed by the transformer 12, and the first drive voltage Vdrv1 is supplied to the EEFL 210 connected to the secondary coil 12b.

  Hereinafter, the configuration of the control circuit 20 will be described. FIG. 3 is a circuit diagram showing a configuration of the control circuit 20 according to the present embodiment. The control circuit 20 includes an error amplifier 22, a PWM comparator 24, a triangular wave signal generation unit 30, and a logic control unit 40, and is a functional IC integrated on a single semiconductor substrate.

  The detection voltage Vdet ′ fed back from the current / voltage converter 14 is input to the non-inverting input terminal of the error amplifier 22, and a predetermined reference voltage Vref is input to the inverting input terminal. The reference voltage Vref is determined according to the light emission luminance of the EEFL 210. The error amplifier 22 outputs an error voltage Verr corresponding to an error between the detection voltage Vdet 'and the reference voltage Vref.

  The triangular wave signal generator 30 generates a triangular wave signal Vosc having a predetermined frequency. FIG. 4 is a circuit diagram illustrating a configuration example of the triangular wave signal generation unit 30. The triangular wave signal generation unit 30 includes a first comparator 32, a second comparator 34, an RS flip-flop 36, a first constant current source 38a, a second constant current source 38b, and a capacitor C2.

  Since the triangular wave signal generation unit 30 has a general configuration, only the configuration and operation will be briefly described. The first constant current source 38a is a current source for charging the capacitor C2 whose one end is grounded, and the second constant current source 38b is a current source for discharging the capacitor C2. The voltage appearing on the capacitor C2 is output as the triangular wave signal Vosc.

  The first comparator 32 compares the potential of the triangular wave signal Vosc with the maximum voltage Vmax that sets the peak value of the triangular wave signal to be output. The first comparator 32 outputs a high level when Vosc> Vmax. The second comparator 34 compares the potential of the triangular wave signal Vosc with the minimum voltage Vmin that sets the bottom value of the triangular wave signal to be output. The second comparator 34 outputs a high level when Vosc <Vmin.

  The output signals of the first comparator 32 and the second comparator 34 are input to the set terminal and the reset terminal of the RS flip-flop 36, respectively. The output signal Vq of the RS flip-flop 36 is output to the first constant current source 38a, and the inverted output signal * Vq is output to the second constant current source 38b. The first constant current source 38a is turned on when the output signal Vq is at a high level, and charges the capacitor C2 with the constant current Ic1. The second constant current source 38b is turned on when the inverted output signal * Vq is at a high level, and discharges the capacitor C2 with the constant current Ic2.

  The triangular wave signal generator 30 configured as described above outputs a triangular wave signal Vosc having a peak voltage set to Vmax and a bottom voltage set to Vmin. Further, the output signal Vq of the RS flip-flop 36 is output to the logic control unit 40 as a periodic signal. The triangular wave signal generation unit 30 may be configured using a hysteresis comparator.

  Returning to FIG. The PWM comparator 24 compares the error voltage Verr output from the error amplifier 22 with the triangular wave signal Vosc output from the triangular wave signal generator 30, and is high when Verr <Vosc and low when Verr> Vosc. A pulse width modulation signal (hereinafter referred to as PWM signal) Vpwm is generated. The PWM signal Vpwm is input to the logic control unit 40 together with the triangular wave signal Vosc and the periodic signal Vq.

  The logic control unit 40 is based on the PWM signal Vpwm, the triangular wave signal Vosc, and the periodic signal Vq. Controls on / off. Hereinafter, the logic control unit 40 will be described.

  The logic control unit 40 controls the H bridge circuit 10 with two cycles of the triangular wave signal Vosc output from the triangular wave signal generation unit 30 as one cycle. More specifically, the two cycles of the triangular wave signal Vosc are divided into six first to sixth periods to perform switching control. 5A to 5H are time charts showing the operating state of the inverter 100. FIG. 5A shows the error voltage Verr and the triangular wave signal Vosc, FIG. 5B shows the PWM signal Vpwm, FIG. 5C shows the periodic signal Vq, and FIGS. The state of the first high-side transistor MH1, the second high-side transistor MH2, the first low-side transistor ML1, and the second low-side transistor ML2 is shown in FIG. 5 (h), where the first terminal of the primary side coil 12a of the transformer 12 is shown. The potential Vsw is shown. In FIGS. 4D to 4G, a high level indicates that the transistor is on, and a low level indicates that the transistor is off. In the same figure, the vertical axis and the horizontal axis are appropriately enlarged or reduced for the sake of brevity.

  First, the division from the first period φ1 to the sixth period φ6 will be described. The logic control unit 40 sets the period until the triangular wave signal Vosc reaches the error voltage Verr from the bottom edge as the first period φ1. Next, a period until the triangular wave signal Vosc reaches the peak edge is defined as a second period φ2. Next, a period until the triangular wave signal Vosc reaches the bottom edge is defined as a third period φ3. Next, a period until the triangular wave signal Vosc reaches the error voltage Verr again is a fourth period φ4. Next, a period until the triangular wave signal Vosc reaches the peak edge again is a fifth period φ5. Next, a period until the triangular wave signal Vosc reaches the bottom edge again is a sixth period φ6. This division can be configured using a general logic circuit based on the PWM signal Vpwm and the periodic signal Vq.

Next, the on / off state of the transistors of the H bridge circuit 10 from the first period φ1 to the sixth period φ6 will be described.
In the first period φ1, the logic control unit 40 turns on the first high-side transistor MH1 and the second low-side transistor ML2, and turns off the other transistors. In the subsequent second period φ2, the first high-side transistor MH1 is turned on and the other transistors are turned off. In the subsequent third period φ3, the second high-side transistor MH2 is turned on and the other transistors are turned off. In the subsequent fourth period φ4, the first low-side transistor ML1 and the second high-side transistor MH2 are turned on, and the other transistors are turned off. In the subsequent fifth period φ5, the second high-side transistor MH2 is turned on and the other transistors are turned off. In the subsequent sixth period φ6, the first high-side transistor MH1 is turned on and the other transistors are turned off. Thereafter, the process returns to the first period φ1.

  The operation of inverter 100 according to the present embodiment configured as described above will be described. FIGS. 6A to 6F are circuit diagrams showing a current flow in the H-bridge circuit 10 of the inverter 100 according to the present embodiment. FIGS. 6A to 6F show the on / off state of each transistor and the state of the coil current Isw in the first period φ1 to the sixth period φ6, respectively.

  As shown in FIG. 6A, in the first period φ1, the first high-side transistor MH1 and the second low-side transistor ML2 are turned on. As a result, the coil current Isw flows through the path of the first high side transistor MH1, the primary side coil 12a, and the second low side transistor ML2. At this time, the switching voltage Vsw is substantially equal to the input voltage Vin. In the first period φ1, the coil current Isw gradually increases.

  In the subsequent second period φ2, as shown in FIG. 6B, the second low-side transistor ML2 is turned off and only the first high-side transistor MH1 is turned on. As a result, the regenerative current flows through the body diode of the second high-side transistor MH2 due to the energy stored in the primary coil 12a. During this time, the switching voltage Vsw maintains a voltage substantially equal to the input voltage.

  Next, in the third period φ3, as shown in FIG. 6C, the second high-side transistor MH2 is turned on, and the first high-side transistor MH1 is turned off. At this time, the coil current Isw supplied from the first high-side transistor MH1 in the second period φ2 is supplied from the ground via the body diode of the first low-side transistor ML1. The switching voltage Vsw in the third period φ3 is a negative value that is lower than the ground potential (0 V) by the forward voltage Vf of the body diode of the first low-side transistor ML1. In addition, the energy stored in the primary coil 12a in the first period φ1 is all transferred to the secondary coil 12b in the third period φ3, and the coil current Isw becomes zero.

  In the subsequent fourth period φ4, as shown in FIG. 6D, the first low-side transistor ML1 is switched on while the second high-side transistor MH2 is kept on. At this time, the switching voltage Vsw is fixed near the ground potential. The coil current Isw flows from the right side to the left side of the primary side coil 12a through the path of the second high side transistor MH2, the primary side coil 12a, and the first low side transistor ML1. In the fourth period φ4, the coil current Isw gradually increases.

  In the subsequent fifth period φ5, as shown in FIG. 6E, the first low-side transistor ML1 is switched off while the second high-side transistor MH2 is kept on. As a result, the coil current Isw that has flowed through the first low-side transistor ML1 in the fourth period φ4 flows through the body diode of the first high-side transistor MH1. At this time, the switching voltage Vsw is higher than the input voltage Vin by the forward voltage Vf of the body diode.

  In the subsequent sixth period φ6, as shown in FIG. 6F, the first high-side transistor MH1 is switched on and the second high-side transistor MH2 is turned off. At this time, the coil current Isw supplied from the second high side transistor MH2 in the fifth period φ5 is supplied from the ground via the body diode of the second low side transistor ML2. The switching voltage Vsw in the sixth period φ6 is substantially equal to the input voltage Vin. The energy stored in the primary coil 12a in the fourth period φ4 is all transferred to the secondary coil 12b in the sixth period φ6, and the coil current Isw becomes zero.

  According to the inverter 100 according to the present embodiment, the transistors constituting the H-bridge circuit 10 are driven by monitoring the current flowing through the secondary coil 12b of the transformer 12 and comparing it with the triangular wave signal Vosc. Therefore, by adjusting the shape of the triangular wave signal Vosc, the on / off timing of each transistor can be flexibly adjusted.

  For example, in the present embodiment, the lengths of the first period φ1 and the fourth period φ4 depend on the slope when transitioning from the bottom edge to the peak edge of the triangular wave signal Vosc. This inclination can be changed by adjusting the constant current Ic1 in the triangular wave signal generation unit 30 of FIG.

  In the present embodiment, the transition period from the peak edge to the bottom edge of the triangular wave signal Vosc is the third period φ3 and the sixth period φ6. The lengths of the third period φ3 and the sixth period φ6 can be changed by adjusting the constant current Ic2 in the triangular wave signal generation unit 30 of FIG.

  Here, the energy stored in the primary coil 12a depends on the length of the first period φ1 and the fourth period φ4. The energy stored in the first period φ1 and the fourth period φ4 is transferred to the secondary coil 12b in the third period φ3 and the sixth period φ6. Therefore, it is possible to drive with high efficiency by adjusting the shape and cycle of the triangular wave signal Vosc in accordance with the characteristics of the transformer 12 and the characteristics of the EEFL 210 to be driven.

  Note that the transition time from the bottom edge to the peak edge of the triangular wave signal Vosc is set in the range of 2 to 100 times, more preferably in the range of 5 to 15 times the transition time from the peak edge to the bottom edge. Is desirable. Which value is set may be determined according to the frequency of the triangular wave, the characteristics of the transformer, and the like. By designing the triangular wave signal Vosc within this range, it is possible to drive with high efficiency.

  The embodiments are exemplifications, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. .

For example, the following modification can be considered as the control of the H bridge circuit 10 by the logic control unit 40.
In this modification, the logic control unit 40, during the fifth period φ25, during the period from when the triangular wave signal Vosc reaches the error voltage Verr until the predetermined first off time Toff1 elapses, the first high-side transistor MH1. And the first high-side transistor MH1 is turned on after the first off time Toff1 has elapsed.

  Further, in the second period φ2, the logic control unit 40 also turns off the second high-side transistor MH2 during a period from when the triangular wave signal Vosc reaches the error voltage Verr until a predetermined second off time Toff2 elapses. The second high-side transistor MH2 is turned on after the second off time Toff2 has elapsed. The first off time Toff1 and the second off time Toff2 may be set to about 50 ns to 200 ns according to the period of the triangular wave signal Vosc.

  7A to 7E are time charts showing operation states of the inverter 100 according to the modification. 7A shows the first high-side transistor MH1, FIG. 7B shows the second high-side transistor MH2, FIG. 7C shows the first low-side transistor ML1, and FIG. The second low-side transistor ML2 is in an on / off state, and FIG. 8E shows the switching voltage Vsw.

  If the second high-side transistor MH2 is kept off during the fifth period φ5, the coil current Isw flows through the body diode (parasitic diode) of the second high-side transistor MH2, so that a voltage drop corresponding to the forward voltage Vf occurs. Power loss increases. Therefore, in the present modification, the first high-side transistor MH1 is turned on after a predetermined first off time Toff1 has elapsed in the fifth period φ5. As a result, as shown in FIG. 7E, the switching voltage Vsw drops to the input voltage Vin after the first off time Toff1 has elapsed. At this time, the coil current Isw flowing in the body diode of the first high-side transistor MH1 flows in the first high-side transistor MH1, so that power loss can be reduced. Further, by appropriately setting the first off time Toff1, it is possible to prevent the through current from flowing due to the first high-side transistor MH1 and the first low-side transistor ML1 being simultaneously turned on.

  Similarly, in the second period φ2, if the second high-side transistor MH2 is kept off, a current flows through the body diode, so that power loss increases. Accordingly, by turning on the second high-side transistor MH2 after a predetermined second off time Toff2 has elapsed, it is possible to reduce power loss by causing a current to flow through the second high-side transistor MH2.

  The first off time Toff1 and the second off time Toff2 may be determined according to the characteristics of the transformer 12, and are preferably set in the range of about 30 ns to 150 ns. More preferably, power loss can be reduced when it is set in the range of 50 ns to 100 ns.

  In the present embodiment, the control circuit 20 may be integrated as a whole, or a part thereof may be composed of discrete components or chip components. Further, the control circuit 20 may be integrated including the H bridge circuit 10. What part and how much to integrate may be determined by the specifications, cost, occupied area, etc. of the inverter 100.

  In the present embodiment, the setting of the logic values of the high level and low level of the logic circuit is an example, and can be freely changed by appropriately inverting it with an inverter or the like. For example, the logic control unit 40 may control on / off of the transistors of the H bridge circuit 10 by inverting the peak edge and the bottom edge.

  In the embodiment, the case where the high-side transistor of the transistors constituting the H-bridge circuit 10 is configured by an N-channel MOSFET has been described, but a P-channel MOSFET may be used.

  In the embodiment, a case has been described in which the inverter 100 is connected to both ends of the EEFL 210 in the light emitting device 200 and is driven by a driving voltage having a reverse phase. However, the present invention is not limited to this. The fluorescent tube to be driven is not limited to EEFL, and may be another fluorescent tube such as CCFL. Further, the load driven by the inverter 100 according to the present embodiment is not limited to the fluorescent tube, and can be applied to driving various devices that require an alternating high voltage.

It is a circuit diagram which shows the structure of the light-emitting device which concerns on embodiment. It is a block diagram which shows the structure of the liquid crystal television in which the light-emitting device of FIG. 1 is mounted. It is a circuit diagram which shows the structure of the control circuit which concerns on embodiment. It is a circuit diagram which shows the structural example of a triangular wave signal generation part. FIGS. 5A to 5H are time charts showing operation states of the inverter of FIG. FIGS. 6A to 6F are circuit diagrams showing the current flow of the H-bridge circuit of the inverter of FIG. It is a time chart which shows the operation state of the inverter which concerns on a modification.

Explanation of symbols

  10 H bridge circuit, 12 transformer, 12a primary side coil, 12b secondary side coil, 14 current voltage conversion unit, 22 error amplifier, 30 triangular wave signal generation unit, 40 logic control unit, 100 inverter, 200 light emitting device, 212 first 1 terminal, 214 second terminal, 300 liquid crystal television, 302 liquid crystal panel, MH1 first high side transistor, MH2 second high side transistor, ML1 first low side transistor, ML2 second low side transistor.

Claims (13)

A transformer,
A first high-side transistor having one end connected to an input terminal to which an input voltage is applied and the other end connected to a first terminal of a primary coil of the transformer;
A first low-side transistor having one end connected to a fixed potential terminal having a fixed potential and the other end connected to a first terminal of the primary coil;
A second high-side transistor having one end connected to the input terminal and the other end connected to the second terminal of the primary coil;
A second low-side transistor having one end connected to the potential fixing terminal and the other end connected to the second terminal of the primary coil;
A current-voltage converter that converts the current of the secondary coil of the transformer into a voltage and outputs the voltage as a detection voltage;
A triangular wave signal generator for generating a triangular wave signal;
An error amplifier that outputs an error voltage corresponding to an error between the detection voltage and a predetermined reference voltage;
Logic for controlling on / off of the first and second high-side transistors and the first and second low-side transistors based on the error voltage output from the error amplifier and the triangular wave signal generated by the triangular wave signal generator. A control unit,
The logic control unit
In the first period until the triangular wave signal reaches the error voltage from the bottom edge, the first high-side transistor and the second low-side transistor are turned on,
Next, in the second period until the triangular wave signal reaches the peak edge, the first high-side transistor is turned on,
Next, in the third period until the triangular wave signal reaches the bottom edge, the second high-side transistor is turned on,
Next, in the fourth period until the triangular wave signal reaches the error voltage again, the first low-side transistor and the second high-side transistor are turned on,
Next, in the fifth period until the triangular wave signal reaches the peak edge again, the second high-side transistor is turned on,
Next, in the sixth period until the triangular wave signal reaches the bottom edge again, the first high-side transistor is turned on.   In the fifth period, the logic control unit turns off the first high-side transistor during a period from when the triangular wave signal reaches the error voltage until a predetermined first off time elapses, The inverter according to claim 1, wherein the first high-side transistor is turned on after an off time has elapsed.   In the second period, the logic control unit turns off the second high-side transistor during a period from when the triangular wave signal reaches the error voltage until a predetermined second off time elapses, The inverter according to claim 1, wherein the second high-side transistor is turned on after an off time has elapsed.   4. The transition time from the bottom edge to the peak edge of the triangular wave signal is set in a range of 2 to 100 times the transition time from the peak edge to the bottom edge. Inverter.   The logic control unit reverses the peak edge and the bottom edge to control on / off of the first and second high-side transistors and the first and second low-side transistors. 4. The inverter according to any one of 4.   6. The inverter according to claim 1, wherein the first and second high-side transistors and the first and second low-side transistors are constituted by MOSFETs.   The inverter according to claim 1, wherein the triangular wave signal generation unit, the error amplifier, and the logic control unit are integrated on a single semiconductor substrate. A fluorescent lamp,
The inverter according to any one of claims 1 to 7, wherein a driving voltage is supplied to the fluorescent lamp;
A light emitting device comprising:   The light emitting device according to claim 8, wherein the number of the inverters is two, and the inverters are respectively provided at both ends of the fluorescent lamp and supply driving voltages having opposite phases to each other.   10. The light emitting device according to claim 8, wherein the fluorescent lamp is a cold cathode fluorescent lamp.   The light emitting device according to claim 8 or 9, wherein the fluorescent lamp is an external electrode fluorescent lamp. LCD panel,
A plurality of light emitting devices according to any one of claims 8 to 11 disposed on a back surface of the liquid crystal panel;
A liquid crystal television comprising: An inverter driving method comprising:
Converting the current of the secondary coil of the transformer into a voltage and converting it into a detection voltage;
Generating an error voltage according to an error between the detection voltage and a predetermined reference voltage;
A control step for controlling on / off of the first and second high-side transistors and the first and second low-side transistors constituting the H-bridge circuit based on the error voltage and the triangular wave signal;
In the control step,
In the first period until the triangular wave signal reaches the error voltage from the bottom edge, the first high-side transistor and the second low-side transistor are turned on,
Next, in the second period until the triangular wave signal reaches the peak edge, the first high-side transistor is turned on,
Next, in the third period until the triangular wave signal reaches the bottom edge, the second high-side transistor is turned on,
Next, in the fourth period until the triangular wave signal reaches the error voltage again, the first low-side transistor and the second high-side transistor are turned on,
Next, in the fifth period until the triangular wave signal reaches the peak edge again, the second high-side transistor is turned on,
Next, in the sixth period until the triangular wave signal reaches the bottom edge again, the first high-side transistor is turned on.

Images