JP2007142873A - Carrier extraction circuit, rf tag, and contactless ic card - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a carrier extraction circuit, a RF tag, and a contactless IC card capable of avoiding a malfunction of an internal circuit even when a change in the amplitude of an AC signal induced in an antenna is great. <P>SOLUTION: The carrier extraction circuit connectable to the antenna receiving an electromagnetic wave, in one terminal a of which a first AC signal INa is induced and in the other terminal b of which a second AC signal INb inverse to the first AC signal INa is induced, includes a binary circuit 31a for binarizing the first and second AC signals INa, INb to output first and second binary pulses BINP, BINM; a pulse generating circuit 32 for generating a first trigger pulse TRGP synchronously with the first binary pulse BINP and generating a second trigger pulse TRGM synchronously with the second binary pulse BINM; and an output circuit 33a for receiving the first and second trigger pulses TRGP, TRGM and outputting a clock CLK with a fixed duty ratio. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an RF tag and a non-contact IC card that obtains electric power by electromagnetic coupling with a reader / writer (R / W), and in particular, a carrier extraction circuit that can extract an AC signal (carrier) induced in an antenna, and an RF tag And a non-contact IC card.

  In RF tags and non-contact IC cards, it is difficult to obtain a high-accuracy clock using a crystal oscillator or the like due to a lack of a power supply and restrictions on the housing. For this reason, a method of extracting a reception carrier from an electromagnetic wave (magnetic field) received by an antenna and using it as an operation clock of an internal circuit may be used. In this case, an inverter that binarizes the AC signal generated by the main carrier induced at one end of the antenna and a 1/2 frequency divider that divides the binarized AC signal by 1/2 are provided (for example, Patent Documents). 1).

Since the amplitude of the AC signal induced in the antenna varies greatly depending on the reception distance, if the signal is binarized by an inverter having a fixed threshold voltage Vth, the clock duty ratio varies. Furthermore, since the frequency of the clock becomes 1/2 of the carrier frequency by dividing the binarized AC signal by 1/2, this hinders the high-speed operation of the internal circuit. In addition, the internal circuit may malfunction due to fluctuations in the duty ratio of the clock, and a highly reliable RF tag and non-contact IC card cannot be realized.
JP 2002-269517 A (FIG. 6)

  The present invention provides a carrier extraction circuit, an RF tag, and a non-contact IC card that can avoid malfunction of an internal circuit even when a change in the amplitude of an AC signal induced in an antenna is large.

  According to one aspect of the present invention, a first AC signal is induced at one end by receiving electromagnetic waves, and a second AC signal having a phase opposite to that of the first AC signal is induced at the other end. A possible carrier extraction circuit, which binarizes first and second AC signals and outputs first and second binarized pulses and is synchronized with the first binarized pulse The first trigger pulse is generated, the second trigger pulse is generated in synchronization with the second binarization pulse, and the duty ratio is fixed with the first and second trigger pulses as inputs. A carrier extraction circuit is provided that includes an output circuit that outputs the clock of the carrier.

  According to another aspect of the present invention, an antenna in which a first AC signal is induced at one end by receiving an electromagnetic wave, and a second AC signal having a phase opposite to the first AC signal is induced at the other end; A binarization circuit that binarizes the first and second AC signals and outputs the first and second binarization pulses, and a first trigger pulse in synchronization with the first binarization pulse. A pulse generation circuit that generates and generates a second trigger pulse in synchronization with the second binarization pulse; and an output circuit that outputs a clock with a fixed duty ratio by using the first and second trigger pulses as inputs An RF tag including an internal circuit that operates in synchronization with a clock is provided.

  According to still another aspect of the present invention, an antenna in which a first AC signal is induced at one end by receiving an electromagnetic wave and a second AC signal having a phase opposite to that of the first AC signal is induced at the other end. A binarization circuit that binarizes the first and second AC signals and outputs the first and second binarization pulses, and a first trigger pulse in synchronization with the first binarization pulse Generating circuit that generates a second trigger pulse in synchronization with the second binarization pulse, and an output circuit that outputs a clock with a fixed duty ratio by using the first and second trigger pulses as inputs And a non-contact IC card provided with an internal circuit that operates in synchronization with the clock.

  According to the present invention, it is possible to provide a carrier extraction circuit, an RF tag, and a non-contact IC card that can avoid malfunction of the internal circuit even when the change in the amplitude of the AC signal induced in the antenna is large.

  Next, an embodiment of the present invention will be described with reference to the drawings. In the description of the drawings in the following embodiments, the same or similar parts are denoted by the same or similar reference numerals.

  As shown in FIG. 1, the RF tag 1 according to the embodiment of the present invention includes an antenna 11 and an IC 12 connected to the antenna 11. The RF tag 1 is not limited to a card type shape, and may be a box type, a cylindrical type, a disk type, a stick type, a label type, or the like. For example, the antenna 11 is formed so as to surround the IC 12. The IC 12 includes a carrier extraction circuit 121a, a rectifier circuit 122, a constant voltage circuit 123, a demodulation circuit 124, and an internal circuit 125. The carrier extraction circuit 121a extracts the carrier component of the electromagnetic wave received by the antenna 11 from the R / W 2 in order to generate the clock CLK as the operation clock of the internal circuit 125. Due to the electromagnetic coupling with the antenna 22 on the R / W2 side, the first AC signal INa is induced in the RF tag 1 at one end a of the antenna 11, and the second AC signal INb having a phase opposite to the first AC signal INa is generated. It is induced at the other end b of the antenna 11. The binarization circuit 31a binarizes the first and second AC signals INa and INb and outputs first and second binarization pulses BINP and BINM. The pulse generation circuit 32 generates a first trigger pulse TRGP in synchronization with the first binarization pulse BINP, and generates a second trigger pulse TRGM in synchronization with the second binarization pulse BINM. The output circuit 33a receives the first and second trigger pulses TRGP and TRGM and outputs a clock CLK with a fixed duty ratio.

  In this way, the carrier extraction circuit 121a uses the AC signals INa and INb generated at both ends a and b of the antenna 11, so that the clock CLK having a good duty ratio regardless of the amplitude fluctuation of the AC signals INa and INb. Can be generated.

  The first AC signal INa induced at one end a of the antenna 11 is supplied to the rectifier circuit 122 and the binarization circuit 31a through the terminal 13 of the IC 12. Similarly, the second AC signal INb induced at the other end b of the antenna 11 on the RF tag 1 side is supplied to the rectifier circuit 122 and the binarization circuit 31a via the terminal 13 of the IC 12.

  The rectifier circuit 122 rectifies the first and second AC signals INa and INb and outputs the rectified signal REC to the constant voltage circuit 123 and the demodulator circuit 124. The constant voltage circuit 123 generates the internal operating voltage VDD by making the rectified signal REC constant (DC voltage). The generated internal operation voltage VDD is used as a power supply voltage for the carrier extraction circuit 121a, the demodulation circuit 124, and the internal circuit 125, and as a result, a batteryless operation is realized.

  Further, the demodulation circuit 124 demodulates the reception data from the rectified signal REC and transmits the demodulated reception data to the internal circuit 125. The internal circuit 125 includes a logic circuit, a ROM, and a RAM (not shown), for example. The ROM stores a program for executing an authentication process or the like executed in the logic circuit. On the other hand, the RAM is used as a storage area and a work area for data used during program execution processing in the logic circuit.

  Note that a load switching method is used when data is transmitted to the R / W2. In the load switching method, the load on the antenna 22 on the R / W2 side is increased or decreased by changing the impedance of the antenna 11 on the RF tag 1 side. As a result, carrier amplitude fluctuation is detected as transmission data from the RF tag 1 in the antenna 22 on the R / W 2 side.

A specific configuration example of the antenna 11, the rectifier circuit 122, the binarization circuit 31a, the pulse generation circuit 32, and the output circuit 33a illustrated in FIG. 1 will be described below with reference to FIG. The antenna 11 is configured as a parallel resonant circuit including a coil (power receiving coil) L ₁ and a capacitor C, for example. The rectifier circuit 122 is configured as a diode bridge including _first to fourth diodes D _{1 to} D ₄ that are bridge-connected.

The binarization circuit 31 a includes first and second p-type channel MOS transistors (hereinafter simply referred to as “pMOS transistors”) P ₁ and P _2, and first and second n-type channel MOS transistors ( Hereinafter, it is simply referred to as “nMOS transistor”.) N ₁ and N ₂ and two inverters 311 and 312 are provided. The gates of the first pMOS transistor P ₁ and the first nMOS transistor N ₁ are connected to the terminal 13, and the gates of the second pMOS transistor P ₂ and the second nMOS transistor N ₂ are connected to the terminal 14. . Connection node n ₁ of the first pMOS transistor P ₁ and the first of each drain of the nMOS transistor N ₁ is connected to the input of an inverter 311, a second pMOS transistor P ₂ and second drains of the nMOS transistor N ₂ the connection node n ₂ is connected to the input of inverter 312.

The first pMOS transistor P ₁ and the first nMOS transistor N ₁ constitute a first CMOS inverter, and the second pMOS transistor P ₂ and the second nMOS transistor N ₂ constitute a second CMOS inverter. Is done. Each threshold voltage Vth of the first and second CMOS inverters is designed to be about ½ VDD, for example. The inverters 311 and 312 are used for waveform shaping of the first and second binarized pulses BINP and BINM, but the inverters 311 and 312 can be omitted.

A signal obtained by binarizing and inverting the first AC signal INa is generated at the connection node n ₁ . A signal obtained by binarizing and inverting the second AC signal INb is generated at the connection node n ₂ . The inverter 311 inverts the logic of the signal generated at the connection node n ₁ and outputs the first binarized pulse BINP. Inverter 312 inverts the logic of the signal generated at connection node n ₂ and outputs a second binarized pulse BINM. Therefore, first and second binarized pulses BINP and BINM having frequencies equal to the frequencies of the first and second AC signals INa and INb are obtained.

  The pulse generation circuit 32 includes first and second delay circuits 321 and 322, and first and second NAND circuits 323 and 324. The inputs of the first and second delay circuits 321 and 322 are connected to the outputs of the inverters 311 and 312, respectively. The input of the first NAND circuit 323 is connected to each output of the inverter 311 and the first delay circuit 321. The input of the second NAND circuit 324 is connected to the outputs of the inverter 312 and the second delay circuit 322.

  The first delay circuit 321 delays the first binarized pulse BINP for a certain time. The first NAND circuit 323 performs NAND operation on the first binarized pulse BINP and the inverted signal of the output signal of the first delay circuit 321. As a result, the first trigger pulse TRGP becomes L level only when the output signal of the first delay circuit 321 is low (L) level and the first binarization pulse BINP is high (H) level.

  Similarly, the second delay circuit 322 delays the second binarized pulse BINM for a certain time. The second NAND circuit 324 performs NAND operation on the second binarized pulse BINM and the inverted signal of the output signal of the second delay circuit 322. As a result, the second trigger pulse TRGM becomes L level only during the period when the output signal of the second delay circuit 322 is L level and the second binarized pulse BINM is H level.

  The output circuit 33 a is configured as an RS latch circuit including first and second NAND circuits 331 and 332. The input of the first NAND circuit 331 of the output circuit 33a is connected to the output of the first NAND circuit 323 of the pulse generation circuit 32 and the output of the second NAND circuit 332 of the output circuit 33a. The input of the second NAND circuit 332 of the output circuit 33a is connected to the output of the second NAND circuit 324 of the pulse generation circuit 32 and the output of the first NAND circuit 331 of the output circuit 33a. The output signal of the first NAND circuit 331 of the output circuit 33a is used as a clock CLK to the internal circuit 125 shown in FIG.

  Therefore, the output circuit 33a performs the same operation as dividing the combined frequency of the first and second trigger pulses TRGP and TRGM by 1/2. Therefore, a carrier extraction circuit 121a that has a good duty ratio and can generate a clock CLK having a frequency equal to each frequency of the first and second AC signals INa and INb is configured.

  The operation of the carrier extraction circuit 121a will be described below with reference to the time charts shown in FIGS. First, the case where the distance between the R / W 2 and the RF tag 1 shown in FIG. 1 is relatively long, that is, the case where the amplitudes of the first and second AC signals INa and INb are relatively small will be described with reference to FIG. To do. As shown in FIG. 3A, the first and second AC signals INa and INb have the same amplitude and the opposite phases (180 ° shift).

  (A1) First, in the period from time t2 to time t3 in FIG. 3, the amplitude of the first AC signal INa shown in FIG. 3A exceeds the threshold voltage Vth, and the binarization circuit 31a changes to the state shown in FIG. The first binarized pulse BINP shown in FIG. 2 is raised from the L level to the H level. As a result, as shown in FIG. 3C, the pulse generation circuit 32 generates the L-level first trigger pulse TRGP for a certain period from time t2. The output circuit 33a raises the clock CLK from the L level to the H level as shown in FIG. 3F by the falling edge of the first trigger pulse TRGP.

  (B1) In the period from time t4 to time t5 in FIG. 3, the amplitude of the second AC signal INb shown in FIG. 3A exceeds the threshold voltage Vth, and the binarization circuit 31a is shown in FIG. The second binarized pulse BINM is raised from the L level to the H level. As a result, as shown in FIG. 3E, the pulse generation circuit 32 generates the L-level second trigger pulse TRGM for a certain period from time t4. The output circuit 33a causes the clock CLK to fall from the H level to the L level as shown in FIG. 3 (f) by the falling edge of the second trigger pulse TRGP.

  In the period after (C1), the same operations as in (A1) and (B1) are performed alternately. Therefore, as shown in FIG. 3, the clock CLK having the same frequency as the AC signals INa and INb induced at both ends a and b of the antenna 11 can be generated, which contributes to high-speed operation of the internal circuit 125. it can.

  Next, referring to the time chart shown in FIG. 4, when the distance between the R / W 2 and the RF tag 1 is relatively short, that is, the amplitudes of the first and second AC signals INa and INb are relatively The operation of the carrier extraction circuit 121a when it is large will be described.

  (A2) First, in the period from time t1 to time t4 in FIG. 4, the amplitude of the first AC signal INa shown in FIG. 4A exceeds the threshold voltage Vth, and the binarization circuit 31a is replaced with the one shown in FIG. The first binarized pulse BINP shown in FIG. 2 is raised from the L level to the H level. As a result, as shown in FIG. 4C, the pulse generation circuit 32 generates the L-level first trigger pulse TRGP for a certain period from time t1. The output circuit 33a raises the clock CLK from the L level to the H level as shown in FIG. 4F by the falling edge of the first trigger pulse TRGP.

  Here, the pulse width of the first binarized pulse BINP shown in FIG. 4B (period from time t1 to t4) is the half cycle of the clock CLK shown in FIG. 4F (period from time t1 to t3). Bigger than). However, since the pulse generation circuit 32 generates the first trigger pulse TRGP having a pulse width equal to or less than ½ of the pulse width of the first binarized pulse BINP, the output circuit 33a is stably operated. Can do.

  (B2) During the period from time t3 to time t6 in FIG. 4, the amplitude of the second AC signal INb shown in FIG. 4A exceeds the threshold voltage Vth, and the binarization circuit 31a is shown in FIG. The second binarized pulse BINM is raised from the L level to the H level. As a result, as shown in FIG. 4E, the pulse generation circuit 32 generates the L-level second trigger pulse TRGM for a certain period from time t3. The output circuit 33a raises the clock CLK from the H level to the L level as shown in FIG. 4F by the falling edge of the second trigger pulse TRGP.

  The pulse width (period from time t3 to t6) of the second binarized pulse BINM shown in FIG. 4C is larger than the half cycle of the clock CLK shown in FIG. However, since the pulse generation circuit 32 generates the second trigger pulse TRGM having a pulse width equal to or less than ½ of the pulse width of the second binarized pulse BINM, the output circuit 33a can be operated stably. Can do.

  In the period after (C2), the same operations as in (A2) and (B2) are performed alternately.

  As described above in detail, according to the carrier extraction circuit 121a and the RF tag 1 according to the embodiment of the present invention, the clock CLK having a good duty ratio can be obtained over a wide range that can be communicated with the R / W2. The operation margin of the internal circuit 125 can be maintained large. Therefore, even when the change in the amplitude of the AC signal induced in the antenna 11 is large, it is possible to avoid the malfunction of the internal circuit 125.

(Modification)
As shown in FIG. 5, the carrier extraction circuit 121b according to the modification of the embodiment of the present invention is different from that of FIG. 2 in the configuration of the binarization circuit 31b and the output circuit 33b. Specifically, the binarization circuit 31b shown in FIG. 5 uses first and second resistors R ₁ and R ₂ instead of the first and second pMOS transistors P ₁ and P ₂ of FIG. ing.

  The output circuit 33 b includes a NAND circuit 333 and a toggle-flip flop (T-FF) 334. An input of the NAND circuit 333 is connected to outputs of the first and second NAND circuits 323 and 324. In the T-FF 334, the internal operating voltage VDD is input to the T terminal, the output signal of the NAND circuit 333 is input to the CK terminal, and the clock CLK is output from the output Q. An EXOR circuit may be used instead of the NAND circuit 333.

According to the carrier extraction circuit 121a according to the modification of the embodiment of the present invention, the same effect as the carrier extraction circuit 121a shown in FIG. 2 can be obtained. Further, in the binarization circuit 31b, the first and second resistors R ₁ and R ₂ are used in place of the first and second pMOS transistors P ₁ and P _2. Can be simplified.

(Other embodiments)
As mentioned above, although this invention was described by embodiment, it should not be understood that the description and drawing which form a part of this indication limit this invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the above description of the embodiment, an example in which the IC 12 is mounted on the RF tag 1 has been described. However, the antenna 11 and the IC 12 shown in FIG. 1 can be covered with a card substrate to form a non-contact IC card. In this case, the internal circuit 125 having a higher function than that of the RF tag can be used.

  Further, the IC 12 may be mounted on a portable information terminal such as a mobile phone terminal, a personal handy phone (PHS), or a personal digital assistance (PDA). In this case, since a power supply voltage can be supplied to the IC 12 from a power supply (battery) included in the portable information terminal, it is preferable to use a limiter circuit or the like instead of the constant voltage circuit 123.

  Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters in the scope of claims reasonable from this disclosure.

It is a block diagram which shows the structural example of the RF tag which concerns on embodiment of this invention. It is a circuit diagram which shows the specific structural example of the antenna, rectifier circuit, and carrier extraction circuit which concern on embodiment of this invention. It is a time chart which shows the operation example of the carrier extraction circuit which concerns on embodiment of this invention. It is a time chart which shows the operation example of the carrier extraction circuit which concerns on embodiment of this invention. It is a circuit diagram which shows the structural example of the carrier extraction circuit which concerns on the modification of embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Antenna 31a, 31b ... Binarization circuit 32 ... Pulse generation circuit 33a, 33b ... Output circuit 121a, 121b ... Carrier extraction circuit 125 ... Internal circuit

Claims (5)

A carrier extraction circuit that can be connected to an antenna in which a first AC signal is induced at one end by receiving an electromagnetic wave, and a second AC signal having a phase opposite to that of the first AC signal is induced at the other end. ,
A binarization circuit that binarizes the first and second AC signals and outputs first and second binarization pulses;
A pulse generation circuit that generates a first trigger pulse in synchronization with the first binarization pulse, and generates a second trigger pulse in synchronization with the second binarization pulse;
An output circuit that receives the first and second trigger pulses and outputs a clock with a fixed duty ratio.   The carrier extraction according to claim 1, wherein each pulse width of the first and second trigger pulses is ½ or less of each pulse width of the first and second binarized pulses. circuit.   3. The carrier extraction circuit according to claim 1, wherein a frequency of the clock is equal to each frequency of the first and second AC signals. An antenna in which a first AC signal is induced at one end by receiving an electromagnetic wave, and a second AC signal having a phase opposite to that of the first AC signal is induced at the other end;
A binarization circuit that binarizes the first and second AC signals and outputs first and second binarization pulses;
A pulse generation circuit that generates a first trigger pulse in synchronization with the first binarization pulse, and generates a second trigger pulse in synchronization with the second binarization pulse;
An output circuit for outputting a clock with a fixed duty ratio, using the first and second trigger pulses as inputs;
An RF tag comprising: an internal circuit that operates in synchronization with the clock. An antenna in which a first AC signal is induced at one end by receiving an electromagnetic wave, and a second AC signal having a phase opposite to that of the first AC signal is induced at the other end;
A binarization circuit that binarizes the first and second AC signals and outputs first and second binarization pulses;
A pulse generation circuit that generates a first trigger pulse in synchronization with the first binarization pulse, and generates a second trigger pulse in synchronization with the second binarization pulse;
An output circuit for outputting a clock with a fixed duty ratio, using the first and second trigger pulses as inputs;
And an internal circuit that operates in synchronization with the clock.

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