JP2007141020A - Data processor and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption by reducing a clock frequency to be used for processing of real time data and shortening an idle period. <P>SOLUTION: This data processor is provided with a first data processing means for performing data processing of real time data by using a first clock of a first frequency, a measuring means for measuring a data processing period and an idle period of the real time data by the first data processing means each predetermined processing unit time, a clock setting means for setting a second clock of a second frequency lower than the first frequency on the basis of a measurement result of the measuring means, and a second data processing means for performing data processing of the real time data by using the second clock set by the clock setting means. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a data processing apparatus and an electronic apparatus suitable for a mobile terminal that handles real-time data.

Conventionally, portable electronic devices that perform digital processing of real-time data such as audio and video have been commercialized. Since the capacity of a storage medium such as a memory medium or a hard disk that can be used for a portable terminal is relatively small, even in such a portable terminal, encoded real-time data is stored in the storage medium. At the time of reproduction, the real-time data read from the storage medium is decoded to enable output of audio and video.

By the way, portable electronic devices have been reduced in size and weight and reduced in power consumption. For example, Patent Documents 1 and 2 disclose a technique for reducing the system clock frequency when the frame processing is in an idle state.
Special table 2004-536414 gazette JP 2005-505003 Gazette

In the proposals of Patent Documents 1 and 2, the power consumption is reduced by lowering the system clock frequency in the idle state.

However, even in the idle state, power is consumed, and there is a problem that power consumption cannot be reduced sufficiently.

The present invention has been made in view of such problems, and an object of the present invention is to provide a data processing apparatus and an electronic apparatus that can achieve low power consumption by shortening the period of an idle state.

The data processing apparatus according to the present invention includes a first data processing means for performing data processing on real-time data using a first clock having a first frequency, and the first data processing means for each predetermined processing unit time. Measuring means for determining a data processing period and an idle period of the real-time data according to, and a clock setting for setting a second clock having a second frequency lower than the first frequency based on a measurement result of the measuring means And a second processing for performing data processing on the real-time data using the second clock set by the clock setting means.
And data processing means.

According to such a configuration, the first data processing means performs data processing on the real-time data using the first clock having the first frequency. The first data processing means performs data processing during a data processing period in a predetermined processing unit time, and is in an idle state during a period other than the data processing period. The measuring means obtains a data processing period and an idle period. Since the idle period occurs, processing within a predetermined processing unit time is possible even when a clock having a frequency lower than the first frequency is used. The clock setting means obtains a second frequency for performing data processing within a predetermined processing unit time by using the measurement result. The second data processing means performs data processing on the real-time data using the second clock set by the clock setting means. Since the second frequency is lower than the first frequency, the idle period can be shortened and the power consumption can be reduced.

According to an aspect of the present invention, the measurement unit statistically obtains a data processing period and an idle period of the real-time data in the predetermined processing unit time.

According to such a configuration, by statistically obtaining the data processing period and the idle period,
From the statistically obtained result, the second frequency capable of data processing within a predetermined unit time can be reliably obtained.

Further, according to one aspect of the present invention, the clock setting unit is configured to determine the first processing unit time based on a ratio between a maximum value of a data processing period of the real-time data in the predetermined processing unit time and the predetermined processing unit time. The second frequency is obtained from the first frequency.

According to such a configuration, it is possible to sufficiently shorten the idle period within a predetermined processing unit time.

Further, according to one aspect of the present invention, the clock setting means adds a predetermined margin to a value obtained based on a ratio between the maximum value of the data processing period and the predetermined processing unit time. 2 frequency is obtained.

According to such a configuration, it is possible to reliably execute all necessary data processing within a predetermined processing unit time.

According to another aspect of the invention, the clock setting unit stops the clock during an idle period other than the data processing period by the second data processing unit. Even when an idle period occurs within a predetermined processing unit time, the clock of this idle period can be stopped, so that power consumption can be sufficiently reduced.

Moreover, according to one aspect of the present invention, the data processing by the first and second data processing means is a reproduction process of the real-time data.

According to such a configuration, it is possible to reduce power consumption by reducing the clock frequency required for real-time data reproduction processing.

Moreover, according to one aspect of the present invention, the real-time data is audio data or moving image data.

According to such a configuration, it is possible to perform reliable reproduction while reducing power consumption when reproducing audio or moving images.

According to another aspect of the invention, the clock setting unit generates the second clock by phase locked loop control.

According to such a configuration, it is possible to accurately generate a clock necessary for data processing within a predetermined processing unit time.

  The data processing apparatus is used as an audio controller.

According to such a configuration, an electronic device with reduced power consumption necessary for reproducing audio data can be obtained.

According to another aspect of the present invention, the audio controller is included in a host processor.

According to such a configuration, power consumption can be reduced by controlling the clock frequency necessary for processing not only audio data but also other data.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a data processing apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram showing a circuit configuration of an electronic apparatus such as a portable terminal in which the data processing apparatus of FIG. 1 is incorporated. The present embodiment is an example applied to a data processing apparatus that digitally processes audio data.

In FIG. 2, the portable terminal 11 has a hard disk (HD) 12 as a recording medium. The portable terminal 11 has a memory interface 13 for using an IC memory that is an external storage medium. The host processor 14 controls the entire mobile terminal 11. The host processor 14 can read real-time data from an IC memory (not shown) mounted on the memory interface 13 and the hard disk 12. Note that audio data, moving image data, and the like can be considered as the real-time data.

The host processor 14 transfers the read real-time data to each controller (not shown) that performs digital processing of each data. For example, the host processor 14 outputs audio data to an audio controller 15 as a data processing device. The audio controller 15 decodes the input audio data and provides a digital audio signal to the D / A converter 16. The D / A converter 16 converts the input digital audio signal into an analog audio signal and supplies it to the speaker 17. Thus, sound is output from the speaker 17.

  FIG. 1 shows a specific configuration of the audio controller 15 in FIG.

Audio data from the host processor 14 is supplied to the input circuit 21. Input circuit 21
Performs an interface between a signal transferred from the host processor 14 and a signal handled in the audio controller 15. The CPU 22 controls the entire audio controller 15. The CPU 22 is connected to the input circuit 21 via the bus 23, and takes in the audio data via the input circuit 21.

The memory 24 is a working memory, and the CPU 22 executes various processes using the memory 24. For example, the CPU 22 uses the memory 24 to decode input audio data. The output circuit 25 includes a signal handled in the audio controller 15 and the D / A converter 1.
Interfacing with the signals handled in step 6. The audio signal decoded by the CPU 22 is supplied to the D / A converter 16 via the output circuit 25.

The PLL circuit 26 constituting the clock setting means reproduces a clock used for various digital processes of the CPU 22. The PLL circuit 26 is supplied with a predetermined clock from the outside, and reproduces a clock having a predetermined frequency by multiplying or dividing the clock. In the present embodiment, the PLL circuit 26 can be controlled by the CPU 22 to change the frequency of the clock to be reproduced. CPU 2 as first and second data processing means
2 executes various processes using the clock generated by the PLL circuit 26.

The timer unit 27 constituting the measuring unit measures time by being controlled by the CPU 22 and counting a predetermined clock. The measurement result is given to the CPU 22.
The interrupt controller 28 detects an input from the input circuit 21 and notifies the CPU 22 of the occurrence of an interrupt. The CPU 22 switches the processing when an interrupt occurs. For example, when an interrupt informing the input of audio data occurs in the polling state, the CPU 22 cancels the polling state and starts decoding the input audio data.

In the present embodiment, the CPU 22 controls the PLL circuit 26 to reset the clock frequency so as to shorten the idle period within each processing unit time of data processing for real-time data. . Normally, the number of clocks required for each processing unit time is different from the highest frequency clock used for the processing of the CPU 22. In Patent Document 1 described above, processing is performed using a clock with the highest frequency, a period remaining after the end of processing within each processing unit time is set as an idle period, and a sufficiently slow clock is set in the idle period. It is like that.

On the other hand, in this embodiment, the CPU 22 measures the idle period that occurs every processing unit time, for example, every frame unit for audio data, and performs digital processing so that the idle period is set to 0 as much as possible. The frequency of the clock to be used is lowered. Note that the CPU 22 may set the clock frequency using, for example, statistically obtained measurement results.

Thus, the time required for processing in each frame unit approaches the frame period within the frame period, and the idle period can be made close to zero. An operation with a low-speed clock is performed in substantially the entire frame period, so that power consumption can be reduced.

Next, the operation of the embodiment configured as described above will be described with reference to FIGS. 3 to 5 are flowcharts for explaining the operation of the embodiment, and FIGS. 6 and 7 are explanatory diagrams for explaining the idle period.

Now, it is assumed that reproduction of audio data stored in the hard disk 12 of FIG. 2 or audio data captured via the memory interface 13 is instructed by a user operation. The host processor 14 reads real-time data from the hard disk 12 or the memory interface 13 and supplies it to the audio controller 15.

The audio data is real-time data, and the processing unit time is a fixed one frame period. The audio data read by the host processor 14 has been subjected to predetermined encoding and may have a different data length for each frame. For this reason, in the reproduction process of the audio controller 15, the number of clocks required for the process may differ for each frame. In the present embodiment, the audio controller 15 sets the minimum clock frequency necessary for reproduction processing by statistically obtaining the idle period, for example, and shortens the idle period of each frame. .

That is, the CPU 22 of the audio controller 15 first performs normal digital processing in step S1 of FIG. FIG. 4 specifically shows normal digital processing.

In normal digital processing described in Patent Document 1 and the like, the amount of audio data varies from frame to frame, so the time required for processing varies from frame to frame. In Patent Literature 1 and the like, reproduction processing using a set clock is performed, and when the reproduction processing for each frame is completed, an idle period is set.

That is, first, in step S11, audio data is acquired. The CPU 22 takes in data via the input circuit 21. The CPU 22 is supplied with a predetermined clock from the PLL circuit 26, and performs a decoding process using the memory 24. MP3 processing, AAC processing, and the like are performed as audio data decoding processing. In step S13, it is determined whether all the processes for the frame have been completed. The decoding process is continued until all the processes in the frame are completed.

The CPU 22 outputs an audio signal obtained by the decoding process via the output circuit 25. In this case, the audio data is accumulated in a buffer (not shown), and the output process is controlled so that the audio is continuously output regardless of the progress of the decoding process.

The audio signal is given from the output circuit 25 to the D / A converter 16. The D / A converter 16 converts the audio signal into an analog audio signal and supplies it to the speaker 17. In this way, sound based on the audio data supplied to the audio controller 15 is output.

When all the processes in the frame are completed, the process proceeds from step S13 to the interrupt polling process in step S14. In the interrupt polling process, an idle state is set until the frame period ends and audio data of the next frame period is captured.
As described above, the processing time of each frame is different, and the idle period is also different for each frame. When the audio data of the next frame period is taken in via the input circuit 21, an interrupt by the interrupt controller 28 occurs, the idle period ends, and frame processing such as decoding is resumed.

FIG. 6 shows such normal digital processing, and shows that frame processing periods and idle periods appear alternately.

In the next step S <b> 2 in FIG. 3, the CPU 22 controls the timer unit 27 to measure the idle period and obtains statistics thereof. In the next step S3, the CPU 22 calculates a clock frequency to be set from the statistical result of the idle period. Next, in step S4, the CPU 22 controls the PLL circuit 26 so that a clock having the calculated clock frequency is obtained.

FIG. 5 shows an example of a specific flow from the measurement process of step S2 of FIG. 3 to the clock setting process of step S4. In step S21 of FIG. 5, first, polling time of each frame is measured in order to obtain statistics of the idle period. In step S22, CP
U22 determines whether or not the number of frames necessary for taking statistics has been reached. If the necessary number of frames has not been reached, the process of step S21 is repeated. When the polling time is measured for the required number of frames, the CPU 22 detects the minimum value of the polling time, that is, the minimum value of the idle time (maximum value of the frame processing period) in the next step S23.
Then, in the next step S24, the CPU 22 sets a clock frequency to be set based on a value obtained by providing a predetermined margin for the detected maximum value of the frame processing period.

For example, assuming that the frame period is La and the maximum value of the frame processing period using the normal clock frequency AMHz is Lm, the reset clock frequency BMHz is
B = {(A × Lm / La) + α} MHz

FIG. 7 shows such a clock frequency setting. In FIG. 7, immediately after the start of the audio data processing, the frame processing period and the idle period are alternately repeated. When the predetermined number of frames elapses, an instruction to change the clock frequency is given, and the clock frequency is changed to a frequency lower than the original frequency. As a result, the idle period is shortened, and a frame processing period in which digital processing is performed in substantially the entire range of each frame period.

In practice, there is a possibility that a slight idle period may occur for each frame, but the illustration is omitted in FIG.

In the present embodiment, the clock generation may be stopped during an idle period that occurs slightly for each frame.

As described above, in the present embodiment, the minimum clock frequency necessary for each frame process is detected by statistically detecting the idle period, and each frame is used by using this clock frequency for subsequent processes. Can significantly reduce the idle period.
Since each frame is processed using a minimum clock frequency necessary for data processing, power consumption can be reduced.

In the above-described embodiment, the example in which the audio controller is configured separately from the host processor has been described. However, the present invention can be similarly applied to a configuration in which the audio controller is incorporated in the host processor. In this case, the CPU in the host processor can set the minimum clock frequency necessary for processing each data including the audio data, shorten the idle period, and reduce the power consumption. .

1 is a block diagram showing a data processing apparatus according to an embodiment of the present invention. The block diagram which shows the circuit structure of electronic devices, such as a portable terminal incorporating the data processor of FIG. 6 is a flowchart for explaining the operation of the embodiment. 6 is a flowchart for explaining the operation of the embodiment. 6 is a flowchart for explaining the operation of the embodiment. Explanatory drawing for demonstrating an idle period. Explanatory drawing for demonstrating an idle period.

Explanation of symbols

15 ... Audio controller, 21 ... Input circuit, 22 ... CPU, 25 ... Output circuit,
26 ... PLL circuit, 27 ... timer unit, 28 ... interrupt controller.

Claims (10)

First data processing means for performing data processing on real-time data using a first clock of a first frequency;
Measuring means for obtaining a data processing period and an idle period of the real-time data by the first data processing means for each predetermined processing unit time;
Based on the measurement result of the measuring means, the second of the second frequency lower than the first frequency.
Clock setting means for setting the clock of
Second data processing means for performing data processing on the real-time data using a second clock set by the clock setting means;
A data processing apparatus comprising: The data processing apparatus according to claim 1, wherein the measurement unit statistically obtains a data processing period and an idle period of the real-time data in the predetermined processing unit time. The clock setting unit obtains a second frequency from the first frequency based on a ratio between a maximum value of a data processing period of the real-time data in the predetermined processing unit time and the predetermined processing unit time. The data processing apparatus according to claim 2. The clock setting unit obtains the second frequency by adding a predetermined margin to a value obtained based on a ratio between a maximum value of the data processing period and the predetermined processing unit time. Item 4. The data processing device according to item 3. The data processing apparatus according to claim 1, wherein the clock setting unit stops the clock during an idle period other than a data processing period by the second data processing unit. The data processing apparatus according to claim 1, wherein the data processing by the first and second data processing means is a reproduction process of the real-time data. The data processing apparatus according to claim 1, wherein the real-time data is audio data or moving image data. The data processing apparatus according to claim 1, wherein the clock setting unit generates the second clock by phase locked loop control. 9. An electronic apparatus using the data processing apparatus according to claim 1 as an audio controller. The electronic apparatus according to claim 9, wherein the audio controller is included in a host processor.

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