JP2007135090A - Signal generation circuit and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sample hold signal generation circuit which allows software for setting a sample hold timing to be shared even between different models, in an electrophotographic image forming apparatus which scans a photoreceptor drum to write image information. <P>SOLUTION: In a sample hold signal generation circuit 10, a minimum period out of periods B of a line synchronizing signal outputted from a line synchronizing signal period measuring instrument 11 is extracted by a minimum period extraction circuit 12. A computing element 13 computes a generation timing E of the sample hold signal based on a line synchronizing signal A on the basis of the extracted minimum period C of the line synchronizing signal and outputs the generation timing E to a sample hold signal generation comparator 15 which outputs the sample hold signal. The sample hold signal generation comparator 15 compares the number F of clocks from the line synchronizing signal outputted from a timing generation counter 14, with the sample hold signal generation timing E and outputs a sample hold signal G. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a signal generation circuit that is used in an electrophotographic image forming apparatus that scans a photosensitive drum and writes image information, and generates a predetermined signal for each scanning cycle, and more particularly, to scan a photosensitive drum. The present invention relates to a signal generation circuit and an image forming apparatus suitable for a sample-and-hold signal generation circuit that calculates a sample-and-hold light amount correction timing indicating a timing for correcting a light amount of a laser diode that writes image information.

  Some conventional sample hold signal generation circuits generate sample hold timing according to software settings. FIG. 18 shows a block diagram of a general image forming apparatus including a sample hold signal generation circuit. The image forming apparatus includes an LSU controller 1, an LSU unit 2, a CPU 3, an operation panel 4, various control motors 5, a CCD and an image processing block 6, and a drum and a developing unit 7. When the user presses the copy button on the operation panel 4, the CPU 3 controls the various control motors 5 to start conveying the output paper. When the sheet is conveyed to the printing position, the LSU controller 1 outputs image data to the LSU unit 2 in synchronization with the line synchronization signal from the LSU unit 2. The LSU unit 2 forms an image on the drum with laser light based on the image data received from the LSU controller 1. The image formed on the drum is transferred to output paper and developed by a developing unit.

  Here, the sample hold signal generation circuit 50 of the LSU controller block outputs a correction instruction signal (hereinafter, the correction instruction signal is referred to as a sample hold signal) to the LSU unit 2 at regular intervals in order to correct the temporal change of the LSU unit 2. To do. A change with time of the LSU unit 2 includes a decrease in the light emission amount of the laser diode due to a natural discharge of the current control capacitor. The LSU unit 2 measures the light emission amount of the laser diode at the timing when the sample hold signal output from the sample hold signal generation circuit 50 is input, and charges the current control capacitor according to the light emission amount so as to obtain an appropriate light emission amount. In addition, the light amount of the laser diode is corrected.

  FIG. 19 is a timing chart showing the relationship between the sample hold signal and the charge amount of the current control capacitor, and explains that the charge amount of the current control capacitor decreases with time and is recharged at the input timing of the sample hold signal. Yes. The line indicating the charge amount of the current control capacitor also indicates the light emission amount of the laser diode, and the light emission amount of the laser diode is also corrected by correcting the charge amount of the current control capacitor. Hereinafter, the correction of the light emission amount of the laser diode performed by the LSU unit 2 by the input of the sample hold signal is referred to as light amount correction. The light amount correction is generally performed once in one line synchronization signal period (one laser scanning time).

  FIG. 20 is a block diagram for explaining a conventional sample and hold signal generation circuit. The conventional sample and hold signal generation circuit 50 includes a timing generation counter 51 and a sample and hold signal generation comparator 52. The timing generation counter 51 is a counter that outputs the number of clocks after the line synchronization signal is input. The timing generation counter 51 is configured to be reset to 0 when the line synchronization signal is input and is incremented by +1 for each clock input. The The sample hold signal generation comparator 52 compares the number of clocks from when the line synchronization signal output from the timing generation counter 51 is input with the sample hold signal generation timing setting value (number of clocks) input from the CPU 3 to perform sample hold. If it is signal generation timing, a sample hold signal is output.

FIG. 21 is a timing chart for explaining the output timing of the sample and hold signal in the conventional LSU controller 2. When the sample and hold signal generation timing U is set to 9000 as shown in FIG. When the clock number V from the line synchronization signal output from the counter reaches 9000, the sample hold signal W is output. Here, the sample hold signal generation timing U is a predetermined fixed value, and has no correlation with the cycle of the line synchronization signal.
However, the line synchronization signal cycle differs depending on the model of the image forming apparatus, and the output timing of the sample hold signal needs to be optimized for each model to set individual sample hold signal generation timing. Some conventional image forming apparatuses are configured so that the sample hold signal generation timing from the CPU can be controlled by software, and the optimum sample hold timing is obtained by using software corresponding to each model of the image forming apparatus. There was something to be realized.

  However, since the sample hold signal generation timing is not correlated with the cycle of the line synchronization signal, the conventional sample hold signal generation circuit has a sample when applied to an image forming apparatus that operates with the same sample hold signal generation timing in different line synchronization signal cycles. In some cases, a hold signal was not output.

  An example in which the sample and hold signal is not output in the conventional LSU will be described using the timing chart of the conventional sample and hold signal generation circuit shown in FIG. When the software in which the sample hold signal generation timing U is set to 9000 is applied to a different model with a small line synchronization signal period, the number of clocks V after the line synchronization signal is input before the sample hold signal generation timing U reaches the sample hold signal generation timing U. The next line synchronization signal T is input and reset. As a result, the condition that the number of clocks V from when the line synchronization signal is input reaches the sample hold signal generation timing U does not occur, and therefore the sample hold signal W is not output.

  For this reason, in the conventional configuration, software that shares the output timing of the sample and hold signal between different models cannot be created, and it is necessary to develop separate software for each model of the image forming apparatus.

  The present invention has been made in view of such circumstances, and provides a sample hold signal generation circuit that can share software among different models by calculating and determining the sample hold timing based on the minimum period of the line synchronization signal. The purpose is to do.

  In order to solve the above problems, a first technical means of the present invention is a signal generation circuit that generates a predetermined signal and is used in an electrophotographic image forming apparatus that scans a photosensitive drum and writes image information. A line synchronization signal period measuring device that measures the period of the line synchronization signal, a minimum period extraction circuit that receives the line synchronization signal period output from the line synchronization signal period measuring device and extracts a minimum period, and An arithmetic unit that calculates an output timing of the predetermined signal based on the line synchronization signal based on the minimum line synchronization signal period output from the minimum period extraction circuit.

  According to a second technical means, in the first technical means, the line synchronization signal period measuring device latches a clock counter that counts the number of clocks based on the line synchronization signal, and a clock count value in synchronization with the line synchronization signal. It is characterized by comprising a latch.

  According to a third technical means, in the first technical means, the minimum period extraction circuit stores a line synchronization signal period storage device that stores a minimum period of a line synchronization signal and the line synchronization measured by the line synchronization signal period measuring device. It is characterized by comprising a minimum period extraction comparator for comparing a signal period and a line synchronization signal minimum period stored in the line synchronization signal period storage device.

  According to a fourth technical means, in the first technical means, the arithmetic unit should output the predetermined signal by subtracting a first threshold value from a minimum period of a line synchronization signal output from the minimum period extraction circuit. It is characterized by comprising a subtractor for calculating timing.

  A fifth technical means is the fourth technical means characterized in that the first threshold value can be rewritten.

  A sixth technical means is the same as the first technical means, further comprising a latch circuit for latching a minimum period of the line synchronization signal output from the minimum period extraction circuit.

  According to a seventh technical means, in the sixth technical means, the latch permission signal inputted to the latch circuit is outputted based on an elapsed time from the time when the minimum cycle of the line synchronization signal is updated. It is what.

  The eighth technical means is the first technical means, further comprising a time measuring device for measuring an elapsed time from the time when the minimum cycle of the line synchronization signal is updated.

  According to a ninth technical means, in the first technical means, the minimum cycle extraction circuit outputs a minimum cycle update flag when the minimum cycle of the line synchronization signal is updated.

  According to a tenth technical means, in the third technical means, the minimum period extraction comparator outputs a minimum period update flag when the minimum period of the line synchronization signal is updated.

  According to an eleventh technical means, in the eighth technical means, the timing device starts an operation based on a minimum period update flag output when the minimum period extraction circuit updates the minimum period of the line synchronization signal. It is characterized by being a timer.

  According to a twelfth technical means, in the eighth technical means, the time measuring device uses the clock for measuring the current time and the minimum cycle update flag output from the minimum cycle extraction comparator as a trigger to set the minimum cycle update time to the clock. The minimum cycle update time storage device that updates to the current time output by and outputs the minimum cycle update time, and the subtraction that outputs the elapsed time since the minimum cycle was updated by subtracting the minimum cycle update time from the current time It is characterized by comprising a vessel.

  According to a thirteenth technical means, in the seventh technical means, the latch permission signal input to the latch circuit has elapsed from the time when the minimum period of the line synchronization signal is updated, and sampling of the period of the line synchronization signal is completed. Control is performed according to whether or not a second threshold value indicating timing is exceeded.

  According to a fourteenth technical means, in the first technical means, the minimum period extracting circuit can accept a line synchronization signal period capturing permission signal for controlling whether or not to sample the period of the line synchronization signal. It is a feature.

  The fifteenth technical means is characterized in that, in the fourteenth technical means, the line synchronization signal period capturing permission signal inputted to the minimum period extracting circuit is controlled by the CPU.

  A sixteenth technical means is the first technical means, further comprising a second time measuring device for measuring an elapsed time since the polygon motor started rotating.

  According to a seventeenth technical means, in the sixteenth technical means, a second elapsed time comparison for comparing an elapsed time after the polygon motor starts rotating and a third threshold value indicating the sampling start timing of the line synchronization signal. And a line synchronization signal period capture permission signal of the minimum period extraction circuit is controlled based on a comparison result of the second elapsed time comparator.

  According to an eighteenth technical means, in the first technical means, the generation timing output from the computing unit is a timing at which output of the predetermined signal is started.

  A nineteenth technical means is characterized in that, in the first technical means, the generation timing output by the computing unit is a timing at which the output of the predetermined signal is terminated.

  A twentieth technical means is a signal generation circuit that is used in an electrophotographic image forming apparatus that scans a photosensitive drum and writes image information, and generates a predetermined signal for each scanning cycle. A line synchronization signal period measuring device for measuring the period, a minimum period extracting circuit for extracting a minimum period from the previous line synchronization signal periods output from the line synchronization signal period measuring device, and an output of the minimum period extracting circuit A first calculator that calculates an output start timing of the predetermined signal based on the line synchronization signal based on the minimum period of the line synchronization signal, and a minimum period of the line synchronization signal output by the minimum period extraction circuit. A second arithmetic unit that calculates an output end timing of the predetermined signal based on a line synchronization signal, and an output of the predetermined signal output from the first arithmetic unit A first sample hold signal generation comparator that generates an output start signal of the predetermined signal based on a start timing; and an output end timing of the predetermined signal output from the second arithmetic unit. A second sample-and-hold signal generation comparator that generates a signal output end signal, and determines whether to output the predetermined signal according to the output level of the signal output start signal and the signal output end signal It is characterized by making decisions.

  A twenty-first technical means is a signal generation circuit that is used in an electrophotographic image forming apparatus that scans a photosensitive drum and writes image information, and generates a predetermined signal for each scanning cycle. A line synchronization signal period measuring device for measuring a period, a minimum period extracting circuit for extracting a minimum period among a plurality of line synchronization signal periods output from the line synchronization signal period measuring device, and an output from the minimum period extracting circuit The predetermined signal is calculated by calculating a first constant for designating a minimum line synchronization signal period and a division unit of the line synchronization signal and a second constant indicating an output position of the sample hold signal with reference to the input of the line synchronization signal. And an arithmetic unit for calculating the output timing.

  According to a twenty-second technical means, in the twenty-first technical means, the arithmetic unit divides a minimum line synchronization signal period output from the minimum period extraction comparator circuit by a first constant to obtain a set unit of the predetermined signal. It comprises a divider for calculating and a multiplier for calculating a generation timing of the predetermined signal by multiplying a set unit of the predetermined signal by a second constant.

  A twenty-third technical means is characterized in that, in the second technical means, a signal line for connecting the output of the clock counter to a sample-and-hold signal generating comparator for outputting the predetermined signal is provided.

  The twenty-fourth technical means is an image forming apparatus including the first to twenty-third technical means.

  According to a twenty-fifth technical means, in an image forming apparatus capable of outputting a plurality of printing colors, a plurality of first technical means are provided for each printing color.

  The twenty-sixth technical means is characterized in that, in the twenty-fifth technical means, an individual signal line for setting a set value for each printing color is further provided.

According to the present invention composed of the above technical means, the following effects can be obtained.
According to the first technical means, it is possible to measure the minimum line synchronization signal period and determine the output position of a predetermined signal such as a sample hold signal based on the minimum line synchronization signal period. Even if the image forming apparatus has a different model or the model of the image forming apparatus is different, the sample hold signal can be reliably output for each line synchronization signal period without changing the software.

  According to the second technical means, the cycle of the line synchronization signal of the image forming apparatus to be controlled can be measured. Although the cycle of the line synchronization signal differs for each model of the image forming apparatus, the cycle of the line synchronization signal can be measured according to the model to be controlled.

  According to the third technical means, the minimum line synchronization signal period can be extracted from the measured line synchronization signals. Strictly speaking, the line synchronization signal does not have the same period due to variations in the rotation of the control motor. According to the third technical means, a minimum line synchronization signal period can be extracted from a plurality of line synchronization signal periods including rotation variations. The subsequent arithmetic unit can calculate the output timing of the sample and hold signal based on the minimum line synchronization signal cycle output from the minimum cycle extraction circuit, so there is no problem that the output timing of the sample and hold signal exceeds the line synchronization signal cycle.

  According to the fourth technical means, the output timing of the sample hold signal can be determined by subtracting the first threshold value from the minimum line synchronization signal period. That is, the output timing of the sample hold signal can be determined by calculating according to the cycle of the line synchronization signal. In the conventional sample and hold signal generation circuit, since the sample and hold output timing itself was set based on the line synchronization signal, it was necessary to set a different value in consideration of the line synchronization signal period for each model. According to the present invention, a common value can be set between models without considering the cycle of the line synchronization signal, and software can be shared between models. Even when a fixed value is set as the first threshold value and applied to an image forming apparatus of a different model, there is no problem that the output timing of the sample hold signal exceeding the cycle of the line synchronization signal is set.

  According to the fifth technical means, the first threshold value indicating the timing at which the sample hold signal should be output can be rewritten, so that the output timing of the sample hold signal can be adjusted. Even if the image forming apparatus is the same model, there are individual differences such as machine variations, but this configuration can adjust the variations.

  According to the sixth technical means, since the minimum cycle of the line synchronization signal cycle is latched by the latch circuit, there is no problem of propagating the abnormal minimum cycle to the arithmetic unit.

  According to the seventh technical means, by performing control of the latch permission signal input to the latch circuit based on the elapsed time from the time when the minimum cycle is updated, unstable operation such as when the image forming apparatus is started up Since the minimum period can be latched before the time or when an abnormality occurs, there is no problem of propagating the abnormal minimum period to the computing unit.

  According to the eighth technical means, since the elapsed time from the time when the minimum cycle is updated is measured, a reference for determining whether or not to latch the minimum cycle can be obtained.

  According to the ninth and tenth technical means, when the minimum cycle is updated, a flag for notifying the subsequent circuit of the update is output, so that the subsequent circuit changes its operation based on the presence or absence of the update. can do.

  According to the eleventh technical means, since the timer is operated by detecting the input of the minimum period update flag, the elapsed time after the minimum period is updated can be measured. In this configuration, the elapsed time can be measured with a simple configuration as compared with the measurement of the current time using a clock.

  According to the twelfth technical means, since the time when the minimum cycle update flag is input is recorded as the current time output by the clock, the time updated in addition to the elapsed time since the minimum cycle was updated. You can leave a history.

  According to the thirteenth technical means, if there is no update of the minimum cycle even after a time exceeding the second threshold from the time when the minimum cycle is updated, it is determined that the minimum cycle is not updated and the latch circuit is Since the control is performed so that the input of the minimum period of the line synchronization signal to the arithmetic unit is fixed, even if noise is detected as the line synchronization signal after the input of the minimum period of the line synchronization signal is fixed, it is not affected.

  According to the fourteenth technical means, since the capture of the cycle of the line synchronization signal is controlled by the line synchronization signal cycle capture permission signal, the cycle of the line synchronization signal when an abnormal cycle occurs can be captured. There is no problem of sampling an abnormal cycle as a minimum cycle extraction target.

  According to the fifteenth technical means, since the CPU controls the line synchronization signal cycle capture permission signal, the timing for sampling the cycle of the line synchronization signal can be selected by the CPU.

  According to the sixteenth technical means, since the elapsed time from the start of the polygon motor is measured, a reference for determining the timing for sampling the cycle of the line synchronization signal based on the elapsed time from the start of the polygon motor is obtained. Can do.

  According to the seventeenth technical means, the cycle of the line synchronization signal is taken into the minimum cycle extraction circuit as a sampling target in consideration of the elapsed time from the start of the polygon motor, so that the unstable in the vicinity of the start of the polygon motor. The period of the line synchronization signal can be excluded from the minimum period extraction target.

  According to the eighteenth technical means, since the timing for starting the output of the sample hold signal is obtained, the timing for starting the output of the sample hold signal can be set even if the model of the image forming apparatus is changed. There is no need to change every time.

  According to the nineteenth technical means, the timing to end the output of the sample hold signal is obtained. Therefore, the timing to end the output of the sample hold signal even if the model of the image forming apparatus is changed. There is no need to change every time.

  According to the twentieth technical means, since the sample hold signal output start signal and the output end signal are obtained, the timing from the output start to the output end can be obtained as an output valid signal of the sample hold signal. Thereby, even if the model of the image forming apparatus is changed, it is not necessary to change the output valid timing of the sample hold signal for each model of the image forming apparatus. In addition, since the output start timing and the output end timing can be set individually, the effective width of the sample hold signal effective signal can be arbitrarily set.

  According to the twenty-first and twenty-second technical means, since the sample and hold signal generation circuit is constituted by a divider and a multiplier, the output timing of the sample and hold signal can be set at a ratio to the period of the line synchronization signal. In addition, when the output position of the sample hold signal is designated by the number of clocks based on the line synchronization signal, a setting value necessary for designation can be reduced. For example, when the sample hold signal is output at a position of 7000 clocks based on the line synchronization signal (10000 clock cycles), when the output position is specified by the number of clocks, 3000 (12 bits) is set as the first threshold value. According to the twenty-first technical means, it is only necessary to specify 10 (4 bits) for the first constant value and 7 (3 bits) for the second constant value.

  According to the twenty-third technical means, the circuit counter can be reduced because the clock counter and the timing generation counter built in the line synchronization signal period measuring device can be shared.

  According to the twenty-fifth and twenty-sixth technical means, a plurality of print colors can be printed, and in a printing apparatus including a laser diode for each print color, an independent sample hold signal can be generated for each color. Even if there is machine variation, it can be absorbed by setting individual sample and hold signals.

  Hereinafter, the best embodiment of a signal generation circuit according to the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram for explaining a sample and hold signal generation circuit when the first technical means of the present invention is applied to an image forming apparatus. The sample hold signal generation circuit 10 includes a line synchronization signal period measuring device 11, a minimum period extraction circuit 12, a calculator 13, a timing generation counter 14, and a sample hold signal generation comparator 15, and the line synchronization signal output from the LSU unit 2. The line synchronization signal period measuring device 11 for measuring the period A is composed of, for example, a counter. The period B of the line synchronization signal output from the line synchronization signal period measuring device 11 is represented by the number of clocks corresponding to the period of the line synchronization signal A. A minimum period extraction circuit 12, which is a circuit for extracting the minimum period C of the line synchronization signal, extracts a minimum period from the period B of the line synchronization signal output from the line synchronization signal period measuring device 11, and calculates the subsequent arithmetic unit 13. Output to. The arithmetic unit 13 is a circuit that calculates the sample hold signal generation timing E from the minimum period C of the line synchronization signal output from the minimum period extraction circuit 12 and the first threshold value D. The sample hold signal generation timing E indicates the output timing of the sample hold signal with the line synchronization signal A as a reference, and is represented by the number of clocks with the line synchronization signal A as a reference. The first threshold value D is set to a value that prevents the sample hold signal from being output while the laser beam scans the image forming area on the drum.

  The timing generation counter 14 is a counter that outputs the number of clocks F after the line synchronization signal is input. The timing generation counter 14 is a counter that becomes 0 when the line synchronization signal A is input and is incremented by 1 when the clock is input. The number of clocks F after the line synchronization signal is input to the generation comparator 15 is output. The sample and hold signal generation comparator 15 compares the number of clocks F after the line synchronization signal output from the timing generation counter 14 is input with the generation and timing E of the sample and hold signal output from the computing unit 13 to obtain the sample and hold signal G. Output to the LSU unit 2. The sample hold signal G is a signal indicating the timing at which the LSU unit 2 performs light amount correction, and is an active level at a timing at which light amount correction is performed, and an inactive level at a timing at which light amount correction is not performed.

  FIG. 2 is a timing chart for explaining the operation timing of each part of the sample hold signal generation circuit to which the first technical means is applied. The cycle B of the line synchronization signal is influenced by mechanical factors and includes an error even in the same image forming apparatus, and does not have the same value for each line. FIG. 2 illustrates a case where the period B of the line synchronization signal is shifted to 10002, 10005, 10003, 10001, and 10006 due to an error. Further, when the model of the image forming apparatus is different, the cycle B of the line synchronization signal is greatly different. The minimum period C of the line synchronization signal is generated by the minimum period extraction circuit 12. The minimum cycle extraction circuit 12 compares the minimum cycle of the cycles of the line synchronization signal input in the past with the latest cycle of the line synchronization signal input from the line synchronization signal cycle measuring device 11, and determines the smaller one as the line. This is extracted as the minimum cycle C of the synchronization signal and output to the calculator 13 as the minimum cycle C of the new line synchronization signal.

  In the example of FIG. 2, the minimum cycle C of the line synchronization signal is updated from 10002 to 10001 when the cycle B of the line synchronization signal is 10001. The first threshold value D is always given a constant value while the minimum period extraction circuit 12 is operating. In the example of FIG. 2, 1000 is given. The sample hold signal generation timing E is calculated by the calculator 13. The sample hold signal generation timing E is calculated by calculating the minimum period C and the first threshold value D of the line synchronization signal. In the example of FIG. 2, subtraction is performed by subtracting the first threshold D from the minimum cycle C of the line synchronization signal. When the minimum cycle C of the line synchronization signal is 10002, the arithmetic unit 13 inputs 9002 when the minimum cycle C of the line synchronization signal is 10001 to the sample hold signal generation comparator 15 as the sample hold signal generation timing E. Output. As described above, the sample hold signal G is output at the timing when the number of clocks F after the line synchronization signal is input and the sample hold signal generation timing E coincide with each other, and in the example of FIG. 2 after the line synchronization signal is input. The sample hold signal G is output when the number of clocks F becomes 9002 and coincides with the sample hold signal generation timing E.

  FIG. 3 is a diagram for explaining the configuration of the second technical means, that is, the line synchronization signal period measuring device 11. FIG. 3A is a block diagram showing a detailed configuration of the line synchronization signal period measuring device 11, and FIG. 3B shows a timing chart thereof. The line synchronization signal period measuring device 11 is composed of a clock counter 11a which becomes 0 when the line synchronization signal A is input and is incremented by 1 when the clock clk is input, and a latch 11b which latches the counter output at the input timing of the line synchronization signal A. The clock counter 11a outputs the number of clocks F after the line synchronization signal is input. The latch 11b latches the value of the clock counter 11a at the input timing of the line synchronization signal A, and outputs the value as the cycle B of the line synchronization signal to the minimum period extraction circuit 12 at the subsequent stage.

  FIG. 4 is a diagram for explaining the configuration of the third, ninth, and tenth technical means, that is, the minimum period extraction circuit 12. FIG. 4A is a block diagram showing a configuration of the minimum period extraction circuit 12, and FIG. 4B shows a timing chart thereof. The minimum cycle extraction circuit 12 includes a minimum cycle extraction comparator 12a and a line synchronization signal cycle storage device 12b. The minimum cycle extraction comparator 12a is a cycle B of the latest line synchronization signal sent from the line synchronization signal cycle measuring unit 11. The line synchronization signal period storage device 12b and the previous minimum line synchronization signal period C1 are compared with the line synchronization signal A, and the smaller one is used as the minimum line synchronization signal period C2. It outputs to the signal period storage device 12b. At this time, a clock may be input instead of the line synchronization signal. When the cycle B of the line synchronization signal is smaller than the cycle C1 of the minimum line synchronization signal, a minimum cycle update flag H for notifying that the minimum cycle has been updated is output to an external circuit such as the timing device 17. The line synchronization signal cycle storage device 12b stores the minimum line synchronization signal cycle C2 and outputs it to the calculator 13 and the minimum cycle extraction comparator 12a as a new minimum line synchronization signal cycle C1. The line synchronization signal cycle storage device 12b changes the minimum cycle C1 of the output line synchronization signal to the minimum cycle C2 of the new line synchronization signal as a comparison result, and newly changes it to the minimum cycle of the line synchronization signal. It can also be configured to output as C1.

  FIG. 5 is a diagram for explaining the configuration of the fourth technical means, that is, the arithmetic unit 13. FIG. 5A is a block diagram showing a configuration of the arithmetic unit 13, and FIG. 5B shows a timing chart thereof. In the example of FIG. 5, the calculator 13 is composed of a subtractor 13a. The first threshold value is subtracted from the minimum cycle C of the line synchronization signal and output as the sample hold signal generation timing.

  FIG. 6 is a block diagram showing a fifth technical means, that is, a configuration in which the first threshold value D can be rewritten. The arithmetic unit 13 and the CPU 3 are connected by a signal line, and the first threshold value D input to the arithmetic unit 13 is shown. Can be rewritten by the CPU 3.

  FIG. 7 is a block diagram showing a configuration comprising sixth and seventh technical means, that is, a latch circuit 16 that latches the minimum period C of the line synchronization signal output from the minimum circuit extraction circuit 12. The minimum cycle C of the line synchronization signal to be output is input to the latch circuit 16, and the minimum cycle C3 of the line synchronization signal output from the latch circuit 16 is input to the calculator 13. The latch circuit 16 receives a latch permission signal I from the CPU 3, and the CPU 3 permits the latch operation.

  FIG. 8A is a block diagram showing a configuration including an eighth technical means, that is, a time measuring device that measures an elapsed time from the time when the minimum period of the line synchronization signal is updated. The sample hold signal generation circuit 10 inputs the minimum cycle update flag signal H output from the minimum cycle extraction circuit 12 to the time measuring device 17. The minimum cycle update flag signal H is output from the minimum cycle extraction circuit 12 when the minimum cycle C of the line synchronization signal is updated. The time measuring device 17 measures the elapsed time J with reference to the minimum cycle update flag signal H, and outputs the elapsed time J to the CPU.

  FIG. 8B is a block diagram showing an eleventh technical means, that is, a configuration in which the timing device 17 includes a timer. When the minimum period update flag signal H is input, the timer 17a starts a timer operation and outputs the elapsed time J to the CPU 3.

  FIG. 8C is a block diagram showing a configuration of the twelfth technical means, that is, the time measuring device 17 includes a clock 17b, a minimum cycle update time storage device 17c, and a subtractor 17d. When the minimum cycle update flag signal H output from the minimum cycle extraction circuit 12 is input, the minimum cycle update time storage device 17c stores the current time K output from the clock 17b as the minimum cycle update time. The subtracter 17d subtracts the minimum cycle update time L output from the minimum cycle update time storage device 17c from the current time K output from the clock 17b, and outputs the result to the CPU 3 as the elapsed time.

  FIG. 9 is a block diagram showing a thirteenth technical means, that is, a configuration for controlling a latch circuit that latches the minimum cycle of the line synchronization signal output from the minimum cycle extraction circuit according to the elapsed time from the minimum cycle last update time. An elapsed time comparator 18 is provided between the CPU 3 and the latch circuit 16 so as to compare the second threshold M and the elapsed time J from the minimum cycle final update time. The elapsed time comparator 18 is the minimum cycle last. When the elapsed time J from the update time exceeds the second threshold value M, the latch permission signal I is activated and the minimum cycle of the line synchronization signal is latched. Here, the elapsed time comparator 18 may be configured by software. When the elapsed time comparator is configured by software, the CPU 3 goes to the latch circuit 16 according to whether or not the elapsed time J from the minimum cycle update time of the line synchronization signal exceeds the second threshold indicating the sampling end timing of the line synchronization signal. The latch permission signal I is controlled.

  FIG. 10 is a block diagram showing a configuration in which the fourteenth and fifteenth technical means, that is, the minimum period extracting circuit can accept the line synchronization signal period capturing permission signal. The minimum cycle extraction circuit 12 receives the line synchronization signal cycle capture permission signal N from the CPU 3, and the minimum cycle extraction circuit 12 sets the cycle B of the line synchronization signal only when the line synchronization signal cycle capture permission signal N is in the permitted state. Acceptance is set as a sampling target for extracting the minimum period C of the line synchronization signal. In the example of FIG. 10, the line synchronization signal period capture permission signal N is input to the write permission terminal 12 c of the line synchronization signal period storage device 12 b included in the minimum period extraction circuit 12. With this configuration, when the line synchronization signal period capture permission signal N is not in the permitted state, the minimum line synchronization signal period C2 is not stored in the line synchronization signal period storage device 12b. Here, the line synchronization signal period capturing permission signal N is inputted from the CPU 3, and the CPU 3 permits the capturing operation.

FIG. 11 is a block diagram showing the configuration of the sixteenth and seventeenth technical means. The fifteenth technical means further includes a second timing device that measures an elapsed time since the polygon motor started rotating. A polygon motor activation signal O output from the CPU 3 to the polygon motor 40 is input to the second timing device 19 in parallel. As shown in FIG. 12, the second timing device 19 includes a timer 19a that starts an operation based on a polygon motor activation signal O.
10 and 11, the line synchronization signal cycle storage device 12b of the minimum cycle extraction circuit 12 includes the write permission terminal 12c. However, the minimum cycle extraction comparator 12a may include the write permission terminal 12c. However, if it is configured as shown in the figure and the line synchronization signal cycle storage device is configured by a nonvolatile memory, the stored line synchronization signal cycle can be used until the permission signal is input even after the power is turned on again.

  According to a seventeenth technical means, in the sixteenth technical means, a second elapsed time comparison for comparing an elapsed time after the polygon motor starts rotating and a third threshold value indicating the sampling start timing of the line synchronization signal. And a line synchronization signal period capturing permission signal of the minimum period extracting circuit is controlled based on the comparison result of the second elapsed time comparator. A second elapsed time comparator 20 is provided between the CPU 3 and the minimum cycle extraction circuit 12, and an elapsed time P from the start of the polygon motor output by the second timing device 19 is stored in the second elapsed time comparator 20. Entered. The second elapsed time comparator 20 compares the third threshold Q output from the CPU 3 with the elapsed time P from the start of the polygon motor, and when the elapsed time P from the start of the polygon motor exceeds the third threshold Q, The line synchronization signal period capturing permission signal N is made active, and the capturing of the period B of the line synchronization signal is permitted. Here, it is preferable that the third threshold value Q output from the CPU 3 gives a time required for stabilization after the rotation of the polygon motor 40 starts.

  FIG. 13A is a block diagram showing an eighteenth technical means, that is, a configuration in which the generation timing output from the arithmetic unit is used as the output start timing of the sample hold signal, and the sample hold signal generation timing E1 output from the arithmetic unit 131 is sampled and held An example is shown in which the signal is input to the signal generation comparator 151 and used as the sample hold signal output start timing. The sample hold signal generation circuit 10 compares the number of clocks F after the line synchronization signal output from the timing generation counter 14 is input with the sample hold signal generation timing E1 output from the computing unit 131, and the line synchronization signal is input. If the clock number F from is larger, the output start signal G1 of the sample hold signal is output.

  FIG. 13B is a block diagram showing a nineteenth technical means, that is, a configuration in which the generation timing output from the arithmetic unit is used as the output end timing of the sample hold signal, and the sample hold signal generation timing E2 output from the arithmetic unit 132 is sampled. An example of inputting to the hold signal generation comparator 152 and using it as the sample hold signal output end timing is described. The sample hold signal generation comparator compares the number of clocks F after the line synchronization signal output from the timing generation counter 14 is input with the sample hold signal generation timing E2 output from the computing unit 132, and the line synchronization signal is input. If the clock number F from is larger, the output end signal G2 of the sample hold signal is output.

  FIG. 13C is a block diagram showing a configuration including a twentieth technical means, that is, a plurality of sample and hold signal generation comparators. FIG. 14 is a diagram showing a timing chart in such a configuration. In FIG. 13C, two arithmetic units, that is, a first arithmetic unit 133 and a second arithmetic unit 134, two sample and hold signal generation comparators, that is, a first sample and hold signal generation comparator 153, and a second sample and hold signal generation comparison. A container 154. The first sample hold signal generation timing E3 output from the first arithmetic unit 133 is used as the sample hold signal output start timing of the first sample hold signal generation comparator 153. The second sample hold signal generation timing E4 output from the second calculator 134 is used as the sample hold signal output end timing of the second sample hold signal generation comparator 154. Then, the logic circuit 155 logically outputs the sample hold signal output start signal G3 output from the first sample hold signal generation comparator 153 and the sample hold signal output end signal G4 output from the second sample hold signal generation comparator 154. The calculation is performed, and when the sample hold signal output start signal G3 is at the valid level and the sample hold signal output end signal G4 is at the invalid level, the sample hold signal G is output. (In FIG. 14, the effective level is represented by L level.)

  FIG. 15 is a block diagram showing a configuration in which the twenty-first and twenty-second technical means, that is, the arithmetic unit comprises a divider and a multiplier. As shown in FIG. 15B, a constant value is input from the CPU 3 to each of the divider 33a and the multiplier 33b. The divider 33a divides the minimum cycle C of the line synchronization signal output from the minimum cycle extraction circuit 32 by the first constant value R1, and outputs the result to the multiplier 33b as the sample hold signal setting unit S. The multiplier 33b multiplies the sample hold signal setting unit S output from the divider 33a by the second constant value R2, and outputs the sample hold signal generation timing E to the sample hold signal generation comparator 35. With this configuration, the output position of the sample hold signal with respect to the minimum cycle of the line synchronization signal can be specified as a ratio with respect to the minimum cycle of the line synchronization signal. For example, when a sample hold signal is output at a position 7/10 of the line synchronization signal period, 10 is set as the divisor and 7 is set as the multiplier.

  FIG. 16 is a block diagram showing a configuration in which the 23rd technical means, that is, the line synchronization signal period measuring device and the sample hold signal generation circuit share a clock counter. The number of clocks F after the line synchronization signal output from the clock counter 11 a incorporated in the line synchronization signal period measuring device 11 is input is input to the sample hold signal generation circuit 15.

  In FIG. 17, a plurality of sample and hold signal generation circuits of the 25th and 26th technical means, that is, the first technical means are provided for each printing color, and individual signal lines for setting a setting value for each printing color are provided. It is a figure which shows the structure made into. If comprised in this way, it can respond also to color printing.

  Note that the present invention can also be applied to generation of output timing of a specific signal controlled by different software for each model of the image forming apparatus with reference to the line synchronization signal. For example, the present invention can also be applied to a noise mask circuit that masks noise of a specific signal for a certain period with reference to a line synchronization signal.

It is a block diagram which shows the structure of the sample hold signal generation circuit based on this invention. 6 is a timing chart for explaining the operation of the sample hold signal generation circuit according to the present invention. It is a figure for demonstrating the structure of the line synchronous signal period measuring device which concerns on this invention. It is a figure for demonstrating the structure of the minimum period extraction circuit which concerns on this invention. It is a figure for demonstrating the structure of the calculator based on this invention. It is a block diagram which shows the example from which the structure of the sample hold signal generation circuit which concerns on this invention differs. It is a block diagram which shows the further different example of a structure of the sample hold signal generation circuit which concerns on this invention. It is a block diagram which shows the further different example of a structure of the sample hold signal generation circuit which concerns on this invention. It is a block diagram which shows the structure of the time measuring device which concerns on this invention. It is a block diagram which shows the example from which the structure of the timing device which concerns on this invention differs. It is a block diagram which shows the further different example of a structure of the sample hold signal generation circuit which concerns on this invention. It is a block diagram which shows the further different example of a structure of the sample hold signal generation circuit which concerns on this invention. It is a block diagram which shows the further different example of a structure of the sample hold signal generation circuit which concerns on this invention. It is a block diagram which shows the 2nd time measuring device which concerns on this invention. It is a block diagram which shows the further different example of a structure of the sample hold signal generation circuit which concerns on this invention. It is a block diagram which shows the further different example of a structure of the sample hold signal generation circuit which concerns on this invention. It is a block diagram which shows the further different example of a structure of the sample hold signal generation circuit which concerns on this invention. 6 is a timing chart for explaining the operation of a different example of the configuration of the sample and hold signal generation circuit according to the present invention. It is a block diagram which shows the further different example of a structure of the sample hold signal generation circuit which concerns on this invention. It is a block diagram which shows the further different example of a structure of the sample hold signal generation circuit which concerns on this invention. 1 is a block diagram illustrating a configuration of an image forming apparatus according to the present invention. It is a block diagram which shows the structure of the conventional image forming apparatus. It is a timing chart which shows the production | generation timing of a sample hold signal. It is a block diagram which shows the structure of the conventional sample hold signal generation circuit. It is a timing chart explaining operation | movement of the conventional sample hold signal generation circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... LSU controller, 2 ... LSU unit, 3 ... CPU, 4 ... Operation panel, 5 ... Various control motors, 6 ... CCD, image processing block, 7 ... Drum, developing unit, 10 ... Sample hold signal generation circuit, 11 ... Line synchronization signal cycle measuring device, 11a ... clock counter, 11b ... latch, 12 ... minimum cycle extraction circuit, 12a ... minimum cycle extraction comparator, 12b ... line synchronization signal cycle storage device, 12c ... write enable terminal, 13 ... calculator , 13a ... subtractor, 14 ... timing generation counter, 15 ... sample hold signal generation comparator, 16 ... latch circuit, 17 ... timing device, 17a ... timer, 17b ... clock, 17c ... minimum cycle update time storage device, 17d ... Subtractor, 18 ... elapsed time comparator, 19 ... second timing device, 19a ... timer, 20 ... second passage Intercomparator, 31 ... Line synchronization signal period measuring device, 32 ... Minimum period extraction circuit, 33 ... Calculator, 33a ... Divisor, 33b ... Multiplier, 34 ... Timing generation counter, 35 ... Sample hold signal generation comparator, 40 ... polygon motor 131 ... calculator 132 ... calculator 133 ... first calculator 134 ... second calculator 151 ... sample hold signal generator comparator 152 ... sample hold signal generator comparator 153 ... Sample hold signal generation comparator, 154. Sample hold signal generation comparator, 155... Logic circuit.

Claims (26)

  A line generation signal that is used in an electrophotographic image forming apparatus that scans a photosensitive drum and writes image information, and that generates a predetermined signal for each scanning period, and that measures the period of the line synchronization signal. A period measuring device, a minimum period extracting circuit for extracting a minimum period from the previous line synchronizing signal periods output by the line synchronizing signal period measuring device, and a minimum period of the line synchronizing signal output by the minimum period extracting circuit; And a computing unit that calculates an output timing of the predetermined signal based on the line synchronization signal.   2. The signal generation circuit according to claim 1, wherein the line synchronization signal period measuring device includes a clock counter that counts the number of clocks based on the line synchronization signal, and a latch that latches the clock count value in synchronization with the line synchronization signal. A signal generation circuit characterized by comprising:   The signal generation circuit according to claim 1, wherein the minimum period extraction circuit stores a line synchronization signal period storage device that stores a minimum period of a line synchronization signal, and a line synchronization signal stored in the line synchronization signal period storage device. A signal generation circuit comprising a minimum period extraction comparator for comparing a minimum period and a period of a line synchronization signal measured by the line synchronization signal period measuring device.   2. The signal generation circuit according to claim 1, wherein the computing unit calculates a timing at which the predetermined signal is output by subtracting a first threshold value from a minimum period of a line synchronization signal output from the minimum period extraction circuit. A signal generation circuit comprising: a subtractor that performs the subtraction.   5. The signal generation circuit according to claim 4, wherein the first threshold value is rewritable.   2. The signal generation circuit according to claim 1, further comprising a latch circuit that latches a minimum cycle of a line synchronization signal output from the minimum cycle extraction circuit.   7. The signal generation circuit according to claim 6, wherein the latch permission signal input to the latch circuit is output based on an elapsed time from the time when the minimum cycle of the line synchronization signal is updated. circuit.   2. The signal generation circuit according to claim 1, further comprising a timing device that measures an elapsed time from a time when the minimum cycle of the line synchronization signal is updated.   2. The signal generation circuit according to claim 1, wherein the minimum cycle extraction circuit outputs a minimum cycle update flag when the minimum cycle of the line synchronization signal is updated.   4. The signal generation circuit according to claim 3, wherein the minimum cycle extraction comparator outputs a minimum cycle update flag when the minimum cycle of the line synchronization signal is updated.   9. The signal generation circuit according to claim 8, wherein the timing device is a timer that starts an operation based on a minimum cycle update flag that is output when the minimum cycle of the line synchronization signal is updated by the minimum cycle extraction circuit. A signal generation circuit characterized by the above.   9. The signal generation circuit according to claim 8, wherein the timing device triggers a clock for measuring a current time, and a minimum period update flag that is output when the minimum period of the line synchronization signal is updated by the minimum period extraction circuit. As a minimum cycle update time storage device for updating the minimum cycle update time to the current time output by the clock, and subtracting the minimum cycle update time from the current time and outputting the elapsed time since the minimum cycle update time is updated A signal generation circuit comprising a subtractor.   8. The signal generation circuit according to claim 7, wherein the latch permission signal input to the latch circuit is a second time when the elapsed time from the time when the minimum cycle of the line synchronization signal is updated indicates the sampling end timing of the line synchronization signal. The signal generation circuit is controlled according to whether or not the threshold value is exceeded.   2. The signal generation circuit according to claim 1, wherein the minimum period extraction circuit is capable of accepting a line synchronization signal period capturing permission signal for controlling whether or not to sample the period of the line synchronization signal. Signal generation circuit.   15. The signal generation circuit according to claim 14, wherein a line synchronization signal period capture permission signal input to the minimum period extraction circuit is controlled by a CPU.   The signal generation circuit according to claim 1, further comprising a second timing device that measures an elapsed time after the polygon motor starts rotating.   17. The signal generation circuit according to claim 16, further comprising a second elapsed time comparator for comparing an elapsed time after the polygon motor starts rotating and a third threshold value indicating a sampling start timing of the line synchronization signal. A signal generation circuit characterized in that the line synchronization signal period capture permission signal of the minimum period extraction circuit is controlled based on a comparison result of the second elapsed time comparator.   2. The signal generation circuit according to claim 1, wherein the generation timing output from the arithmetic unit is a timing at which the output of the predetermined signal is started.   2. The signal generation circuit according to claim 1, wherein the generation timing output by the arithmetic unit is a timing at which the output of the predetermined signal is terminated.   A line generation signal that is used in an electrophotographic image forming apparatus that scans a photosensitive drum and writes image information, and that generates a predetermined signal for each scanning period, and that measures the period of the line synchronization signal. A period measuring device, a minimum period extracting circuit for extracting a minimum period from the previous line synchronizing signal periods output by the line synchronizing signal period measuring device, and a minimum period of the line synchronizing signal output by the minimum period extracting circuit; A first arithmetic unit that calculates an output start timing of the predetermined signal based on the line synchronization signal, and a line synchronization signal based on the minimum period of the line synchronization signal output from the minimum period extraction circuit A second computing unit that calculates an output end timing of the predetermined signal and an output start timing of the predetermined signal output by the first computing unit. A first sample-and-hold signal generation comparator that generates an output start signal of the predetermined signal, and an output end of the predetermined signal based on an output end timing of the predetermined signal output from the second computing unit. A second sample-and-hold signal generation comparator for generating a signal, and determining whether to output the predetermined signal according to the output level of the signal output start signal and the signal output end signal. Signal generating circuit.   A line generation signal that is used in an electrophotographic image forming apparatus that scans a photosensitive drum and writes image information, and that generates a predetermined signal for each scanning period, and that measures the period of the line synchronization signal. A period measuring device, a minimum period extracting circuit for extracting a minimum period from the previous line synchronizing signal periods output from the line synchronizing signal period measuring device, and a minimum line synchronizing signal period output from the minimum period extracting circuit; And a first constant for designating the division unit of the line synchronization signal and a second constant indicating the output position of the sample hold signal with reference to the input of the line synchronization signal to calculate the output timing of the predetermined signal. A signal generation circuit comprising: an arithmetic unit;   23. The signal generating circuit according to claim 21, wherein the arithmetic unit divides a minimum line synchronization signal period output from the minimum period extraction circuit by a first constant to calculate a set unit of the predetermined signal. And a multiplier that multiplies a set unit of the predetermined signal by a second constant to calculate the generation timing of the predetermined signal.   3. The signal generation circuit according to claim 2, further comprising a signal line for connecting an output of the clock counter to a sample and hold signal generation comparator for outputting the predetermined signal.   An image forming apparatus comprising the signal generation circuit according to claim 1.   An image forming apparatus capable of outputting a plurality of printing colors, comprising a plurality of signal generation circuits according to claim 1 for each printing color.   26. The image forming apparatus according to claim 25, further comprising an individual signal line for setting a set value for each print color.

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