JP2007134975A - Digital modem - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital modem which is suitable for a transmission line that is not in good condition, high in frequency usage efficiency, and of simple configuration. <P>SOLUTION: Spread signal data of 256 samples are stored in order of addresses "0" to "255" in a spread signal memory 13. The spread signals represented by the spread signal data have a nearly constant power density in a prescribed bandwidth and sharp autocorrelation characteristics. Corresponding to the bit value of transmission data branching off by a transmission control circuit 11, an address forming circuit 12 forms addresses and outputs them and lets the spread signal memory 13 output the spread signal data of a first to a 256th sample or the spread signal data of a 128th to a 256th sample, and a first to a 127th sample. The following 64 addresses are inputted, and a guard interval is added. These are subjected to digital-analog conversion through a D-A converter 17, and sent out to a transmission line. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a digital modulation / demodulation device, and more particularly to a digital modulation / demodulation device that is suitable for poor transmission paths, has high frequency utilization efficiency, and has a simple configuration.

  In the conventional narrow band digital modulation system, when noise of the frequency of the transmission signal is unavoidable, the transmission power may be increased and the C / N ratio (Carrier to Noise ratio) may be increased. However, there is an upper limit on transmission power for technical or legal reasons. For this reason, there is a problem that communication failure is easily caused by noise in the transmission band.

By the way, according to Shannon's communication capacity theorem, the upper limit of the communication capacity C [bit / s] is given by the following equation by the bandwidth B [Hz], the signal power S [W], and the noise power N [W]. . Note that log ₂ indicates a logarithmic operation with 2 as the base.
C = B log ₂ (1 + S / N) (1)

  As can be seen from the equation (1), when the signal power S is a predetermined value, the bandwidth B can be widened according to the noise level N in order to secure a desired communication capacity C. The communication system that embodies this is the spectrum spread (SS) system, and the main ones are the frequency hopping (FH) system and the direct spread (Direct Spread / Direct Sequence; DS) system. There is.

  In the frequency hopping method, the spectrum of the original signal is switched (hopped) in a short period and spread over a wide band. For this reason, a high-accuracy frequency synthesizer (mixer) that operates at high speed is required at both the transmitting end and the receiving end, and if a fault occurs in each hopped signal, a bit error occurs. An error correction circuit is required. For this reason, in general, the modem is complicated and expensive.

  In the direct spreading method, the spectrum of the original signal is directly spread over a wide band using a spreading code. For this reason, compared with the frequency hopping method, there is generally an advantage that the configuration of the modem is simple and the cost is low.

  However, the signal in the transmission line deteriorates due to the influence of the group delay. This influence is greater in a wired transmission path that passes through various lines and connection points in a complicated manner than in a wireless transmission path by radio wave propagation in free space. As a result, a plurality of correlation peaks between the received signal and the spread code are detected at the receiving end, which makes it difficult to demodulate.

  Therefore, conventionally, a signal received by an antenna is amplified by an amplifier, and then a narrowband interference wave removal circuit that limits a signal whose level is higher than its saturation level on the frequency axis by a magnetostatic filter, and rake synthesis that performs delay synthesis There has been proposed a “spread spectrum communication apparatus” including a receiver or a PDI (Postdetection Integration) receiver (see, for example, Patent Document 1).

  Conventionally, for a binary input signal of 1/1, a sweep signal whose amplitude frequency characteristic is constant and whose phase changes in proportion to the square of the frequency is made to correspond to 1, and the time axis of this sweep signal There has been proposed a “digital modulation / demodulation device” in which a signal obtained by inverting the signal corresponds to −1 (see, for example, Patent Document 2).

  In addition, conventionally, a plurality of antenna elements and corresponding radio receiving units are provided, and a calibration signal for correcting delay characteristics and amplitude characteristics of received signals in these radio receiving units is input to the radio receiving unit. An antenna wireless receiver calibration apparatus ”has been proposed (see, for example, Patent Document 3).

  Conventionally, a transmission signal in which data and pilot are QPSK modulated to generate a narrow-band complex baseband signal, and subcarriers obtained by spreading each of the branched signals are multiplexed to add a pilot signal. Has been proposed (see, for example, Patent Literature 4).

Japanese Patent No. 3132399 (paragraphs 0020,0026, FIG. 4, FIG. 6) JP 2002-64570 A (paragraphs 0014 to 0018, FIGS. 2 and 3) Japanese Patent No. 3369466 (paragraphs 0039-0043, FIG. 1) JP 2003-143111 A (paragraphs 0023 to 0028, FIGS. 1 to 3)

  However, in the conventional “spread spectrum communication device” (described in Patent Document 1), the magnetostatic wave filter is provided for the purpose of removing the narrowband interference wave, but the level of the spread signal can be specified by the frequency and time. In addition, since the frequency of the narrowband jamming wave is usually indefinite, it is difficult to sufficiently remove the narrowband jamming wave from the received signal. In the first place, in the direct spreading method, the narrow-band interference wave component becomes a low-level component in a wide band due to despreading at the time of demodulation, and thus can normally be ignored. The rake combiner or the PDI receiver is for synthesizing a signal in which a group delay is caused by a magnetostatic wave filter, and if a magnetostatic wave filter is not provided, these are also unnecessary. Therefore, the “spread spectrum communication apparatus” has a complicated configuration and has problems that are not suitable for application to a transmission line in which group delay is likely to occur.

  Further, in the conventional “digital modulation / demodulation device” (described in Patent Document 2), the sweep signal corresponding to “1” has a high frequency in the vicinity of the head on the time axis, and the frequency decreases toward the tail. The sweep signal corresponding to 0 ″ has a low frequency near the beginning on the time axis, and the frequency increases toward the tail. Therefore, during transmission of one sweep signal, the occupied frequency bandwidth is narrow and continuously changes in one direction (the direction in which the frequency is high or low). Therefore, when the transmission signal is observed in a relatively short time window, only a part of the frequency is used, and the front end or the rear end of the sweep signal is almost in the state of no signal. there were.

  Further, the conventional “calibration apparatus for array antenna wireless reception device” (described in Patent Document 3) is provided with a plurality of antennas, and therefore corrects delay characteristics and amplitude characteristics that are different among the antennas. . That is, the delay characteristics in the free space as the transmission path are not uniform, and there is a problem that, for example, the group delay in the transmission path that tends to occur in the wired transmission path cannot be dealt with.

  In the multi-carrier CDMA transmitter (described in Patent Document 4), the frequency spectrum of each channel (subcarrier) is widened by frequency spread modulation, but the profile itself is the spectrum of the original narrowband modulated signal. The profile is still stretched in the frequency direction. Therefore, even if filtering is performed appropriately, the profile of the frequency spectrum of the average power of each channel has a mountain shape, and the power density is low at the peripheral portion of the band. Here, increasing the number of channels (number of branches) to increase frequency utilization efficiency increases the number of multipliers and the amount of computation of inverse discrete Fourier transform, which increases the circuit scale and makes the device complex. There was a problem to become.

  Furthermore, in the direct spreading method, when the bit rate is the same, if the signal is spread at a higher chip rate at the transmitting end, and a signal in a wider frequency band is generated and transmitted, the S / N ratio of the transmission path is increased. Even if it is lower, transmission data can be demodulated at the receiving end. However, if the chip rate is increased, the signal is spread over a wider band and is easily affected by the group delay, and if the group delay applied to the transmission signal in the transmission path is more than half of the chip rate, it is between the spreading codes. Since code interference occurs at the receiving end, despreading cannot be performed on the receiving side, and transmission data cannot be demodulated.

  In wireless communication, since free space is used as a transmission path, the group delay is relatively small, and if the multipath path delay is longer than one chip, rake reception can be performed to integrate the processing gain. However, in wire transmission, a group delay is likely to occur at a relay point or a connection point in the transmission path, so that the bit error rate increases when the chip rate is increased. Therefore, in wired communication, when the state of the transmission path is poor (for example, when the S / N ratio is low or the noise level N is unstable), the bandwidth is increased according to equation (1). Even if it is attempted to cope with the problem by expanding B, there is a problem in that transmission data may not be demodulated normally even if spreading demodulation is performed at the receiving end due to code interference between the spread symbols due to the influence of group delay. It was.

  Accordingly, an object of the present invention is to provide a digital modulation / demodulation device that is suitable for an unsatisfactory transmission line, has high frequency utilization efficiency, and has a simple configuration.

  In order to solve the above-described problem, a digital modulation / demodulation device according to the present invention is a digital modulation / demodulation device for transmitting information data using an information signal that is spread spectrum and represents information data, and has power within a predetermined frequency bandwidth. A spread signal memory in which spread signal data representing a spread signal having a substantially constant density and having sharp autocorrelation characteristics and having a predetermined number of samples is stored in a storage position for each sample corresponding to the time order of the spread signal; and the information data A read start position determining means for determining a read start position in the storage position according to the spread signal memory, the spread signal data for the predetermined number of samples from the read start position sequentially output in the order of time, When reading from the last storage position is completed, the modulation data is returned to the first storage position and output continuously. Start position modulation means for forming, and guard interval addition means for reading the spread signal data by a predetermined guard interval length and forming guard interval data following the start position modulation means, and the guard interval is included in the modulation data. A modulation circuit for outputting information signal data to which data is added; and a DA converter for generating the information signal by performing digital-analog conversion on the information signal data output from the modulation circuit. It is characterized by.

  According to the present invention, a digital modulation / demodulation apparatus that can perform data transmission even when communication conditions are not favorable can be realized with a simple configuration.

  Next, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, a first embodiment according to the present invention will be described with reference to FIGS.

(First embodiment)
As shown in FIG. 1, the digital modulation / demodulation device 101 according to the first embodiment of the present invention has one end connected to an information device (not shown) and the other end connected to a transmission line (not shown). It is a device for mediating transmission / reception of discrete information (information data) through this transmission path by an information device. That is, when the digital modulation / demodulation apparatus 101 receives information data (transmission data) from the information apparatus, the digital modulation / demodulation apparatus 101 generates a transmission signal (transmission signal) based on the data and transmits the transmission signal to the transmission path, and transmits the transmission signal (reception) from the transmission path. When the signal is received, information data (received data) is extracted based on the received signal and output to the information device.

  The information data (transmission data and reception data) will be described as being serially transmitted by a binary baseband signal such as a unipolar NRZ (Non Return to Zero) signal. It is possible to use other signal systems and transmission systems as long as the signals can be handled. The transmission signal (transmission signal and reception signal) is a spread spectrum signal, and is a wideband signal having an occupied frequency band of, for example, several tens to several thousand times the Nyquist frequency of the baseband signal. .

  The information device has a function of sending transmission data to the digital modulation / demodulation device 101 and receiving reception data from the digital modulation / demodulation device 101. Typically, the information device is a personal computer having a communication port or a PDA (Personal Digital Assistance; personal digital assistant). Etc.

  The transmission path may be either a wired transmission path or a wireless transmission path. For example, power line carrier communication can be performed using a power line in a home or the like, or a subscriber line of a subscriber telephone can be used as a digital subscriber line (DSL). When a wireless transmission path is used, the digital modulation / demodulation apparatus 101 is connected to an aerial system (both not shown) including an aerial line and a feed line via a frequency converter, a power amplifier, and the like.

  The digital modulation / demodulation apparatus 101 includes a transmission unit 10 that converts transmission data into transmission signals and outputs, a reception unit 40 that converts reception signals into reception data, and a clock generator that supplies a clock signal to each unit in the digital modulation / demodulation apparatus 101 30.

  The clock generator 30 has a clock cycle that is the same as a sample cycle, which is a unit for handling a transmission signal and a reception signal in a discrete manner on the time axis, and generates a clock signal indicating a timing for each clock cycle. It is.

  Next, the transmission unit 10 will be described in detail with reference to FIGS.

  As illustrated in FIG. 1, the transmission unit 10 includes a transmission control circuit 11, an address generation circuit 12, a spread signal memory 13, a synchronization signal memory 14, a sign inverter 15, a switching circuit 16, and a DA. And a converter 17 (digital-analog converter).

  The transmission control circuit 11 has a function of controlling each unit in the transmission unit 10 in order to modulate transmission data into a transmission signal. The transmission data input to the digital modulation / demodulation apparatus 101 is input to the transmission control circuit 11 in the transmission unit 10. The transmission control circuit 11 first collects the transmission data in units of 2 bits. Then, a polarity signal representing the polarity corresponding to the upper bits is generated from the 2-bit transmission data and output to the sign inverter 15, and the lower bits data is output to the address generation circuit 12. The case where the polarity is “positive” when the high-order bit is “0” and “negative” when “1” is described will be described. However, the polarity may be reversed. Further, the transmission control circuit 11 has a function of detecting the timing of the end of output of synchronization signal data from the synchronization signal memory 14 described later and generating a switching signal for controlling the switching circuit 16.

  The synchronization signal memory 14 and the spread signal memory 13 each have a storage function for storing data to be described later, and the storage position is positioned by M consecutive addresses from “0” to “M−1”. Yes. Details of these will be described later.

  The address generation circuit 12 has a function of generating an address according to the value of input data (the value of the lower bits of the two bits) and outputting it according to the clock signal. The address generation circuit 12 associates two values selected from “0” to “M−1” with the two values “0” and “1” of the input data (the lower-order bits), thereby starting position (One of the addresses of the synchronization signal memory 14 and the spread signal memory 13) is determined. As an example, the case where the input value “0” corresponds to the start position “0” and the input value “1” corresponds to the start position “M / 2” will be described. It may be configured. In this case, the difference between these two types of start positions (addresses) is preferably “M / 2”.

  Therefore, as shown in FIG. 2, for the transmission data collected every two bits by the transmission control circuit 11, a combination of the polarity indicated by the polarity signal and the start position generated by the address generation circuit 12 is obtained.

  As a result, as shown in the table of FIG. 2, the polarity of the spread code is inverted or non-inverted by the code inverter 15 according to the 2-bit transmission data collected by the transmission control circuit 11, and the spread signal memory 13 is output. The first address to perform is determined. Thus, in one information signal in the transmission signal, the value of 2-bit transmission data is expressed by the combination of the signal polarity and the deviation of the signal waveform on the time axis.

  The synchronization signal memory 14 stores synchronization signal data for M samples, which is sampling data of the synchronization signal, in correspondence with the ascending order of addresses in the order of sample numbers. This synchronization signal can be converted into synchronization signal data by the A / D converter 47 of the receiver 40 described later, and the start point of the information signal data (described later) following the synchronization signal data can be detected by this synchronization signal data. I just need it.

  The spread signal memory 13 stores spread signal data for M samples, which is the spread signal sampling data, in correspondence with the ascending order of addresses in the order of sample numbers.

As shown in FIG. 3A, the spread signal is a pseudo noise (PN) signal obtained by converting the spread signal data by the DA converter 17 and whose signal level changes like noise. is there.
As shown in FIG. 3B, this spread signal has a very steep autocorrelation characteristic.
Further, the spread signal is assumed to have a substantially constant power density in a desired band. That is, it is preferable that the frequency spectrum of the power density of the spread signal exhibits a flat profile close to a rectangle within a predetermined band.

  In order to generate a spread signal having a flat frequency spectrum and high autocorrelation, for example, the following process is performed. That is, first, discrete frequency spectrum data is randomly generated within a desired band, and this data is subjected to IFFT (Fast Inverse Fourier Transform) processing to create time-axis sampling data of this signal. A plurality of similar data is created. Next, the autocorrelation of each of these data is obtained, and one having good autocorrelation (sharp correlation value peak and few spurious) is selected from the data, and is set as spread signal data.

  The spread signal data may be calculated in advance by another computer (not shown) or the like and stored in the spread signal memories 13 and 43. This eliminates the need for a circuit for generating a pseudo-spread code every time communication is performed, thereby reducing the circuit scale.

  Returning to FIG. 1, the address generation circuit 12 outputs M + G addresses starting from the determined start position to the synchronization signal memory 14 and the spread signal memory 13 in synchronization with the clock signal from the clock generator 30. When the output address reaches the final “M−1”, it returns to the address “0” and outputs in the same manner.

  Here, G addresses are added to generate a guard interval to be described later. Although the case where the guard interval length is 64 samples will be described, the guard interval length is increased when the group delay of the transmission path is large, and is shortened when the transmission delay is small. If the effect of group delay does not substantially appear, it is not necessary to provide a guard interval.

  That is, when the input data is “0”, the address generation circuit 12 outputs the addresses “0” to “M−1” and subsequently the addresses “0” to “G−1”. . Similarly, when the input data is “1”, the addresses “M / 2” to “M−1” and subsequently, the addresses “0” to “M / 2−1 + G” are output. Specifically, when the input data is “0”, addresses “0” to “255” and “0” to “63” are output, and when the input data is “1”, the address “128” to “255” and “0” to “191” are output.

  The sign inverter 15 synchronizes with the clock signal from the clock generator 30 and each time one sample of data is input from the spread signal memory 13, this data according to the polarity signal input from the transmission control circuit 11. Has a function of performing the arithmetic processing so that the polarity of the signal indicated by is kept non-inverted or inverted, and outputs the result to the switching circuit 16. Specifically, when the polarity signal is “positive”, the data is output as non-inverted, and when the polarity signal is “negative”, the data is inverted and output. As a result, the upper bits of the 2-bit transmission data collected by the transmission control circuit 11 are expressed.

  The switching circuit 16 has a function of switching between the output of the synchronization signal memory 14 and the output from the sign inverter 15 in accordance with the switching signal from the transmission control circuit 11 and outputting to the DA converter 17.

  The DA converter 17 performs digital-analog conversion based on the data input from the switching circuit 16, generates a transmission signal, and sends it to the transmission path.

  As shown in FIG. 4A, the transmission signal is composed of a synchronization signal transmitted in the leading synchronization frame D0 and information signals transmitted in information frames D1, D2,. Since the synchronization signal is a signal for providing frame synchronization, the value of the input data is not expressed. Each information signal represents two bits of input data. Therefore, according to this transmission signal, 2 × k-bit transmission data can be transmitted.

  As shown in FIG. 4B, the information signal is modulated by changing the time axis of the spread signal in accordance with the lower bits of the input data for 2 bits, and then the head part of this signal is copied to the rear end. In addition, a guard interval is generated, and the polarity (positive / negative) is inverted / non-inverted according to the upper bits of the input data.

  In this information signal, the signal from the first sample to the 256th sample in the front is the main body of the modulation signal, and the signal from the 257th sample to the 320th sample in the rear is the signal from the first sample to the 64th sample. Is a guard interval signal obtained by copying.

  In this digital modulation / demodulation apparatus 101, a transmission signal is generated by adding a guard interval of a predetermined length to a signal corresponding to one code period in order to avoid group delay in the transmission path. Therefore, after reading the data for one code period from the spread signal memory 13, it returns to the head address, reads the data corresponding to the guard interval length, and adds the data read later as the guard interval to the previously read data. Then, transmission waveform data is generated.

  This information signal outputs the spread signal data from the address “0” to the address “63” following the spread signal data from the address “0” to the address “255”, and based on the sampling data string thus obtained. In addition, a transmission signal to which a guard interval is added is generated. In this case, the guard interval length is 64 samples, and the length of the transmission signal corresponding to 2 bits of transmission data is 320 samples.

  Next, the receiving unit 40 will be described in detail with reference to FIGS. 1 to 4 again.

  Returning to FIG. 1, the receiving unit 40 includes an A / D converter 47, a GI removal circuit 44, a synchronization detector 45, a reception control circuit 41, an address generation circuit 42, a spread signal memory 43, and a correlator. 50a, a correlator 50b, and a maximum value detection circuit 46. The received signal input to the receiving unit 40 is input to the AD converter 47. Although this received signal may be affected by group delay, signal power reduction, or noise component superposition during transmission, it can be handled in the same way as a transmission signal in the demodulation process.

  When the reception signal is input, the A-D converter 47 has a function of performing analog-digital conversion and generating reception signal data which is a data string representing the reception signal. The A-D converter 47 includes a preamplifier, a band-pass filter (none of which are shown), and the like, depending on the type and state of the transmission path. As described above, since the transmission signal and the reception signal are substantially equivalent, the transmission signal data input to the DA converter 17 and the reception signal data output from the AD converter 47 are different from each other. Is substantially equivalent.

  The synchronization detector 45 monitors the received signal data from the A-D converter 47 and, when detecting the synchronization signal data from the received signal data, generates a trigger signal that gives frame synchronization of the information frame. The synchronization detector 45 further monitors this received signal data and generates a trigger signal at the start of each information frame. These trigger signals are supplied to each unit in the receiving unit 40.

  The GI removal circuit 44 has a function of removing GI (guard interval) from the received signal data for each information frame and outputting the data (modulated data) in synchronization with the clock signal from the clock generator 30. Have. Specifically, the GI removal circuit 44 extracts and outputs the first to 256th samples from the first sample in order to remove the guard interval of 64 samples from the information signal of 320 samples for one information frame, The 320th sample is removed from the rear 257th sample (that is, it is not used in the subsequent correlation processing), and is sequentially output for each sample. Alternatively, since the 64 samples from the front end and the 64 samples from the rear end are the same in principle, the 64th sample is removed from the first front sample, and the 320th sample from the 65th sample is removed. You may make it output.

  The reception control circuit 41 is a circuit for controlling each part in the reception unit 40 such as the address generation circuit 42 and the maximum value detection circuit 46 according to the trigger signal from the synchronization detector 45 and the clock signal from the clock generator 30. is there.

  The address generation circuit 42 has a function of generating an address as described below under the control of the reception control circuit 41 and outputting it in synchronization with the clock signal described above according to the start point of the information frame. In short, the address generation circuit 42 has a function equivalent to that of two address generation circuits 12 having different input data values. That is, the address generation circuit 42 includes (1) a first address string from addresses “0” to “255”, and (2) addresses “128” to “255” and “0” to “127”. Are generated and output for each address (that is, two addresses simultaneously).

  The spread signal memory 43 stores the same spread signal data as the spread signal memory 13 at the same address. The spread signal memory 43 further outputs spread signal data to the correlator 50a in accordance with the first address string input from the address generation circuit 12, and spread signal data to the correlator 50b in accordance with the second address string. Has simultaneous output function.

  Therefore, for each information frame, spread signal data from the first sample to the 256th sample is sequentially input to the correlator 50a, and the correlator 50b is input from the 129th sample to the 256th sample and from the first sample to the first sample. Spread signal data consisting of up to 128 samples is sequentially input.

  The correlator 50a and the correlator 50b are product-sum calculators and may have the same configuration. The correlator 50a includes a multiplier 51a and an accumulator 52a, and the correlator 50b includes a multiplier 51b and an accumulator 52b. In the correlator 50a, the multiplier 51a multiplies the modulated data from the GI removal circuit 44 and the spread signal data from the spread signal memory 43 for each sample in synchronization with the clock signal from the clock generator 30. Then, the multiplication value is output to the integrator 52a. The integrator 52 a outputs the integrated value obtained by integrating the multiplied values, that is, the correlation value Ca, to the maximum value detecting circuit 46. Similarly, in the correlator 50b, the multiplier 51b and the multiplier 52b perform processing, and the correlation value Cb is output to the maximum value detection circuit 46.

  The reception control circuit 41 outputs a reset signal to the integrator 52a and the integrator 52b in response to the trigger signal from the synchronization detector 45. Thereby, the integration value is reset every time the information frame starts in the integrator 52a and the integrator 52b.

  The maximum value detection circuit 46 has a function of generating reception data bit by bit based on the combination of the correlation value Ca and the correlation value Cb and outputting the reception data to the outside of the reception unit 40 (information device (not shown)).

  Specifically, if the correlation values Ca and Cb are larger than a threshold value having a positive magnitude, it is determined that there is a positive correlation. If the correlation values Ca and Cb are smaller than a threshold value having a negative magnitude, a negative value is determined. Judge that there was a correlation. When either the correlation value Ca or the correlation value Ca indicates a positive correlation, the upper bit is determined as “0”, and when the correlation value Ca indicates a negative correlation, the upper bit is determined as “1”. . Subsequently, when the correlation value Ca indicates correlation, the lower bit is determined as “0”, and when the correlation value Cb indicates correlation, the lower bit is determined as “1”. In this way, reception data for 2 bits is generated and output to the outside of the receiving unit 40. If these conditions are not satisfied, the received data is indefinite and no output is performed.

This is summarized as follows. This corresponds to the table shown in FIG.
―――――――――――――――――
Correlation value Correlation value Output Ca Cb received data ―――――――――――――――――
Positive 00
0 positive 01
Negative 0 10
0 Negative 11
―――――――――――――――――

  Next, a specific example from the correlation process to the data generation process will be described with reference to FIGS.

  As shown in FIG. 5A, when a signal having a positive polarity and a starting position of “0” is input, as shown in FIG. 5B, a correlator 50a (Ca in the graph) and a correlator 50b. (Cb in the graph) outputs the accumulated correlation value Ca and correlation value Cb, respectively. Looking at the integrated values (correlation value Ca and correlation value Cb) after 256 samples, which is one spread signal period, the output (Ca) of the correlator 50a shows a high value close to “1”, and the output of the correlator 50b is It shows almost “0”. Therefore, the maximum value detection circuit 46 determines that the correlation value Ca from the correlator 50a is “positive” and the correlation value Cb from the correlator 50b is “0”, and outputs received data “00”.

  As shown in FIG. 6A, when a signal having a polarity of “negative” and a start position of “M / 2” is input, as shown in FIG. 6B, a correlator 50a (Ca in the graph). The correlator 50b (Cb in the graph) outputs the accumulated correlation value Ca and correlation value Cb, respectively. Looking at the integrated value (correlation value Ca and correlation value Cb) after 256 samples, which is one spread signal period, the output of the correlator 50a (Ca in the graph) shows almost “0”, and the output of the correlator 50b (graph) Cb) shows a low value close to “−1”. Therefore, the maximum value detection circuit 46 determines that the correlation value Ca from the correlator 50a is “0” and the correlation value Cb from the correlator 50b is “negative”, and outputs received data “11”.

  The example shown in FIG. 5 shows a communication state in which the signal-to-noise ratio (S / N ratio) is as large as 60 dB and the influence of noise added in the transmission path can be practically ignored. On the other hand, in the example shown in FIG. 6, the signal-to-noise ratio (S / N ratio) is as very small as 0 dB, and the noise power added in the transmission path is almost the same as the signal power of the received signal. Indicates a large communication state. Referring to FIG. 5 and FIG. 6, it can be understood that data can be normally demodulated even in a poor communication state with large noise, as a matter of course in a good communication state.

  In this way, since the calculation for each sample clock only needs to be the product-sum operation, the processing load and the circuit scale are small, and the despreading processing is realized by integration, so the transmission line with a low S / N ratio. Also, the data error of the demodulated received data is reduced.

(Extended example of the first embodiment)
Note that a case where two types of start positions, that is, two types of addresses (“0” and “M / 2”) in the spread signal memory 13 are used to represent one bit of information in the information signal will be described. However, it may be configured to use more types of start positions. As a result, the amount of information that can be transmitted with an information signal for one information frame can be increased, and the data transmission rate can be increased. For example, when modulation / demodulation is performed with four start positions (“0”, “M / 4”, “2M / 4”, “3M / 4”), 3 bits can be transmitted with an information signal for one information frame. A data transmission rate of 1.5 times the example is obtained.

According to the digital modulation / demodulation apparatus 101, for example, the following effects can be obtained.
(1) Since the spread signal data is stored in advance in the spread signal memory 13 and the spread signal memory 43, it is not necessary to generate a spread code every time modulation / demodulation is performed, the processing load and the circuit scale can be reduced, and the configuration is simple. Become.
(2) Since the spread signal used in the digital modulation / demodulation apparatus 101 is a signal spread in the spectrum so as to have a flat power density over the occupied frequency band, the frequency utilization efficiency is improved. In addition, since the multiplexing with a plurality of carriers is not performed in order to improve the frequency utilization efficiency, a simple configuration is sufficient.
(3) Since the guard interval portion is added to the transmission signal, the influence of the group delay can be suppressed, and data transmission can be performed using a transmission path with poor conditions.
(4) Since correlation processing is performed by a single product-sum operation and the received data is demodulated, the processing load and the circuit scale can be reduced.
(5) Since despreading is performed by the product-sum operation in the correlation processing, data transmission can be performed using a transmission line that is not easily affected by the narrowband interference wave and has a low S / N ratio.

  Next, the second to seventh embodiments according to the present invention will be described with reference to FIGS. 7 to 14. In principle, these embodiments will be described above except for the following description. It is assumed that this is the same as the first embodiment.

(Second Embodiment)
The digital modulation / demodulation device (not shown) of the second embodiment has a configuration including a reception unit 40b instead of the reception unit 40 of the digital modulation / demodulation device 101 (see FIG. 1) of the first embodiment.
As shown in FIG. 7, the receiving unit 40 b includes a comparator 48 instead of the A / D converter 47 of the receiving unit 40 described above.

  The comparator 48 has a 1-bit A / D conversion function, detects the polarity of the reception signal for one information frame based on the clock signal from the clock generator 30, and represents the upper bits of the reception signal representing 2 bits It is a circuit which determines. The level of the signal output from the comparator 48 represents the upper 1 bit represented by one information frame, and the timing of this signal represents the lower 1 bit. An output signal from the comparator 48 is input to the GI removal circuit 44 and the synchronization detector 45.

  The GI removal circuit 44 removes the guard interval from the input signal and outputs it to the correlator 50a and the correlator 50b.

  The correlator 50a and the correlator 50b calculate the sum of products of the input signal value and the data value from the spread signal memory 43 in synchronization with the clock signal, and set the correlation value Ca and the correlation value Cb to the maximum values. Output to the detection circuit 46.

  The maximum value detection circuit 46 generates and outputs 2-bit reception data for each information frame based on the correlation value Ca and the correlation value Cb.

  According to this digital modulation / demodulation device, since one bit is determined for each information frame by the comparator 48 and demodulation is performed, it is sufficient to perform a correlation operation on one bit of the information bits, and the correlation processing load at the time of demodulation is increased. The circuit size of the receiving unit 40b can be reduced and the configuration can be simplified.

(Third embodiment)
As illustrated in FIG. 8, the digital modulation / demodulation device 103 according to the third embodiment includes a transmission unit 10 c instead of the transmission unit 10 according to the first embodiment, and includes a reception unit 40 c instead of the reception unit 40. Have.

  First, the transmission unit 10c will be described. The transmission unit 10c has a configuration in which a differential modulator 20 is added to the transmission unit 10 (see FIG. 1) of the first embodiment. The transmission data output to the transmission unit 10 c is input to the differential modulator 20. The differential modulator 20 differentially modulates the transmission data as will be described later, and outputs the differential data to the transmission control circuit 11.

  As shown in FIG. 9, the differential modulator 20 includes an XOR gate 21 (exclusive OR gate) and a delay device 22. The input to the differential modulator 20 is input to the XOR gate 21. The output of the XOR gate 21 becomes the output of the differential modulator 20 and is also input to the delay unit 22. The output of the delay device 22 is input to the XOR gate 21.

The delay unit 22 stores the data currently being output from the XOR gate 21 and outputs the previous data (delayed data) value to the XOR gate 21.
The XOR gate 21 has two input terminals and one output terminal, and has a function of outputting data (differential data) obtained by calculating exclusive OR of two input data. The differential data is output outside the differential modulator 20.

  Therefore, the differential modulator 20 sets the value of the differential data to be output to “0” when the value of the newly input transmission data is equal to the value of the differential data output prior to this. To do. In addition, when the value of the newly input transmission data is different from the value of the differential data output prior to this, the value of the differential data to be output is set to “1”.

These are summarized as follows.
――――――――――――――――――――――――――
New input value Preceding output value New output value ――――――――――――――――――――――――――
0 0 0
0 1 1
1 0 1
1 1 0
――――――――――――――――――――――――――

  The output value (differential data value) of the differential modulator 20 is reset to the initial value when the input is resumed after the transmission data input is interrupted and the synchronization signal is output. The initial value is “0”, for example. At this time, if transmission data “0” is input, differential data “0” is output, and if transmission data “1” is input, differential data “1” is output.

  In the transmission unit 10c, instead of transmitting transmission data to the transmission control circuit 11, differential data is input from the differential modulator 20. However, in other operations, transmission data is read as differential data, This is performed in the same manner as the transmission unit 10 of the first embodiment. However, since the digital modulation / demodulation apparatus 103 is configured to transmit and receive 2 bits per information frame, the transmission control circuit 11 sets the value of the first 2 bits represented by the information signal following the synchronization signal to “00”. Control is performed so that

  Next, the receiver 40c will be described. The receiver 40c includes a differential demodulator 60 in addition to the receiver 40 (see FIG. 1) of the first embodiment, and includes a spread signal memory 43c instead of the spread signal memory 43. The configuration is as follows.

  The spread signal memory 43c includes two reception signal memories each having a function of storing input data in ascending order of addresses and a function of collectively erasing stored data. These received signal memories have a storage capacity capable of storing data input from the GI removal circuit 44 for at least one spread signal period.

(1) During a certain information frame, one reception signal memory stores data input from the GI removal circuit 44, and the other reception signal memory is multiplied by the multiplier 51a and the multiplication based on the control of the address generation circuit 42. The output is made to the device 51b.
(2) When the next information frame is reached, first, the received signal memory that has been output to the multiplier 51a and the multiplier 51b is erased all at once by the reset signal from the reception control circuit 41. Then, the functions of the two received signal memories are exchanged and the operation is performed in the same manner as (1).
(3) The operations of (1) and (2) are repeated alternately for each information frame.
That is, the reception signal memory being output to the multiplier 51a and the multiplier 51b operates in the same manner as the spread signal memory 43 of the first embodiment.

  The differential demodulator 60 has the same configuration as that of the differential modulator 20. In the differential demodulator 60, when new data (received data subjected to differential modulation) is input from the maximum value detection circuit 46, the XOR gate 21 causes the previous data (held by the delay unit 22 ( By calculating an exclusive OR with the received data after differential demodulation, the new data is differentially demodulated and the received data is output.

  In the present embodiment, as described above, the value (initial value) of the reception data represented by the first information signal following the synchronization signal is determined to be “00”, for example. Therefore, the received signal data of the first information frame D1 is stored in the spread signal memory 43c after the guard interval is removed, but no received data is generated at that time.

  When the reception signal of the next information frame D2 is input, in the correlator 50a and the correlator 50b, the multiplier 51a and the multiplier 51b are synchronized with the clock signal from the clock generator 30 and the spread signal memory 43c. Is multiplied by the output value from the GI removal circuit 44, and the integrator 52a and the integrator 52b respectively add these multiplied values and output the values to the maximum value detection circuit 46.

The spread signal memory 43c is a first-in first-out (FIFO) type memory, and stores the data input from the GI removal circuit 44 while outputting to the correlator 50a and the correlator 50b. Good. In this case, the address generation circuit 42 outputs the address data to the spread signal memory 43 so that the same output as described above is performed from the spread signal memory 43c.
In this way, correlation processing is performed on the preceding and following received signals, and the transmission data is demodulated.

  According to this digital modulation / demodulation device 103, even if a received signal is affected by signal distortion during transmission, a spread signal used for correlation processing of the received signal is also generated from the received signal immediately before receiving the signal distortion. Therefore, the influence of signal distortion is canceled out. For this reason, even if a transmission line with large signal distortion is used, data transmission errors can be suppressed.

(Fourth embodiment)
The digital modulation / demodulation device according to the fourth embodiment includes a reception unit (not shown), a clock generator 30 (see FIG. 1), and a transmission unit 10d.
As shown in FIG. 10, the transmission unit 10d includes a transmission control circuit 11d and a modulation circuit 25d. The modulation circuit 25d includes an address generation circuit 12, a spread signal memory 13, and a multiplier 23. ing.

  When the transmission data is input, the transmission control circuit 11d collects the transmission data every 3 bits, generates an amplitude command signal from the higher 2 bits of data, and generates the address of the lowest 1 bit of data. Output to the circuit 12. The amplitude command signal is “1”, “0.5”, “−0.5”, respectively, when the upper 2 bits are “00”, “01”, “10”, “11”, respectively. , Take the four values of “−1”.

  The address generation circuit 12 outputs an address corresponding to the least significant bit value among the above three bits. Specifically, if the number of addresses in the spread signal memory 13 is M, “0” is output when the bit value is “0”, and “M / 2” is output when the bit value is “1”.

The transmission data, the value (amplitude) of the amplitude command signal corresponding to this, and the address value (start position) output from the address generation circuit 12 are summarized as follows.
―――――――――――――――――――――――
Transmission data Amplitude command signal value Start position ―――――――――――――――――――――――
000 1 0
001 1 M / 2
010 0.5 0
011 0.5 M / 2
100 -0.5 0
101 -0.5 M / 2
110 -1 0
111 -1 M / 2
―――――――――――――――――――――――

  When an address value (start position) is input from the address generation circuit 12, the spread signal memory 13 recursively reads spread signal data for one signal period, starting from the corresponding address. Then, guard interval data having a predetermined length is generated from the spread signal data, added to the guard interval data, and output to the multiplier 23.

  The multiplier 23 multiplies the amplitude value of the one-sample spread signal data input from the spread signal memory 13 and the value represented by the amplitude command signal in synchronization with the clock signal from the clock generator 30, and the switching circuit. 16 (see FIG. 1). That is, the multiplier 23 performs the same calculation as when the amplitude of the transmission signal is amplitude-modulated according to the value of the amplitude command signal.

  When the absolute value of the amplitude command signal is 1, it means that the amplitude of the transmission signal is not changed, and when it is 0.5, it is halved. Further, when the value of the amplitude command signal is a positive value, it means that the transmission signal is not inverted, and when it is a negative value, it is inverted.

  The switching circuit 16 (see FIG. 1) switches the input to the synchronization signal memory 14 (see FIG. 1) side at the start of transmission, and outputs the synchronization signal data to the DA converter 17 (see FIG. 1). Subsequently, the input is switched to the modulation circuit 25d side, and the above-described transmission signal data is sequentially output. The DA converter 17 generates a transmission signal based on the input data and sends it to the transmission path.

The receiving unit (not shown) in this embodiment includes a modified maximum value detecting circuit (not shown) instead of the maximum value detecting circuit 46, and the receiving unit 40 of the first embodiment. It is the same composition.
This maximum value detection circuit has a function of detecting the amplitude of the received signal from the correlation values Ca and Cb when the correlation is obtained in a detection step corresponding to the number of steps of the amplitude value of the amplitude command signal of the transmission unit 10d. Have. Since the correlation values Ca and Cb obtained by the receiving unit change depending on the amplitude of the received signal, data corresponding to the value of the amplitude command signal can be detected by detecting this amplitude change.

  Thus, according to the digital modulation / demodulation device of the fourth embodiment, the amplitude of the transmission signal is changed to four values in correspondence with the transmission data, so that the amount of data that can be transmitted with the transmission signal of one information frame is increased by 2 bits, The transmission speed can be increased. Further, the transmission speed can be further increased by increasing the number of steps of the amplitude value.

(Fifth embodiment)
The digital modulation / demodulation device (not shown) according to the fifth embodiment includes a transmission unit 10e, a reception unit (not shown) that can demodulate a reception signal from the transmission unit 10e, and a clock signal to the transmission unit 10e and the reception unit. A clock generator 30 (see FIG. 1) is provided.

  As shown in FIG. 11, the transmission unit 10e generates time signals generated by transmission data on both the I axis and the Q axis, combines them by the IQ modulator 28, and outputs them to the switching circuit 16 (not shown). .

  The transmission control circuit 11e collects the input transmission data every 4 bits, and divides the 4 bits into 2 bits. The transmission control circuit 11e outputs to the modulation circuit 25i using one 2-bit transmission data, and outputs to the modulation circuit 25q using the other 2-bit transmission data. This 2-bit processing is the same as that of the transmission control circuit 11 of the first embodiment. Therefore, the transmission data is transmitted for 4 bits, which is a total of 2 bits in the modulation circuit 25i and 2 bits in the modulation circuit 25q per information frame.

  The I-phase modulation data output from the modulation circuit 25 i and the Q-phase modulation data output from the modulation circuit 25 q are input to the IQ modulator 28.

  The IQ modulator 28 shifts the cosine wave signal from the local oscillator 24 that outputs a cosine wave signal cos (ωot) having a frequency that is a carrier frequency, and the cosine wave signal from the local oscillator 24 to have a sine wave signal sin (ωot) having the same frequency. , A multiplier 23i that multiplies the I-phase modulation data and the cosine wave signal cos (ωot), and a multiplier 23q that multiplies the Q-phase modulation data and the sine wave signal sin (ωot). And an adder 26e that adds the output of the multiplier 23i and the output of the multiplier 23q and outputs the result to the switching circuit 16 (not shown). Here, ω is an angular frequency, t is time, and o is a constant.

  In addition, the transmission control circuit 11e has a function of switching the switching circuit to a synchronization signal generator (not shown) that generates a synchronization signal and adding the synchronization signal prior to transmission of the transmission signal. The output from the switching circuit is sent to the transmission line. Note that a DA converter (not shown) is inserted at any point from the IQ modulator 28 to the output end to the transmission line, but the IQ modulator 28 is a DA converter (not shown). (Not shown) and analog modulation processing may be performed.

  The IQ modulator 28 adds and outputs the multiplication output of the output of the modulation circuit 25i and the cosine wave signal cos (ωot) and the multiplication output of the output of the modulation circuit 25q and the sine wave signal sin (ωot). Therefore, the output signal to the switching circuit 16 has a spectrum distributed in the center at the angular frequency ωo.

  Since the cosine wave signal cos (ωot) and the sine wave signal sin (ωot) are in an orthogonal relationship, the I-phase modulation data and the Q-phase modulation data do not cause symbol interference even though they have the same frequency. .

  A receiving unit (not shown) multiplies the received signal by a cosine wave signal sin (ωot) to generate an I-phase received signal, and multiplies the received signal by a sine wave signal sin (ωot) to generate a Q-phase received signal. Generate. Then, it is divided into an I axis and a Q axis, and correlation processing is performed in the same manner as in the first embodiment to demodulate received data.

  According to this digital modulation / demodulation device, data transmission is performed using a signal modulated and demodulated using a cosine wave signal cos (ωot) and a sine wave signal sin (ωot) having the same frequency divided into an I-phase component and a Q-phase component. Therefore, the number of bits represented by one information frame can be increased and the data transmission rate can be improved without substantially increasing the occupied frequency bandwidth.

(Sixth embodiment)
The digital modulation / demodulation device (not shown) according to the sixth embodiment of the present invention includes a transmission unit 10f, a reception unit (not shown) capable of demodulating a transmission signal from the transmission unit 10f, and a clock generator 30 (FIG. 1). Reference).

  As shown in FIG. 12, the transmission unit 10f includes a transmission control circuit 11f, m modulation circuits 25f1 to 25fm (m is a natural number of 2 or more), and m modulation circuits 25f1 to 25fm. Corresponding IQ modulators 28f1 to 28fm, a multiplexer 26f, a switching circuit 16 (see FIG. 1), and a synchronization signal generator (not shown) are provided.

  The synchronization signal generator has a function of generating a synchronization signal for providing frame synchronization. The synchronization signal is sent to the transmission line prior to the output from the multiplexer 26f when the switching circuit 16 is switched under the control of the transmission control circuit 11f.

  In addition to the function of the transmission control circuit 11 of the first embodiment, the transmission control circuit 11f has a serial-parallel conversion function of branching and outputting transmission data to each of the IQ modulators 28f1 to 28fm.

  Each of the modulation circuits 25f1 to 25fm includes the modulation circuit 25i and the modulation circuit 25q (see FIG. 11) of the fifth embodiment.

  The IQ modulators 28f1 to 28fm each have the same configuration as the IQ modulator 28 (see FIG. 11) of the fifth embodiment, but the oscillation frequencies of the local oscillator 24 (see FIG. 11) are different. That is, the IQ modulators 28f1 to 28fm perform modulation using different carrier frequencies f1, f2,.

  The multiplexer 26f synthesizes outputs from the IQ modulators 28f1 to 28fm and outputs them to the switching circuit 16 (see FIG. 1).

  As shown in FIG. 13, the carrier wave frequencies f1, f2,..., Fm of the IQ modulators 28f1, 28f2,..., 28fm are spaced apart on the frequency axis. That is, this digital modulation / demodulation device provides a frequency division multiple access (FDMA) function. Therefore, if one set of any of the modulation circuits 25f1 to 25fm and any of the corresponding IQ modulators 28f1 to 28fm outputs 2 bits of data for each information frame, 2 × m bits of data are converted. Transmission can be performed in one transmission signal period.

  According to this digital modulation / demodulation apparatus, a set of m modulation circuits 25f1 to 25fm (m is a natural number of 2 or more) and IQ modulators 28f1 to 28fm corresponding to the m modulation circuits 25f1 to 25fm, respectively. As the number increases, the number of multiplexing can be increased and the data transmission can be speeded up.

(Seventh embodiment)
The digital modulation / demodulation device according to the seventh embodiment includes a transmission unit 10g, a reception unit (not shown) that can demodulate a reception signal from the transmission unit 10g, and a clock generator that supplies a clock signal to the transmission unit 10g and the reception unit. And a container 30 (see FIG. 1).

  As shown in FIG. 14, the transmission unit 10g includes a transmission control circuit 11g, m modulation circuits 25g1, modulation circuits 25g2,..., A modulation circuit 25gm, a combiner 26g, and a switching circuit 16 (see FIG. 1). A synchronization signal data output circuit (not shown) for generating synchronization signal data for providing frame synchronization, and a DA converter 17 for DA-converting the data from the switching circuit 16 and sending it to the transmission line (See FIG. 1).

  The transmission control circuit 11g has a function of outputting the synchronization signal data from the synchronization signal data output circuit to the DA converter 17 by switching the switching circuit 16 prior to the output from the combiner 26g. Similarly to the serial-parallel conversion function for branching the transmission data into 2 × m and the transmission control circuit 11 of the first embodiment, the branched transmission data is processed two bits at a time and one bit is output. In addition, it has a function of generating a polarity signal from another one bit.

  The modulation circuit 25g1 includes an address generation circuit 12, a spread signal memory 13g1, and a multiplier 23. Each of the modulation circuits 25g2,..., 25gm has the same configuration as the modulation circuit 25g1 except that each of the modulation circuits 25g2,. That is, the modulation circuits 25g1,..., 25gm have the same configuration and function as the modulation circuit 25d (see FIG. 10) of the fifth embodiment, except that the diffusion signals stored in the spread signal memories 13g1,. The signal data is different.

  That is, this digital modulation / demodulation device includes m (m is a natural number of 2 or more) modulation circuits 25g1 to 25gm, and the plurality of modulation circuits 25g1 to 25gm use different spread signal data, thereby code division. Provides multiple access (CDMA; Code Division Multiple Access) functionality.

  The spread signal memory 13g1, spread signal memory 13g2,..., Spread signal memory 13gm have the same functions except that they store different spread signal data. The spread signal generated from these spread signal data has a sharp autocorrelation characteristic and can be cross-correlated as much as possible from the viewpoint of avoiding code interference between output data from the modulation circuits 25g1, 25g2,. Use a small one.

  The combiner 26g has a digital combining function for outputting data obtained by combining the output data from the modulation circuits 25g1,..., 25gm.

  The synthesizer 26g adds the outputs of the modulation circuits 25g2,..., 25gm and synthesizes them, and sends them to the switching circuit 16 (see FIG. 1). The switching circuit 16 switches the input to the synthesizer 26 g subsequent to the output of the synchronization signal data, and outputs the output data to the DA converter 17.

  The receiving unit includes a spread signal memory 13g1, a spread signal memory 13g2,..., A plurality of spread signal memories (not shown) for storing spread signal data stored in the spread signal memory 13gm, and a correlator. Correlation is performed on the spread signal data stored in the signal memory, and the received signal is demodulated.

  For example, if the modulation circuits 25g2,..., 25gm are configured to transmit 2 bits in one spread signal period, the transmission unit 10g can transmit 2 × m bits in one information frame.

  According to this digital modulation / demodulation device, by increasing the number of modulation circuits 25g1 to 25gm storing different spread signal data, the number of code division multiplexing increases, and the transmission rate can be improved.

According to the digital modulation / demodulation device (101, etc.) according to each embodiment of the present invention, one of the following effects can be obtained.
(1) By changing the start position of the spreading code sequence, the same spreading code sequence can be used to divide the channel with a simple configuration and improve the transmission rate.
(2) When the same spreading code sequence is used, it is not necessary to consider the cross-correlation characteristics of the spreading code. Therefore, among various code sequences including code sequences that cannot be practically used in the code division multiple access method. Thus, the code sequence to be used can be selected.
(3) Since various code sequences can be used, a code sequence that gives good flatness to the frequency spectrum of the average power can be used.
(4) Since a guard interval is provided in the transmission / reception signal, data transmission can be performed even under poor communication conditions in which the signal deteriorates due to group delay.

It is a block diagram which shows the structure of the digital modulation / demodulation apparatus of 1st Embodiment. It is a figure which shows the combination correspondence table | surface of the transmission data and the change of the polarity corresponding to this transmission data, and the change of a starting position. (A) It is a graph which shows an example of the waveform of a spread signal, and (b) is a graph which shows the autocorrelation of this spread signal. (A) The figure which shows the structure of a transmission signal typically, (b) The graph which shows an example of the waveform of the data signal in the transmission signal. (A) It is a graph which shows an example of the waveform showing the input data to a correlator, and (b) is a graph which shows the change of the output of a correlator by the input of this waveform. (A) The graph which shows another example of the waveform showing the input data to a correlator, (b) The graph which shows the change of the output of a correlator by the input of this waveform. It is a block diagram which shows the structure of the receiving part of the digital modulation / demodulation apparatus of 2nd Embodiment. It is a block diagram which shows the structure of the digital modulation / demodulation apparatus of 3rd Embodiment. It is a block diagram which shows the structure of a differential modulator. It is a block diagram which shows the partial structure of the transmission part of the digital modulation / demodulation apparatus of 4th Embodiment. It is a block diagram which shows the partial structure of the transmission part of the digital modulation / demodulation apparatus of 5th Embodiment. It is a block diagram which shows the partial structure of the transmission part of the digital modulation / demodulation apparatus of 6th Embodiment. It is a graph which shows typically the frequency spectrum of the transmission signal of the digital modulation / demodulation apparatus of 6th Embodiment. It is a block diagram which shows the partial structure of the transmission part of the digital modulation / demodulation apparatus of 7th Embodiment.

Explanation of symbols

10, 10c-10g Transmitter 11, 11d, 11e, 11g Transmission control circuit (reading start position determining means)
12 Address generation circuit (start position modulation means)
13, 13g1 to 13gm Spread signal memory 14 Sync signal memory 15 Sign inverter 16 Switching circuit 17 DA converter (DA converter)
20 Differential modulator (differential modulator)
21 XOR gate 22 delay device 23, 23i, 23q multiplier 25d, 25g1-25gm, 25i, 25q, 25f1-25fm modulation circuit 26e adder (addition means)
26f multiplexer (adding means)
26g Synthesizer 27 Phase shifter 28, 28f1 to 28fm IQ modulator (analog modulation means)
30 clock generators 40, 40b, 40c reception unit 41 reception control circuit 42 address generation circuit (spread signal data output control means)
43, 43c Spread signal memory 44 GI removal circuit 45 Sync detector 46 Maximum value detection circuit (detection circuit)
47 A-D converter (A-D converter)
48 Comparator (Sign detection means)
50a, 50b Correlator (correlator)
51a, 51b Multiplier 52a, 52b Multiplier 60 Differential demodulator 101, 103 Digital modulator / demodulator

Claims (10)

A digital modulation / demodulation device for transmitting information data using an information signal that is spread spectrum and represents information data,
Spread signal data representing a spread signal having a substantially constant power density and sharp autocorrelation characteristics within a given frequency bandwidth and having a predetermined number of samples is stored in a storage position for each sample corresponding to the time order of the spread signal. Spread signal memory,
A read start position determining means for determining a read start position in the storage position according to the information data;
The spread signal data for the predetermined number of samples are sequentially output from the spread signal memory in the order of time from the read start position, and when read from the last storage position is completed, the process returns to the first storage position and continues. Starting position modulation means for outputting and forming modulation data; and
Guard interval addition means for reading the spread signal data for a predetermined guard interval length following the start position modulation means to form guard interval data;
A modulation circuit that outputs information signal data in which the guard interval data is added to the modulation data; and
A D-A converter for generating the information signal by digital-analog conversion of the information signal data output from the modulation circuit;
A digital modulation / demodulation device comprising: Synchronization signal generating means for generating a synchronization signal for identifying the transmission timing of the information signal;
Switching means for transmitting the synchronization signal by switching to the synchronization signal generating means prior to transmission of the information signal;
The digital modulation / demodulation apparatus according to claim 1, further comprising: The modulation circuit includes:
The sign inversion means for performing inversion processing on the output of the modulation circuit according to the information data so that the polarity of the information signal is non-inverted or inverted according to the information data. The digital modem according to claim 1 or 2. The modulation circuit includes:
The digital modulation / demodulation device according to any one of claims 1 to 3, further comprising amplitude modulation means for performing amplitude modulation processing so that an amplitude of the information signal changes according to the information data. Two modulation circuits,
The DA converter is
Carrier generation means for generating two carrier waves having the same frequency and orthogonal to each other;
Analog modulation means for modulating each of the carrier waves by each modulation data output from the two modulation circuits;
Adding means for adding and outputting the outputs of the two analog modulating means;
5. The digital modulation / demodulation device according to claim 1, further comprising: A plurality of the analog modulation means each having a different frequency of the carrier;
A plurality of the modulation circuits each corresponding to the analog modulation means;
Comprising
The digital modulation / demodulation apparatus according to claim 5, wherein the adding means adds and outputs the outputs of the plurality of analog modulating means. Comprising a plurality of the modulation circuits;
The digital modulation / demodulation device according to any one of claims 1 to 4, wherein the spread signal data stored in the spread signal memory is different for each of the plurality of modulation circuits. A differential modulator that generates differential modulation data that is differentially modulated by calculating an exclusive OR of a first bit value of the information data and a second bit value preceding the first value; Equipped,
8. The digital modulation / demodulation device according to claim 1, wherein the differential modulation data is input to the modulation circuit as the information data. In a digital modulation / demodulation apparatus for transmitting information data using an information signal that is spread spectrum and represents information data,
An A / D converter for analog-to-digital conversion of the information signal to generate information signal data;
A demodulation circuit, and the demodulation circuit includes:
Guard interval adding means for removing the added guard interval and outputting modulation data from the information signal data;
A spread signal memory in which the same spread signal data as that used to generate the information signal is stored in a storage position for each sample in correspondence with the time order of the spread signal indicated by the spread signal data;
Read start position storage means for storing a plurality of read start positions in the storage position in the spread signal memory that can be taken in the information signal data;
The spread signal data for the predetermined number of samples is sequentially output from the spread signal memory in the order of time from a plurality of read start positions, and when read from the last storage position is completed, the spread data is returned to the first storage position. Spread signal data output control means for continuously outputting and performing a plurality of outputs corresponding to a plurality of read start positions,
A plurality of correlators for obtaining a correlation between a plurality of outputs from the spread signal data and the modulation data; and
A detection circuit for demodulating the information data based on an output from each of the correlators;
A digital modulation / demodulation device. A sign detection unit for detecting inversion or non-inversion of the information signal with respect to the spread signal instead of the AD converter;
The digital modulator / demodulator according to claim 9, wherein the correlator obtains a correlation based on the code detection means.

Images