JP2007133999A - Nonvolatile semiconductor memory device and memory card mounting the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device in which coupling noise is reduced further when data are read and whose reliability is high. <P>SOLUTION: When data of a memory cell adjacent to a drain side selection transistor is read, a source side selection gate is boosted after a drain side selection gate line is boosted. When data of a memory cell adjacent to a source side selection transistor is read, the drain side selection gate line is boosted after the source side selection gate line is boosted. Voltage applied to word lines of the memory cell adjacent to the drain side selection transistor or the memory cell adjacent to the source side selection transistor is different between the case where a source side selection gate is boosted after a drain side selection gate line is boosted, and the case where a drain side selection gate is boosted after a source side selection gate line is boosted. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a memory card equipped with the nonvolatile semiconductor memory device.

  In recent years, so-called nonvolatile semiconductor memory devices that hold stored data in a nonvolatile manner have become widespread among semiconductor memory devices. Some of such semiconductor memory devices have a memory cell array structure called a NAND type.

  A semiconductor memory device having a memory cell array structure called a NAND type has a plurality of memory cells connected in series with a common source / drain region, and is connected at the drain side end of the plurality of memory cells connected in series. Connected to the source-side select transistor, the source-side select transistor connected at the source-side end opposite to this end, and the source-drain region on the side not connected to the memory cell of the drain-side select transistor And a plurality of memory cell units having bit lines. Further, the semiconductor memory device includes a drain side selection gate line connected in common to the gates of the drain side selection transistors in each unit, a source side selection gate line connected in common to the gates of the source side selection transistors, The memory cell unit has a plurality of word lines connected in common to the gates of the memory cells at the same electrical connection position.

  In a semiconductor memory device having such a NAND type memory cell array structure, when data is read from a memory cell, first, the drain side select gate line is boosted by about 4V to turn on the drain side select transistor, and then the bit line is set to 1V. Apply an appropriate voltage. A read voltage is applied to a word line (hereinafter referred to as “selected word line”) connected to a memory cell from which data is read (hereinafter referred to as “selected memory cell”), while memory cells (other than the selected memory cell) ( The word line connected to the “non-selected memory cell” (hereinafter referred to as “non-selected word line”) is boosted to about 5 V and turned on, and thereafter, the voltage of the source-side selected gate line is increased. Is increased by about 4 V to turn on the transistor. Then, by detecting the resulting voltage change of the bit line, it is determined whether “0” data is stored in the selected memory cell or “1” data is stored. As a conventional technique related to such timing operation, there is a technique described in Patent Document 1 below.

JP 2005-108404 A

  An object of the present invention is to provide a highly reliable non-volatile semiconductor memory device in which coupling noise is further reduced when reading data, and a memory card equipped with the same.

  A nonvolatile semiconductor memory device according to the present invention includes a plurality of memory cells connected in series with a common source / drain region, and a drain side select transistor connected to one side of the plurality of memory cells connected in series A source side select transistor connected to a side opposite to a side to which a drain side select transistor of a plurality of memory cells connected in series is connected; a drain side select gate line connected to a gate of the drain side select transistor; A source-side selection gate line connected to the gate of the source-side selection transistor and a plurality of word lines connected to each of the plurality of memory cells connected in series; When data is read, the source side select gate line is boosted after the drain side select gate line is boosted. When the data of the memory cell adjacent to the source side select transistor is read, the source side select gate line is boosted and then the drain side select gate line is boosted, and the drain side select gate line is boosted and then the source side select gate line is boosted. In the case where the selection gate line is boosted and in the case where the drain side selection gate line is boosted after the source side selection gate line is boosted, the memory cell adjacent to the drain side selection transistor or the source side selection transistor is adjacent. The voltage applied to the word line of the memory cell is different.

  As described above, according to the present invention, it is possible to provide a highly reliable nonvolatile semiconductor memory device in which coupling noise is further reduced when reading data, and a memory card equipped with the same.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes and is not limited to the embodiments shown below. Note that in this specification, portions having the same or similar functions are denoted by the same reference numerals, and repeated description thereof is omitted.

  Here, when the timing described in Patent Document 1 is adopted and the memory cell adjacent to the source side select transistor is a selected memory cell, the word line of the memory cell is coupled with coupling noise as the source side select gate is boosted. Will receive. For example, the above timing operation is shown in FIG. In the figure, SGD is the voltage of the drain side selection gate line, WL0 is the voltage of the selected word line, WL1 to i are the voltages of the unselected word lines, SGS is the voltage of the source side selection gate line, and BL0 is the bit line. Are shown respectively. In this case, since the selected memory cell is adjacent to the source side selection gate line as shown by the dotted circle in WL0 in the figure, when the source side selection gate line is boosted, the selected word line adjacent to the source side selection gate line is selected. Will overshoot due to coupling noise. In particular, at this time (t4), since the drain side select transistor is also in the ON state, when the memory cell receives conduction noise and becomes conductive, if the read data is “1” data, a bit line discharge occurs. It is not preferable. That is, the discharge of the bit line BL is started in a state where a voltage higher than a desired voltage is applied to the selected word line WL0. As a result, the threshold voltage of the memory cell seems to be lower than the intended value. It will be. This tendency is expected to become even more prominent due to the narrowing of the interval between wirings such as word lines due to microfabrication that is expected to proceed clearly in the future.

  In addition, since such a nonvolatile semiconductor memory device has a plurality of memory cell units, there is a problem that coupling noise is received from a channel that is a current path in the read operation.

  As a result of intensive studies, the inventors have determined which of the two select transistors is boosted first in accordance with the position of the memory cell to be read in the read operation in the nonvolatile semiconductor memory device. It was determined that the coupling noise between the gate line and the word line of the selection transistor can be reduced by determining and boosting this first. Furthermore, the present inventors completed the present invention by conceiving that the coupling noise generated due to other channels can be reduced by correcting the voltage applied to the word line in accordance with the order of boosting.

(Embodiment)
FIG. 1 is a schematic block diagram of a nonvolatile memory device (hereinafter referred to as “the present nonvolatile memory device”) according to the present embodiment. The nonvolatile memory device 1 shown in FIG. 1 includes a plurality of gate lines, a plurality of word lines arranged along the plurality of gate lines, a plurality of word lines, and a plurality of gate lines arranged to cross the plurality of gate lines. Bit line, a memory cell array 2 having a plurality of memory cells, a bit line control circuit 3 for controlling the bit lines in the memory cell array 2, a word line control circuit 4 for controlling the word lines in the memory cell array 2, and a memory cell array 2, a gate control circuit 5 that controls the gate lines, a control signal generation circuit 6 that generates control signals in the word line control circuit 3, the bit line control circuit 4, the gate line control circuit 5, and the like, and the control signal generation circuit 6 has a signal input terminal 7 for inputting a signal as a basis thereof. The nonvolatile memory device 1 also includes a data input / output buffer 8 connected to the bit line control circuit 3 and a data input / output terminal 9 connected to the data input / output buffer 8.

  Here, FIG. 2 shows a configuration of the memory cell array 2. The memory cell array 2 shown in FIG. 2 is configured by arranging a plurality of memory cell units MU0, MU1,... MUj in parallel, and each memory cell unit is arranged in series with a common source / drain region. A plurality of memory cells MC0, MC1,..., MCi, a source side select transistor S1 connected to one end (source region side) of these connections, and a drain side select transistor connected to the other end (drain region side) S2. Note that the gates of the memory cells MC0, MC1,..., MCi are floating gates, and these memory cells are connected to the floating gate and word of the memory cells in the same electrical connection position in other memory cell units. They are connected in common via lines (WL0, WL1,..., WLi). Further, the gate of the source side select transistor S1 in each memory cell unit is connected to the source side select gate line SGS common to the memory cell array. Similarly, the gate of the drain side select transistor S2 is also connected to the drain common to the memory cell array. It is connected to the side selection gate line SGD. The drain region of the drain side select transistor S2 in each memory block is connected to bit lines BL0, BL1,..., BLi provided corresponding to each memory block, and the source side select transistor S1 in each memory block. The source region is commonly connected to a cell source line CELSRC common to the memory cell array 2.

  Here, FIG. 3 shows a partial cross-sectional view of the nonvolatile semiconductor memory device. FIG. 3 is a diagram in the case where one memory cell unit is cut by a cross section passing through both the source side select transistor and the drain side select transistor. As described above, the nonvolatile semiconductor memory device is arranged in correspondence with the substrate and the plurality of memory cells, the drain side selection transistor, the source side selection transistor, and the floating gates of the plurality of memory cells arranged on the substrate. A word line, a bit line connected to the drain region of the drain side select transistor, and a cell source line connected to the source region of the source side select transistor. In FIG. 3, the substrate, the floating gate, the word line, A cross section of a bit line or the like is shown. In these configurations, it is necessary to secure capacitance between the floating gate and the word line and between the substrate and the floating gate, respectively. On the other hand, the distance between the gate wiring and the word line is reduced due to the need for wiring miniaturization. It is also necessary to reduce the width, and there is a risk of causing coupling noise between the gate line and the word line. In the nonvolatile semiconductor device, a source-side selection transistor shunt line (SGS shunt line) connected to the source-side selection transistor, and a drain-side selection transistor shunt line (SGD) connected to the drain-side selection transistor. In addition, since these are arranged on a plurality of word lines, there is a possibility that coupling noise may occur. More specifically, the SGD shunt line is connected to the drain side select gate line in the same memory block, and the SGS shunt line is connected to the source side select gate line in the adjacent memory block. Is charged after the source side selection gate line, if the selected memory cell is under the SGD shunt line, there is a risk of receiving coupling noise from the SGD shunt line. Therefore, this nonvolatile semiconductor memory device employs a read operation that reduces the following coupling noise.

  Hereinafter, a data read operation of the nonvolatile semiconductor memory device will be described. FIG. 4 shows a timing chart when reading the memory cell MC0 adjacent to the source side select transistor in the memory cell unit MUj in FIG. In the nonvolatile semiconductor memory device, first, at time t1, the voltage Vsg is applied to the source side selection gate line. Next, at time t2, the voltage Vbl is applied to the bit line BL0. At time t3, the word line WL0 connected to the memory cell MC0 to be read (the memory cell to be read is hereinafter referred to as “selected memory cell”, and the word line connected to this is referred to as “selected word line”), and Word lines WL2 to WLi connected to memory cells MC1 to MCi other than the selected memory cell MC0 (memory cells other than the selected memory cell are hereinafter referred to as “non-selected memory cells”, and word lines connected to these are referred to as “non-selected word lines”. The voltage is applied to. A voltage Vread is applied to the non-selected word line, and a predetermined voltage (hereinafter referred to as “selection voltage”) to be described later is applied to the selected word line. Thereafter, at time t4, the voltage Vsg is applied to the drain side select gate line SGD, and the gate of the drain side select transistor is turned ON. That is, by such an operation, the drain-side selection transistor, the source-side selection transistor, and the gate of the non-selected memory cell are turned on, and “0” data is stored in the selected memory cell or “1” data is stored. The voltage change of the voltage of the bit line occurs depending on whether it is stored, and data can be read by determining the change of the voltage on the bit line BL0 at time t4.

  On the other hand, when the nonvolatile semiconductor memory device reads the memory cell MCi adjacent to the drain side selection transistor in the memory cell unit MUj (in this case, the selected memory cell becomes MCi and the selected word line becomes WLi), the above differs. The order in which voltages are applied to the source side select gate line and the drain side select gate line is reversed. FIG. 5 shows this timing chart. In this case, first, at time t1, the voltage Vsg is applied to the drain side select gate line SGD. Next, at time t2, the voltage Vbl is applied to the bit line BL0. At time t3, a voltage is applied to the selected word line WLi and the unselected word lines WL0 to WLi-1. In this case as well, the voltage Vread is applied to the unselected word lines, and a predetermined voltage described later is applied to the selected word lines. Thereafter, at time t4, the voltage Vsg is applied to the source side selection gate line, and the gate of the drain side selection transistor is turned ON. In this way, the semiconductor memory device determines a change in voltage on the bit line BL0 at time t4.

  With the above operation, the nonvolatile memory device can reduce the coupling noise when the selected memory cell is adjacent to the drain side selection gate line or the source side selection gate line. Specifically, when the selected memory cell is adjacent to the selection gate line in advance, even if the word line corresponding to the selected memory cell is boosted by boosting the selection gate line, the word line from the selection gate line is increased. Occurrence of coupling noise can be suppressed, and a read operation can be performed accurately. In order to make the effects of the timing operation easier to understand, timing charts in the case where coupling noise from a channel described later is not considered are shown in FIGS. FIG. 6 shows an example when the selected memory cell is adjacent to the source side selection transistor (selected word line is WL0), and FIG. 7 shows the case where the selected memory cell is adjacent to the drain side selection transistor (selected word line is WLi). In each of the timing charts shown in FIGS. 6 and 7, the voltage applied to the selected word line is the same as Vcgrv.

  Note that the selection voltage Vcg applied to the selected memory cell in this nonvolatile memory device is selected when the gate line of the source side selection transistor is boosted first as shown in FIG. 4 and when the drain side selection is performed as shown in FIG. One of the features is that the value of the applied voltage differs depending on the case where the gate line of the transistor is boosted first. More specifically, when the memory cell adjacent to the drain side select transistor is a selected memory cell, the drain side select gate line is boosted first at time t3, but the Vcg is boosted first with respect to the source side select gate line. (Vcg = Vcgrv−ΔV) (when the memory cell adjacent to the source-side selection transistor is used as the selection memory, Vcg = Vcgrv remains). This is for reducing coupling noise from the channel caused by reading other than BLi, and such coupling noise has a waveform as shown at time t4 in FIG. If the voltage of the selected word line WL0 remains the selected voltage Vcgrv (see, for example, FIG. 8), the voltage Vbl precharged to the bit line is charged to the channel, and the selected word line WL0 is coupled with the coupling noise. This overshoots the potential. In particular, at the time of verify reading, the threshold voltage of the memory cell appears to be low, so that the threshold voltage distribution spreads to the higher side. For this reason, by reducing the voltage Vcgrv by ΔV in advance, it is possible to make it lower than the threshold voltage even in the case of overshoot. Thereby, it can suppress that threshold distribution spreads to the higher one. This is particularly effective for a multi-level NAND nonvolatile semiconductor memory device that requires a narrower threshold voltage control. Here, ΔV may be constant at all times. However, it is more preferable to make ΔV variable in that the optimum selection voltage can be corrected with respect to coupling noise received from the channel for each reading operation. It is. Here, the unit for making ΔV variable may be different for each read operation, may be a unit of a memory cell unit, or is electrically connected to each selected memory cell (for each position of the word line). There may be a combination thereof. Here, the value of ΔV can be appropriately adjusted depending on the configuration of the non-volatile semiconductor device and is not limited to the following, but ΔV is larger than Vcgrv, specifically, more preferably larger than 0V and not larger than 2V. More preferably, it is more than 0V and 1V or less. On the other hand, when the gate line of the drain side selection transistor is boosted first as shown in FIG. 5, since this noise acts to lower the pressure, the selection voltage Vcgrv is less likely to overshoot, so the voltage is applied as it is. be able to. That is, when boosting the gate line of the source side select transistor before the gate line of the drain side select transistor, it is desirable to lower the voltage applied to the selected word line, specifically to set it lower by ΔV. . From another viewpoint, the voltage applied to the selected word line when the drain side select gate line is boosted first is the voltage applied to the selected word line when the source side select gate line is boosted first. Higher than that. By doing so, the nonvolatile semiconductor memory device according to the present embodiment reduces the coupling noise when the selected memory cell is adjacent to the selection transistor, and the coupling noise generated from other channels in the word line. Therefore, a more reliable nonvolatile semiconductor device can be provided. In addition, in order to make the configuration of the nonvolatile semiconductor device according to the present embodiment easier to understand, timing diagrams excluding the coupling between the selected word line and the gate line and the coupling from the channel described above are shown in FIGS. Show. 9 shows the case where the selected memory cell is adjacent to the source side selection transistor (selected word line is WL0), and FIG. 10 shows the case where the selected memory cell is a drain side transistor (selected word line is WLi).

  In the above example, the case where the selected memory cell is adjacent to the drain side selection transistor and the case where the selected memory cell is adjacent to the source side selection transistor is shown. If they are not adjacent to each other, the coupling noise generated between the selection gate line and the word line is reduced, so that any transistor may be selected first. However, in order to further reduce the coupling noise generated from other channels in the word line, for example, when the word line is closer to the source side select transistor, the voltage of the source side select gate line is boosted first, and the drain side transistor In the case of near, it is more desirable to perform the operation of boosting the voltage of the drain side select gate line first. More specifically, when K selected memory cells are connected in series, the source side selection is selected in the case of the first to Nth memory cells connected in series from the side closer to the source side selection transistor. It is desirable that the voltage of the gate line is boosted first, and in the case of N + 1th to Kth, the voltage of the drain side select gate line is boosted first. Here, K is an integer of 2 or more, and N is an integer of 0 or more smaller than K. Further, in this case, in the cross-sectional structure of the nonvolatile semiconductor memory device under the condition of integer N, the shunt line of the drain side select gate line from the N + 1th memory cell to the Kth memory cell from the side close to the source side select transistor. It is more desirable to be under. In this way, when the selected memory cell is below the shunt line of the drain side select gate line, the drain side select gate line is boosted first, otherwise the source side select gate line is boosted first. In addition to the case where the selected memory cells are adjacent to each other, it is possible to further reduce the coupling noise resulting from the boosting of the shunt line connected to the gate line.

  In addition, the nonvolatile semiconductor memory device according to this embodiment can be mounted on a memory card. In this case, it can be realized by providing a peripheral circuit such as a controller for controlling the nonvolatile semiconductor memory device, a pad portion, and the like.

  As described above, the present invention is industrially applicable as a nonvolatile semiconductor memory device.

FIG. 3 is a diagram showing functional blocks of the nonvolatile semiconductor memory device according to the embodiment. 1 is a diagram showing a configuration of a memory cell array of a nonvolatile semiconductor memory device in an embodiment. 1 is a partial cross-sectional view of a nonvolatile semiconductor memory device according to an embodiment. FIG. 4 is a view showing a timing chart in a read operation of the nonvolatile semiconductor memory device in the embodiment. FIG. 4 is a view showing a timing chart in a read operation of the nonvolatile semiconductor memory device in the embodiment. FIG. 4 is a timing chart when the coupling noise from the channel is not considered in the read operation of the nonvolatile semiconductor memory device in the embodiment. FIG. 4 is a timing chart when the coupling noise from the channel is not considered in the read operation of the nonvolatile semiconductor memory device in the embodiment. FIG. 10 is a timing chart when the voltage of a selected word line WL0 is kept at a selection voltage Vcgrv in a read operation of the nonvolatile semiconductor memory device according to the present embodiment. 6 is a diagram illustrating a timing chart in a case where coupling between a selected word line and a gate line and coupling from a channel are excluded in a read operation of the nonvolatile semiconductor memory device in the embodiment. FIG. 6 is a diagram illustrating a timing chart in a case where coupling between a selected word line and a gate line and coupling from a channel are excluded in a read operation of the nonvolatile semiconductor memory device in the embodiment. FIG. The figure which shows the timing chart in case coupling noise arises in the conventional non-volatile semiconductor memory device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Nonvolatile memory device, 2 ... Memory cell array, 3 ... Word line control circuit, 4 ... Bit line control circuit, 5 ... Gate line control circuit, 6 ... Control voltage generation circuit, 7 ... Signal input terminal, 8 ... Data input Output buffer, 9: Data input / output terminal, MC0-i: Memory cell, S1: Source side select transistor, S2: Drain side select transistor, WL0-i: Word line, SGD ... Drain side select gate line, SGS ... Source side Selection gate line, MB0 to j ... memory cell unit, BL0 to j ... bit line

Claims (5)

A plurality of memory cells connected in series with a common source / drain region;
A drain side select transistor connected to one side of the plurality of memory cells connected in series;
A source side select transistor connected to a side opposite to a side to which the drain side select transistor of the plurality of memory cells connected in series is connected;
A drain side select gate line connected to the gate of the drain side select transistor;
A source side select gate line connected to the gate of the source side select transistor;
A non-volatile semiconductor memory device having a plurality of word lines connected to each of the plurality of memory cells connected in series,
When data of a memory cell adjacent to the drain side select transistor is read, the source side select gate line is boosted after the drain side select gate line is boosted,
When data of a memory cell adjacent to the source side select transistor is read, the source side select gate line is boosted and then the drain side select gate line is boosted.
In the case where the source side selection gate line is boosted after the drain side selection gate line is boosted and in the case where the drain side selection gate line is boosted after the source side selection gate line is boosted, A nonvolatile semiconductor memory device, wherein voltages applied to a memory cell adjacent to a drain side select transistor or a word line of a memory cell adjacent to the source side select transistor are different.   When the source side select gate line is boosted after the drain side select gate line is boosted, the voltage applied to the word line of the memory cell adjacent to the source side select transistor is determined by the source side select gate line. 2. The nonvolatile semiconductor device according to claim 1, wherein when the drain side select gate line is boosted after being boosted, the voltage is higher than a voltage applied to a word line of a memory cell adjacent to the source side select transistor. Storage device.   Between the case where the source side selection gate line is boosted after the drain side selection gate line is boosted and the case where the drain side selection gate line is boosted after the source side selection gate line is boosted. 2. The nonvolatile semiconductor device according to claim 1, wherein a difference in voltage applied to a word line of a memory cell adjacent to the drain side select transistor or a memory cell adjacent to the source side select transistor is variable. Storage device. A plurality of memory cells connected in series with a common source / drain region;
A drain side select transistor connected to one side of the plurality of memory cells connected in series;
A source side select transistor connected to a side opposite to a side to which the drain side select transistor of the plurality of memory cells connected in series is connected;
A drain side select gate line connected to the gate of the drain side select transistor;
A source side select gate line connected to the gate of the source side select transistor;
A non-volatile semiconductor memory device having a plurality of word lines connected to each of K (K is an integer of 2 or more) memory cells connected in series,
In the case of the first to Nth (N is an integer of 0 or more smaller than K) from the side close to the source side selection transistor among the selected memory cells, the voltage of the source side selection gate line is first boosted, and N + 1 In the second to Kth cases, the voltage on the drain side select gate line is boosted first,
In the case where the source side selection gate line is boosted after the drain side selection gate line is boosted and in the case where the drain side selection gate line is boosted after the source side selection gate line is boosted, A nonvolatile semiconductor memory device, wherein voltages applied to a memory cell adjacent to a drain side select transistor or a word line of a memory cell adjacent to the source side select transistor are different. A plurality of memory cells connected in series with a common source / drain region, a drain side select transistor connected to one side of the plurality of memory cells connected in series, and the plurality of memories connected in series A source-side selection transistor connected to the opposite side of the cell to the side to which the drain-side selection transistor is connected, a drain-side selection gate line connected to the gate of the drain-side selection transistor, and a gate of the source-side selection transistor A non-volatile semiconductor memory device having a source-side selection gate line connected to a plurality of word lines connected to each of the plurality of memory cells connected in series,
When data of a memory cell adjacent to the drain side select transistor is read, the source side select gate line is boosted after the drain side select gate line is boosted,
When data of a memory cell adjacent to the source side select transistor is read, the source side select gate line is boosted and then the drain side select gate line is boosted.
In the case where the source side selection gate line is boosted after the drain side selection gate line is boosted and in the case where the drain side selection gate line is boosted after the source side selection gate line is boosted, A method of operating a nonvolatile semiconductor memory device, wherein a voltage applied to a memory cell adjacent to a drain side select transistor or a word line of a memory cell adjacent to the source side select transistor is made different.

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