JP2007129040A - Semiconductor device comprising dram and non-volatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem in the prior art wherein material quality/thickness of the insulting film between a control gate and a floating gate in a non-volatile memory are set to the optimum material/thickness can not be made optimum for non-volatile memory, without increasing the manufacturing steps, at the loading both DRAM and non-volatile memory (for example, flash memory) on the same semiconductor substrate. <P>SOLUTION: A wire is made to function as a control gate, and a contact and a gate electrode, connected to this contact, are made to function as a floating gate. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a DRAM and a nonvolatile memory are mixedly mounted on the same semiconductor chip.

  2. Description of the Related Art In recent years, a technology for mounting a logic element and a memory element on the same semiconductor chip has been developed in response to demands for higher functionality and miniaturization of semiconductor devices. As memory elements, DRAM, SRAM, and various nonvolatile memories are known. A technique for mounting a logic element and a DRAM together is disclosed in Patent Document 1, for example.

  In addition to logic elements and DRAM elements, non-volatile memory is embedded on the same semiconductor chip in order to store firmware for external devices and to save data during computation when the power of the semiconductor device is turned off. Technology to do is expected.

  Here, Patent Document 2 and Patent Document 3 disclose a technique for mounting a DRAM and a nonvolatile memory together.

JP 2001-127270 A JP 2001-257323 A (FIG. 5 (j), FIG. 6) Japanese Patent Laying-Open No. 2003-158242 (FIG. 1)

  The present inventors have found that the above-described conventional technology has the following problems.

  In the semiconductor device disclosed in Patent Document 2, it is necessary to form a polysilicon film that functions as a control gate of a flash memory. This polysilicon film is not required for transistors other than the memory cell transistor of the flash memory (for example, a transistor constituting a logic circuit). Therefore, the process of forming this polysilicon film increases the number of processes. The increase in the number of processes is a problem because it causes an increase in manufacturing cost and a decrease in yield.

  In the semiconductor device disclosed in Patent Document 3, a capacitance insulating film for a DRAM capacitor and an insulating film that insulates the control gate and floating gate of the EEPROM (hereinafter, the control gate and floating gate of the nonvolatile memory are insulated from each other). The insulating film is called a CG-FG insulating film) at the same time. By forming the capacitor insulating film and the CG-FG insulating film at the same time, an increase in the number of processes is prevented. However, since the capacitor insulating film and the CG-FG insulating film are formed at the same time, the material and film thickness of both insulating films are the same.

  Generally, since DRAM performs refreshing, even if the charge accumulated in the capacitor leaks somewhat through the capacitor insulating film, it is allowed. However, it is desirable to store as much charge as possible in the capacitor in order to reliably read out the stored bit. That is, the capacitance insulating film of the DRAM is required to increase the capacitance of the capacitance as much as possible even if there is some leakage.

  On the other hand, the nonvolatile memory needs to hold the charge stored in the floating gate for as long as possible. That is, the CG-FG insulating film is required to have as little leakage as possible.

  However, in the technique of Patent Document 3, since the material and the film thickness of the capacitor insulating film and the CG-FG insulating film are the same as described above, if the capacitor insulating film is made of an optimal material and film thickness, CG-FG The requirements for the inter-layer insulating film cannot be satisfied. The reverse is also true.

  One feature of the present invention is that a wiring is used for the control gate and a contact is used for a part of the floating gate. Furthermore, another feature is that the CG-FG insulating film is formed in a layer different from the capacitor insulating film.

  A wiring as a control gate and a contact as a floating gate can be formed simultaneously with other wirings and contacts. Therefore, the number of manufacturing processes does not increase.

  Furthermore, since the CG-FG insulating film is formed in a layer different from the capacitor insulating film, an optimum material and film thickness can be selected for each insulating film. As a result, the capacitance of the DRAM can be increased to the maximum, and the charge accumulated in the floating gate of the nonvolatile memory can be prevented from leaking through the CG-FG insulating film as much as possible.

  For example, the present invention is a semiconductor device in which a DRAM and a nonvolatile memory are mixedly mounted on the same semiconductor substrate, and the DRAM includes a bit line and a capacitor having a capacitor insulating film, and the nonvolatile memory The memory includes a transistor, a contact electrically connected to the gate electrode of the transistor, a wiring, and an insulating film that is formed in a layer different from the capacitor insulating film and insulates the wiring and the contact from each other. In the semiconductor device, the wiring functions as a control gate, and the contact and the gate electrode function as a floating gate.

  According to the present invention, it is possible to obtain a semiconductor device in which a DRAM and a non-volatile memory are mixedly mounted without increasing the number of manufacturing steps and exhibiting the performance required for each of the DRAM and the non-volatile memory.

  A schematic plan view of a semiconductor device 100 of the present invention is shown in FIG. The semiconductor device 100 includes a semiconductor substrate 1, a DRAM unit 101, a nonvolatile memory unit 102, and a logic operation unit 103 mounted on the same semiconductor substrate 1. Further, an I / O unit 104 for performing signal communication (SC1) between the semiconductor device 100 and an external device is provided on the same semiconductor substrate 1. Further, a BIST (Built-In Self Test) circuit 105 is also provided on the same semiconductor substrate 1.

The DRAM unit 101 includes a memory cell array 101a and peripheral circuits. The peripheral circuit further includes an X decoder 101b, a Y decoder 101c, a sense amplifier 101d, and the like. In addition, the DRAM unit 101 is provided with redundant bits to be provided in the case where a defective bit exists.
The nonvolatile memory unit 102 includes a memory cell array 102a and peripheral circuits. The peripheral circuit further includes an X decoder 102b, a Y decoder 102c, a sense amplifier 102d, and the like.

  The DRAM unit 101 and the logic operation unit 103 exchange data (SC2). That is, the result calculated by the logic operation unit 103 is transferred to the DRAM unit 101 for storage, or the data stored in the DRAM unit 101 is input to the logic operation unit 103 for operation.

  The nonvolatile memory unit 102 stores programs and data in advance. The logic operation unit 103 reads the stored program from the nonvolatile memory unit 102 (SC3) and executes it. Or the logic operation part 103 reads the data memorize | stored in the non-volatile memory 102, calculates this data, or performs various processes based on this data.

  The BIST circuit 105 checks whether or not there is a defective bit in the DRAM unit 101 when the power of the semiconductor device 100 is turned on. Information on defective bits detected by the BIST circuit 105 is written in the nonvolatile memory unit 102. When accessing the DRAM unit 101, redundant bits are selected as necessary based on information on defective bits stored in the nonvolatile memory unit 102.

  As a result, if defective bits in the DRAM unit 101 are inspected at the time of shipment of the semiconductor device 100 and can be replaced with redundant bits, replacement with physical redundant bits by cutting a fuse or the like is necessary. It becomes possible to eliminate the inspection process at the time of shipment.

  If the inspection of defective bits by the BIST circuit 105 and the writing of defective bit information to the nonvolatile memory unit 102 are performed each time the semiconductor device 100 is powered on, even if a defective bit occurs due to deterioration over time, Replacement with redundant bits can be performed reliably.

  The I / O unit 104 exchanges data with the DRAM 101 unit and the nonvolatile memory unit 102 (SC4), and also exchanges data with the logic unit 103 (SC5).

  A method for manufacturing the semiconductor device 100 according to the first embodiment of the present invention will be described with reference to FIGS. 2 to 5 show only one DRAM memory cell and one nonvolatile memory cell, and other parts such as the logic operation unit 103 and peripheral circuits are omitted.

  With reference to FIG. 2, a transistor Tr <b> 1 for the DRAM unit 101 and a transistor Tr <b> 2 for the nonvolatile memory unit 102 are formed on the same semiconductor substrate 1. The transistors Tr1 and Tr2 are formed in the same process. This is because the structure of the transistor Tr2 in the nonvolatile memory unit 102 is not special, and is the same structure as the transistor Tr1 in the DRAM unit 101.

  Since the transistors Tr1 and Tr2 have the same structure as the logic operation unit 103 and other parts of the transistor (not shown), all the transistors on the semiconductor substrate 1 are formed in the same process. Can do. Therefore, when the nonvolatile memory unit 102 is mixedly mounted on the same semiconductor substrate in addition to the DRAM unit 101 and the logic operation unit 103, the number of processes is not increased.

  Each of the transistors Tr1 and Tr2 has source / drain regions SD1 and SD2, gate insulating films GI1 and GI2, gate electrodes GE1 and GE2, and sidewalls SW1 and SW2. Silicide layers SL1 and SL2 are formed on the surfaces of the source / drain regions SD1 and SD2 and the gate electrodes GE1 and GE2. The silicide layers SL1 and SL2 are cobalt silicide or nickel silicide. The transistors Tr1 and Tr2 are separated from adjacent circuits by an element isolation region such as STI (Shallow Trench Isolation).

  Next, referring to FIG. 3, an interlayer insulating film 20 is formed on the semiconductor substrate 1 so as to cover the transistors Tr1 and Tr2. Then, contacts 310, 311, 320 and 321 are formed in the interlayer insulating film 20.

  The contacts 310, 311, 320, and 321 are formed of a metal such as tungsten (W). The contacts 310 and 311 are connected to the source / drain region SD1 of the transistor Tr1 of the DRAM section 101. The contact 320 is connected to the gate electrode GE2 of the transistor Tr2 of the nonvolatile memory unit 102. The contact 321 is connected to the source / drain region SD2 of the transistor Tr2 of the nonvolatile memory unit 102.

  Next, an insulating layer 21 is formed on the interlayer insulating film 20. The insulating layer 21 is formed of an oxide film or a nitride film. Then, a bit contact BC is formed in the insulating layer 21 of the DRAM unit 101.

  Next, wirings 40 and 41 are formed on the insulating film 21. The wirings 40 and 41 are formed according to the following procedure. First, a stacked film 50 of a TiN film and a W film is formed on the insulating film 21. Next, a laminated film 51 of a silicon oxide film and a silicon nitride film is formed. Next, the laminated films 50 and 51 are patterned into a wiring shape by a photolithography technique. Further, a silicon nitride film is formed, and this silicon nitride film is etched back to form sidewalls 52. The wirings 40 and 41 are obtained by the above process.

  The wiring 40 functions as a bit line of the DRAM cell. Bit line 40 is formed on contact 310. The bit line 40 and the contact 310 are electrically connected via the bit contact BC. Therefore, the bit line 40 is electrically connected to the source / drain region SD1 through the bit contact BC and the contact 310.

  On the other hand, the wiring 41 is formed on the contact 320. No bit contact is formed between the wiring 41 and the contact 320. That is, the insulating layer 21 electrically insulates the wiring 41 and the contact 320.

  Finally, the wiring 41 functions as a control gate of the nonvolatile memory, and the contact 320 and the gate electrode GE2 function as a floating gate. The insulating layer 21 becomes a CG-FG insulating film. Since the insulating film 21 is formed independently of a later-described capacitive insulating film, it is possible to make the material and film thickness optimal for the CG-FG insulating film.

  The bit line 40 and the wiring 41 functioning as a control gate are formed simultaneously. Therefore, an additional process for forming the control gate is not required, and the number of processes is not increased. Further, the insulating film 21 is not a film dedicated to the CG-FG insulating film but also serves as a film for forming a bit contact therein. Therefore, an additional process for providing the CG-FG insulating film is not required, and the number of processes is not increased.

  Next, referring to FIG. 4, interlayer insulating film 22 is formed on insulating film 21 so as to cover bit line 40 and wiring 41. Then, contacts 312 and 322 are formed in the interlayer insulating film 22 so as to be connected to the contacts 311 and 321, respectively. The contacts 312 and 322 are formed of a metal such as tungsten (W).

Next, referring to FIG. 5, an insulating layer 23 and an interlayer insulating film 24 are formed on the interlayer insulating film 22. In the DRAM portion 101, the capacitor 6 is formed in the interlayer insulating film 24. The capacitor 6 includes a lower electrode 60, a capacitor insulating film 61, and an upper electrode 62. The lower electrode 60 is made of a metal such as titanium nitride (TiN). The interlayer insulating film 61 is selected from materials such as ZrO ₂ , TaO ₅ , and HfO ₂ . The upper electrode 62 is made of a metal such as tungsten (W).

  In the present embodiment, the capacitor insulating film 61 is formed independently of the insulating film 21 that is the CG-FG insulating film of the nonvolatile memory. Therefore, it is possible to make the material and film thickness optimal for the capacitor insulating film 61 of the DRAM capacitor.

  Next, an interlayer insulating film 25 is formed on the interlayer insulating film 24, contacts 323 and wirings 42 are formed, and the semiconductor device 100 is obtained.

  The semiconductor device 100 according to the present embodiment performs nonvolatile storage by injecting charges into the floating gate formed of the contact 320 and the gate electrode GE2. For example, charge is injected from the channel of the transistor Tr2 into the floating gate through the gate insulating film GI2. Alternatively, charge may be injected from the wiring 41 to the floating gate via the CG-FG insulating film 21. That is, the wiring 41 may function as a programming gate.

  Another example of the first embodiment is shown in FIG. In the semiconductor device 100 of this embodiment, no bit contact is provided between the bit line 40 and the contact 310. The wiring 41 serving as the control gate and the contact 320 serving as the floating gate are insulated by the stopper film 26 between the interlayer insulating film 20 and the interlayer insulating film 22. That is, the stopper film 26 also serves as a CG-FG insulating film.

  A method for manufacturing the semiconductor device 100 according to the second embodiment of the present invention will be described with reference to FIGS.

  The semiconductor device 100 of the present embodiment is manufactured in the same process as that of the first embodiment until the formation of the insulating film 21 and the bit contact BC.

  Next, referring to FIG. 7, wirings 40 and 41 are formed on the insulating film 21. Here, the present embodiment is different from the first embodiment in that the wiring 41 of the nonvolatile memory unit 102 is formed at a position slightly shifted to the side rather than immediately above the contact 320.

  Next, referring to FIG. 8, an interlayer insulating film 22 is formed on the insulating film 21 so as to cover the wirings 40 and 41. Then, contacts 312, 322 and 324 are formed in the interlayer insulating film 22. Contacts 312, 322, and 324 are connected to contacts 311, 321, and 320, respectively. The contact 324 is in contact with the sidewall 52 formed on the side surface of the wiring 41. That is, the sidewall 52 insulates the wiring 41 and the contact 324 from each other.

  Finally, the wiring 41 functions as a control gate of the nonvolatile memory, and the contacts 320 and 324 and the gate electrode GE2 function as a floating gate. The sidewall 52 becomes a CG-FG insulating film.

  As shown in FIG. 8, sidewalls 52 are also formed on the side surfaces of the bit lines 40 of the DRAM unit 101. This is provided in order to reliably insulate the bit line 40 from the surrounding contacts. That is, the sidewall 52 formed on the side surface of the wiring 41 of the nonvolatile memory unit 102 is formed simultaneously with the sidewall 52 of the bit line 40. Therefore, an additional step for forming the CG-FG insulating film is not necessary. Therefore, the number of manufacturing processes does not increase.

  In the present invention, the sidewall 52 is formed independently of the capacitive insulating film of the DRAM. Therefore, the sidewall can be made of an optimum material and film thickness for the CG-FG insulating film. In addition, this embodiment has an advantage that the thickness of the CG-FG insulating film can be controlled by the position of the contact 324. In other words, when it is desired to reduce the thickness of the CG-FG insulating film, the position of the contact 324 may be brought closer to the wiring 41.

  Next, referring to FIG. 9, the insulating film 23, the interlayer insulating film 24, the capacitor 6, the interlayer insulating film 25, the contact 323, and the wiring 42 are formed, and the semiconductor device according to this embodiment is formed. 100 can be obtained.

It is a figure for demonstrating the semiconductor device of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure for demonstrating the other Example of the semiconductor device concerning the 1st Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device concerning the 2nd Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device concerning the 2nd Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device concerning the 2nd Embodiment of this invention.

Explanation of symbols

1 Semiconductor substrate 20, 22, 24, 25 Interlayer insulating film 21, 23 Insulating film 310, 311, 312, 320, 321, 322, 323, 324 Contact 40 Bit line 41 Wiring 50, 51, 52 Side wall 6 DRAM capacitor Tr1 , Tr2 transistor

Claims (10)

A semiconductor device in which a DRAM and a nonvolatile memory are mixedly mounted on the same semiconductor substrate,
The DRAM is
Bit lines,
A capacitor having a capacitive insulating film;
Have
The nonvolatile memory is
A transistor,
Wiring and
A contact electrically connected to the gate electrode of the transistor;
An insulating film that insulates the wiring and the contact from each other;
Have
The wiring functions as a control gate, and the contact and the gate electrode function as a floating gate;
A semiconductor device characterized by the above. The semiconductor device according to claim 1, wherein the insulating film is a sidewall that covers a side surface of the wiring. 3. The semiconductor device according to claim 2, further comprising a multilayer wiring structure having a plurality of levels of wiring layers, wherein the bit line and the wiring are formed in the same level wiring layer. . The DRAM is
A lower electrode constituting the capacitor;
A capacitive contact electrically connected to the lower electrode;
Have
The contact and the capacitor contact are formed in the same level wiring layer;
The semiconductor device according to claim 3. The semiconductor device according to claim 1, wherein the insulating film is sandwiched between a bottom surface of the wiring and an upper surface of the contact. The contact is formed in the first interlayer insulating film;
The wiring is formed in the second insulating film;
The first interlayer insulating film and the second interlayer insulating film are adjacent to each other via the insulating film;
The semiconductor device according to claim 5. 7. A multilayer wiring structure having a plurality of levels of wiring layers, wherein the bit line and the wiring are formed in a wiring layer at the same level. The semiconductor device described. A BIST circuit for detecting a failure of the DRAM;
The non-volatile memory stores information on defects detected by the BIST;
The semiconductor device according to claim 1, wherein: 9. The power supply to the semiconductor device, the BIST circuit detects a failure of the DRAM, and the nonvolatile memory stores information on the failure detected by the BIST circuit. A semiconductor device according to 1. The semiconductor device according to claim 1, wherein the insulating film is formed in a layer different from the capacitor insulating film.

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