JP2007123869A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reliable semiconductor device having the function of replacing a defective bit with a redundancy bit and particularly having high resistance to electrification by cutting a fuse material, and to provide a method of manufacturing the same. <P>SOLUTION: In the semiconductor device of the present invention, an antenna part which includes at least an exposed part and is formed of a top wiring layer stacked on a fuse layer formation area is provided in a fuse window formed by removing a protective layer stacked on the fuse layer formation area so as to cut particularly the fuse material, so that a retraction path is formed for charged particles adhering to a surface of the semiconductor device when the semiconductor device is electrically charged. Thus it is possible to prevent the device from being broken by electrical charge conventionally generated by charged particles entering from a fuse cutting part. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a function of replacing a defective bit with a redundant bit by cutting the fuse material, and in particular, the protective layer stacked on the upper part of the fuse layer forming region is removed so that the fuse material can be cut. The present invention relates to a semiconductor device having a conductive antenna portion that is formed by an uppermost wiring layer that is at least partially exposed in a formed fuse window portion and is stacked on top of a fuse layer formation region, and a manufacturing method thereof.

As an example of a conventional semiconductor device having a fuse, a DRAM (dynamic random access memory) will be described below with reference to the drawings.
FIG. 1 shows an upper schematic configuration (plan view) of a fuse region in a conventional semiconductor device having a function of replacing defective bits with redundant bits by cutting the fuse material. As shown in FIG. 1, in the conventional semiconductor device, a portion corresponding to an upper region of the fuse material 10 in a protective film stacked on the fuse material 10 in order to ensure a cutting margin of the fuse material 10. Is removed to form a fuse opening window 12. The fuse material 10 is connected to the redundant control circuit region 14 through the connection layer 11. Of the fuse material 10 shown in FIG. 1, an uncut fuse cross section (AA ′) is shown in FIGS. 2A to 2C, and a cut fuse cross section (BB ′) is shown in FIGS. 3A to 3C. .

  2A to 2C show cross sections of portions including the fuse material in the memory cell (FIG. 2A), peripheral circuit (FIG. 2B), and redundant circuit (FIG. 2C) regions formed on the same substrate, respectively. is there. The memory cell (FIG. 2A) and the peripheral circuit (FIG. 2B) are shown for reference in correspondence with the redundant circuit (FIG. 2C). Here, the redundant circuit (FIG. 2C) having a redundant function is shown. A configuration of the semiconductor circuit will be described. In the redundant circuit, a groove type isolation region 107 and a diffusion layer region 106 are formed on a silicon substrate. The diffusion layer regions 106 adjacent to both ends of the groove type isolation region 107 correspond to the connection layer 11 in FIG. 1, and the diffusion layer regions 106 connected to the outer edge portions of the gate electrode 108 and the gate electrode 108 in FIG. This corresponds to the redundant control circuit area 14. For example, the bit line 110 in the memory cell region (FIG. 2A) formed of tungsten is used as the first wiring layer 110 in the peripheral circuit and the redundant circuit, and is connected to the diffusion layer 106 by the plug 109. In the memory cell region, a storage capacitor composed of the lower electrode 111, the insulating film 112, and the upper electrode 113 is formed, and is connected to the diffusion layer 106 by a plug 105. The second wiring layer 115 is made of aluminum, for example, and is connected to the first wiring layer 110 by a plug 114. The third wiring layer 117 is formed of aluminum, for example, and is connected to the second wiring layer 115 by the plug 116. A protective film made of, for example, a nitride film 118 and a polyimide film 119 is formed on the second wiring layer. In the redundant circuit shown in FIG. 2C, the fuse 132 is formed in the same layer as the second wiring layer 115 in the memory cell region and the peripheral circuit region, and the diffusion layer passes through the plug 114, the first wiring layer 110, and the plug 109. 106 and further connected to the source and drain of the MOS transistor of the internal redundancy control circuit section. On the other hand, the fuse 132 shown in FIG. 3C is cut by a laser, and the insulating film 120 on the fuse 132 evaporates due to heat at the time of laser irradiation and disappears as a fuse exposed portion 133. For this reason, a part of the cut surface of the fuse 132 is exposed to the outside.

  Here, FIG. 4 shows an outline of a conventional semiconductor device manufacturing process. A conventional semiconductor device manufacturing process includes the formation of a wiring layer on a substrate, the formation of a protective film, and the opening of the protective film, followed by laser trimming (step S01), probe test (step S02), back grinding (step S03), Dicing (step S04), die bonding (step S05), wire bonding (step S06), and resin mold (step S07) are provided. As shown in FIG. 4, the state in which the cut surface of the fuse 132 is partially exposed to the outside continues from the laser trimming (step S01) until the resin mold (step S07) is completed. FIGS. 5A to 5C show states in which the protective films 118 and 119 covering the chip surface are charged in the process from the laser trimming (step S01) to the resin mold (step S07) shown in FIG. In particular, in the redundant circuit shown in FIG. 5C, the charged particles (electrons) 134 charged on the protective film enter from the cut surface of the cut fuse 132 and are discharged to the gate electrode 108 through the diffusion layer 106 to be gate insulating film. Etc. may be destroyed (indicated by path 135). As a result, malfunction or damage occurs in the redundant control circuit.

  In relation to the above-described technology, the following proposals have been made.

  In "Semiconductor integrated circuit device and method for manufacturing the same" disclosed in Japanese Patent Application Laid-Open No. 11-17016, redundancy has a redundant bit, and a defective bit is replaced with a redundant bit by cutting a fuse (agreeing with a fuse). In the semiconductor integrated circuit device provided with the circuit, the fuse is composed of a first fuse that is cut after the final passivation film is formed and a second fuse that is cut before the final passivation film is formed. Semiconductor integrated circuit devices have been proposed. In these structures, since the protective film on the fuse is removed, a guard ring is mainly installed for the purpose of ensuring moisture resistance and preventing external contamination. This guard ring is characterized in that (1) it surrounds the fuse seamlessly and (2) there is no need to connect to the substrate in particular, and it is in an electrically floating state.

In addition, in the “semiconductor device and manufacturing method thereof” disclosed in Japanese Patent Application Laid-Open No. 2000-156212, a fuse provided on a semiconductor substrate (agreeing with a fuse), a plurality of insulating films formed on the fuse, In a semiconductor device having a fuse cutting window opened in an upper insulating film among a plurality of insulating films on a fuse, the inner bottom surface of the fuse cutting window is flat and has a metal film on a side surface of the fuse cutting window Semiconductor devices have been proposed. Also in this example, the metal film disposed on the side surface portion of the fuse cutting window does not need to be connected to the substrate, and is completely different from the purpose of discharging charged charged particles to the substrate.
That is, in the conventional semiconductor devices disclosed in Patent Documents 1 and 2, a conductive layer such as a guard ring is disposed in the vicinity of the fuse cutting window for purposes different from the present invention, such as improvement in moisture resistance or ease of processing. However, the technical idea of discharging charged particles charged on the protective film of the fuse part is not disclosed at all. Regarding the point of the present invention, which is prevention of destruction of the internal circuit by the charged particles, No solution is shown.

JP-A-11-17016 JP 2000-156212 A

  An object of the present invention is to provide a highly reliable semiconductor device having a function of replacing a defective bit with a redundant bit by cutting a fuse material and having particularly high anti-static property and a method for manufacturing the same.

  In the following, means for solving the problem will be described using reference numerals with parentheses used in [Best Mode for Carrying Out the Invention]. These symbols are added in order to clarify the correspondence between the description of [Claims] and the description of the best mode for carrying out the invention. ] Should not be used for interpretation of the technical scope of the invention described in the above.

  The semiconductor device of the present invention includes a substrate and a plurality of wiring layers (110, 115, 117) formed on the substrate, and the upper wiring layer (117) that is the uppermost layer among the plurality of wiring layers. The fuse portion (132) is formed by the wiring layer (115) formed below, and the antenna portion (electrically connected to the substrate) by the upper wiring layer (117) formed in the upper region of the fuse portion ( 137) is formed.

  In the semiconductor device of the present invention, the substrate has a diffusion layer (106) on the upper surface of the substrate, the plurality of wiring layers (110, 115, 117) are formed on the diffusion layer, A fuse window formed by removing the protection layer (118, 119) formed on the wiring layer (117) and the protection layer stacked on the fuse portion so that the fuse portion (132) can be cut. Part (131).

  Moreover, the antenna part (137) in the semiconductor device of the present invention is arranged so that at least a part of the antenna part (137) is exposed to the fuse window part (131).

  The antenna portions (137, 15) in the semiconductor device of the present invention have fuse window portions (131, 12) along the outer edge of one of the two end portions of the fuse portions (132, 10). ) Including a first antenna portion arranged linearly and a second antenna portion arranged linearly inside the fuse window along the outer edge of the other end.

  In the semiconductor device of the present invention, the antenna portions (137, 16) are annularly arranged in the fuse window portions (131, 12) along the outer edges of the two end portions of the fuse portions (132, 10). Is done.

  In the semiconductor device of the present invention, the antenna portions (137, 17) include the fuse window portion (131, 17) along the outer edge of one of the two end portions of the fuse portions (132, 10). 12) A third antenna portion arranged in a straight line so that at least a portion thereof is exposed in the inside, and a linear arrangement so that at least a portion is exposed in the fuse window portion along the outer edge of the other end portion. And a fourth antenna unit.

  In the semiconductor device of the present invention, the antenna portions (137, 18) are at least partially in the fuse window portions (131, 12) along the outer edges of the two end portions of the fuse portions (132, 10). Is arranged in an annular shape so as to be exposed.

  A semiconductor memory according to the present invention comprises a memory cell region (51) and a semiconductor device (52) according to any one of claims 1 to 6 for performing redundancy control of the memory cell region, An I / O (59) which is an input / output unit with respect to the device, and a peripheral circuit (58) for performing interface control with the external device, and includes a memory cell region, a semiconductor device, and an I / O O and the peripheral circuit are integrally formed on the same substrate.

  The semiconductor device manufacturing method of the present invention also includes a fuse part forming step for forming a wiring layer (110, 115, 117) to be a fuse part on a substrate, and an antenna part in an upper region of the fuse part (132). And an antenna part forming step for forming an upper wiring layer (117) to be (137), and in the fuse part forming step, the antenna part is electrically connected to the substrate.

  Further, the method for manufacturing a semiconductor device of the present invention further includes a protective layer forming step for forming a protective layer (118, 119) on the upper wiring layer (117), and a fuse part (132) can be cut. A fuse window portion forming step of forming a fuse window portion (131) by removing the protective layer laminated on the upper region of the fuse portion.

  In the method for manufacturing a semiconductor device of the present invention, the antenna part forming step forms the upper wiring layer so that at least a part of the antenna part (137) is exposed to the fuse window part (131).

  In the method of manufacturing a semiconductor device according to the present invention, the antenna part forming step may include an outer edge of one end part of the two end parts of the fuse parts (132, 10). A first antenna portion arranged linearly along the fuse window portion (131, 12), and a second antenna portion arranged linearly inside the fuse window portion along the outer edge of the other end portion. An upper wiring layer (117) is formed so as to be constituted by the following.

  In the method of manufacturing a semiconductor device according to the present invention, the antenna portion forming step includes a fuse window portion (131) along the outer edge of the two end portions of the antenna portions (137, 16). 12) The upper wiring layer (117) is formed so as to be annularly arranged in the interior.

  In the method of manufacturing a semiconductor device according to the present invention, the antenna portion forming step may include an outer edge of one end portion of the two end portions of the antenna portions (137, 17) of the fuse portions (132, 10). A third antenna portion that is formed in a straight line so that at least a portion is exposed in the fuse window portion along at least, and at least a portion in the fuse window portions (131, 12) along the outer edge of the other end portion The upper wiring layer (117) is formed so as to be constituted by the fourth antenna portion that is formed in a straight line so as to be exposed.

  In the method of manufacturing a semiconductor device according to the present invention, the antenna portion forming step includes a fuse window portion (131) along the outer edge of the two end portions of the antenna portions (137, 18). 12), an upper wiring layer (117) is formed so that at least a part thereof is exposed and disposed in an annular shape.

  According to the present invention, by cutting the fuse material, it has a function of replacing a defective bit with a redundant bit, and in particular, the protective layer stacked above the fuse layer formation region is removed so that the fuse material can be cut. A conductive antenna part formed by the uppermost wiring layer laminated at the upper part of the fuse layer formation region is prevented by charging at least part of the fuse window part, thereby preventing charging breakdown from the fuse cutting part It is possible to provide a semiconductor device that can be used and a manufacturing method thereof.

  The best mode for carrying out a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the accompanying drawings.

  The semiconductor device of the present invention is a semiconductor device having a function for switching a defective bit to a redundant bit by cutting the fuse material. The semiconductor device of the present invention includes a substrate on which a diffusion layer is formed, a plurality of wiring layers formed on the diffusion layer, and a protection formed on an upper wiring layer that is the uppermost layer among the wiring layers. With layers. In addition, there are plugs for electrically connecting adjacent layers of the plurality of wiring layers and the lower wiring layer, which is the lowest layer among the plurality of wiring layers, and the diffusion layer. In the semiconductor device of the present invention, the wiring layer formed below the upper wiring layer among the plurality of wiring layers is formed as a fuse layer, and when the defective bit is switched to the redundant bit, the fuse layer The protective layer laminated on the upper part of the fuse layer forming region is removed so that the fuse window portion can be cut to form a fuse window portion. In particular, the semiconductor device of the present invention includes an antenna portion formed by an upper wiring layer formed above the fuse layer formation region. The antenna portion is formed so that at least a part thereof is exposed to the fuse window portion. As a result, even when the surface of the semiconductor device is charged with charged particles (electrons), it penetrates from the fuse cross section exposed at the lowest part of the conventional fuse window and damages the internal circuit via the gate electrode. The charged particles that have been made are further guided to the antenna portion formed in the upper layer portion before penetrating into the fuse cross section. The charged particles (electrons) are discharged into the substrate from the diffusion layer region formed on the substrate surface via the antenna unit. In the semiconductor device of the present invention, as described above, charged particles (electrons) existing on the surface at the time of charging are prevented from penetrating from a conventional fuse cross section and entering a path that damages an internal circuit. As a result, a semiconductor device capable of preventing charging breakdown in advance even when the fuse cross section is provided is realized.

(Embodiment 1)
A semiconductor device having a fuse will be described below by taking a DRAM as an example.
FIG. 6 shows a block configuration of a semiconductor memory formed on the same substrate and including a semiconductor device as a redundant circuit according to the first embodiment of the present invention. The semiconductor memory includes a memory cell region 51, a redundancy circuit 52, a peripheral circuit 58, and an I / O 59 for performing redundancy control of the memory cell region 51. In the memory cell area 51, a row decoder driver 54 and a row address buffer 53 are connected in series to the word line 61. A sense amplifier 55, a column decoder driver 56, and a column address buffer 57 are connected in series to the bit lines in the memory cell region 51, respectively.

  When a defect exists in the memory cell region 51, the word line 61 or the bit line 60 connected to the defective bit in the memory cell region 51 is replaced with a redundant line by cutting the corresponding fuse in the redundancy circuit 52. To achieve normal operation. FIG. 7 is a diagram showing an upper schematic configuration of a portion including the fuse material 10 in the semiconductor device as a redundant circuit according to the first embodiment of the present invention. As shown in FIG. 7, in the semiconductor device according to the present embodiment, in order to ensure a cutting margin of the fuse material 10, the protective film laminated on the fuse material 10 is removed, and the fuse opening window 12. Is opened. The fuse material 10 is connected to the redundant control circuit region 14 through the connection layer 11. Of the fuse material 10 shown in FIG. 7, cut fuse cross sections (C-C ′) are shown in FIGS. 8A to 8C. 9A to 9C show cross sections (D-D ') where no fuse is arranged.

  8A to 8C show cross sections of the portions including the fuse material of the memory cell (FIG. 8A), the peripheral circuit (FIG. 8B), and the redundant circuit (FIG. 8C) formed on the substrate, respectively. The memory cell (FIG. 8A) and the peripheral circuit (FIG. 8B) are shown for reference in correspondence with the redundant circuit (FIG. 8C) formed on the same substrate. Here, the redundancy having a redundant function is shown. The configuration of the circuit (FIG. 8C) will be described. In the redundant circuit, a groove type isolation region 107 and a diffusion layer region 106 are formed on a silicon substrate. The diffusion layer regions 106 adjacent to both ends of the groove type isolation region 107 correspond to the connection layer 11 in FIG. 7, and the diffusion layer regions 106 connected to the outer edge portions of the gate electrode 108 and the gate electrode 108 in FIG. This corresponds to the redundant control circuit area 14. For example, the bit line 110 in the memory cell region (FIG. 8A) is formed of tungsten, and is used as the first wiring layer 110 in the peripheral circuit and the redundant circuit, and is connected to the diffusion layer 106 through the plug 109. In the memory cell shown in FIG. 8A, a storage capacitor is formed by the lower electrode 111, the insulating film 112, and the upper electrode 113. The formed storage capacitor is connected to the diffusion layer 106 through the plug 105. The second wiring layer 115 is formed of aluminum, for example, and is connected to the first wiring layer 110 by a plug 114 in the peripheral circuit region (FIG. 8B). The third wiring layer 117 is formed of aluminum, for example, and is connected to the second wiring layer 115 by the plug 116. A protective film made of, for example, a nitride film 118 and a polyimide film 119 is formed on the third wiring layer 117. On the other hand, in the semiconductor device as a redundant circuit according to the present embodiment shown in FIG. 8C, the fuse 132 is formed in the same layer as the second wiring layer 115 in the memory cell region and the peripheral circuit region, and the plug 114, the first It is connected to the diffusion layer 106 through one wiring layer 110 and a plug 109, and further connected to the source and drain of the MOS transistor of the internal redundancy control circuit section through the diffusion layer 106. The fuse 132 shown in FIG. 8C is cut by a laser. The insulating film 120 above the fuse 132 evaporates and disappears due to heat at the time of laser irradiation, and a fuse exposed portion 133 is formed. For this reason, a part of the cut surface of the fuse 132 is exposed to the outside.

  This embodiment further includes a conductive antenna 137 (FIG. 8C) formed in the same layer as the third wiring layer 117 in the memory cell region and the peripheral circuit region. As shown in FIG. 9C, the antennas 137 and 15 (see FIG. 7) separated into two formation portions that are each formed in a straight line along the outer edges of both ends of the fuses are respectively provided at some positions. Thus, the plug 116, the second wiring layer 115, the plug 114, the first wiring layer 110, and the plug 109 are connected to the diffusion layer region 106 that is separated from the internal circuit. Further, as shown in FIG. 8C, in the present embodiment, the protective film 118, 119 in the region including the fuse 132 and the antenna 137 of the redundant circuit is removed, and the fuse opening window 131 is formed. As a result, the antenna 137 is arranged in such a manner that at least a part thereof is exposed to the fuse opening window 131.

  10A to 10C schematically show the case where the surfaces of the semiconductor device, the memory cell, and the peripheral circuit as the redundant circuit in this embodiment are charged. In the semiconductor device of the present invention (FIG. 10C), at least part of the fuse opening window 131 is formed by removing the protective layer laminated on the upper part of the fuse layer forming region so that the fuse material can be cut. Is exposed and has an antenna 137 formed by the uppermost wiring layer stacked on the fuse layer formation region, whereby a retracting path 139 (the antenna 137, the plug 116, the first of the charged particles 134 that adheres to the surface during charging) is provided. A diffusion layer region 106) is formed that is separated from the two wiring layers 115, the plug 114, the first wiring layer 110, the plug 109, and the internal circuit. Thereby, the charged particles generated by charging are introduced into the antenna 137 formed in an upper layer part than the fuse cutting part before penetrating into the fuse cutting part via the fuse opening window 131 and the fuse exposure part 133, Discharged to the substrate. Therefore, the charging damage of the device, which has conventionally been caused by the charged particles penetrating from the fuse cutting portion, is prevented, and a highly reliable semiconductor device is realized.

  The antenna 137 in this embodiment has a role of discharging the charged electric charge on the protective film to the substrate, and as a guard ring for the purpose of ensuring moisture resistance and preventing external contamination as in the case of a conventional semiconductor device. It also has a role. However, the arrangement form of the antenna 137 provided in the semiconductor device of the present invention is not necessarily the same as in the case of a conventional guard ring as long as the exposed portion of the antenna 137 in the fuse opening window 12 is electrically connected to the substrate. The fuse material 10 does not need to be disposed so as to completely surround the fuse material 10 and is appropriately set according to the size of the fuse opening window 12 in the semiconductor device, the use environment, and the like.

(Manufacturing method of Embodiment 1)
FIG. 11 shows an outline of a manufacturing process based on the manufacturing method of the semiconductor device according to the first embodiment of the present invention in comparison with a conventional manufacturing process for forming a standard bonding pad. The manufacturing process of the semiconductor device according to the present embodiment includes the formation of the first wiring layer (step S10), the formation of the second wiring layer (step S11), the third wiring layer on the substrate on which the diffusion layer is formed. Formation (step S12), formation of protective film (step S13), opening of protective film (step S14), laser trimming (step S15), probe test (step S16), back grinding (step S17), dicing (step S18) , Die bonding (step S19), wire bonding (step S20), and resin mold (step S20). 12 to 17 show cross sections of the redundant circuit portion including the bonding pad portion and the fuse of the semiconductor device corresponding to the steps S10 to S15. Each of the manufacturing processes (steps S10 to S21) described above is based on a standard manufacturing process, and thus the description thereof is omitted here.

  However, in the method of manufacturing the semiconductor device according to the present embodiment, an optimal antenna 137 pattern is formed as needed in the same layer as the third wiring layer 117 in the step (step S12) shown in FIG. At the same time, the bonding pad 140 is formed by the third wiring layer. Further, in the step shown in FIG. 16 (step S14), the bonding pad opening 141 of the bonding pad 140 and the fuse opening window 131 are formed simultaneously. For this reason, the semiconductor device manufacturing method according to this embodiment does not require a new process for forming the antenna 137. Further, in the manufacturing process related to the manufacturing method according to the present embodiment, the state in which the cut surface of the fuse 132 is partially exposed toward the fuse opening window 131 that causes charging breakdown of the semiconductor device is laser trimming (step The process continues from S15) until the resin mold (step S21) is completed. As described above, in the semiconductor device according to the present embodiment, the charged particles adhering to the surface due to charging are transmitted via the antenna 137. Immediately discharged to the substrate.

(Embodiment 2)
FIG. 18 shows an upper schematic configuration of a semiconductor device according to the second embodiment of the present invention. The basic components of the present embodiment and the manufacturing method thereof are the same as those in the first embodiment. However, in the present embodiment, the formation pattern of the antenna 137 (antenna material 16) formed in the same layer as the third wiring layer is different from that of the first embodiment. The antenna 137 in the present embodiment is obtained by arranging the antenna 137 (FIG. 7) in the first embodiment in a ring shape along the wall surface of the fuse opening window 12.

  In this embodiment, in particular, the fuse layer is formed so as to be exposed in the fuse opening window 12 formed by removing the protective layer laminated on the upper part of the fuse layer formation region so that the fuse material can be cut. By having the annular antenna 137 (antenna material 16 shown in FIG. 18) formed by the uppermost wiring layer laminated on the upper part of the region, it adheres to the surface when the semiconductor device is charged as in the first embodiment. A retreat path for charged particles to be formed is formed. Then, the charged particles generated by the charging are introduced into the antenna 137 formed in the upper layer portion before penetrating the fuse cutting portion, and discharged to the substrate. As a result, charging damage to the device, which has conventionally occurred due to penetration of charged particles from the fuse cutting portion, is prevented, and a highly reliable semiconductor device is realized. Further, in the present embodiment, the antenna 137 completely surrounds the fuse portion and has a function as a guard ring, so that an improvement in reliability due to the function is realized.

(Embodiment 3)
FIG. 19 shows an upper schematic configuration (plan view) of a semiconductor device according to the third embodiment of the present invention. The basic components of the present embodiment and the manufacturing method thereof are the same as those in the first embodiment. However, in the present embodiment, the formation pattern of the antenna 137 (antenna material 17) formed in the same layer as the third wiring layer is different from that of the first embodiment. The antenna 137 in the present embodiment has a fuse along the outer edge of one of the two end portions of the fuse material 10 (end portions positioned above and below the fuse material 10 in FIG. 19). The antenna portion is arranged linearly so that at least a portion is exposed in the opening window 12, and is arranged linearly so that at least a portion is exposed in the fuse window portion along the outer edge of the other end portion. And an antenna portion. In the present embodiment, at least part of the fuse opening window 12 formed by removing the protective layer laminated on the upper part of the fuse layer forming region so that the fuse material can be cut is exposed. By having an antenna 137 (antenna material 17 shown in FIG. 19) formed by two antenna portions formed by the uppermost wiring layer laminated on the upper part of the formation region, the semiconductor device is similar to the first embodiment. This forms a retreat path for charged particles adhering to the surface when is charged. Then, the charged particles generated by the charging are introduced into the antenna 137 formed in the upper layer portion before penetrating the fuse cutting portion, and discharged to the substrate. This prevents charging damage to the device, which has been caused by the penetration of charged particles from the conventional fuse cutting portion, and realizes a highly reliable semiconductor device. In the present embodiment, the exposed area in the fuse opening window 12 of the antenna is obtained by extending a part of the antenna area in the first embodiment to the protective film side and overlapping the fuse opening window. Will increase. Thereby, a semiconductor device having a higher antistatic function than that of the semiconductor device of the first embodiment is realized.

(Embodiment 4)
FIG. 20 shows an upper schematic configuration of the semiconductor device according to the fourth embodiment of the present invention. The present embodiment has the respective constituent elements of the second embodiment and the third embodiment. Further, the manufacturing method of the present embodiment is the same as that in the first embodiment. As shown in FIG. 20, the antenna 137 in the present embodiment is a partial region of the ring-shaped antenna (FIG. 18) in the second embodiment of the antenna form (FIG. 19) shown in the third embodiment. Thus, it has the structure which extended to the protective film side and overlapped with the opening window. In the present embodiment, at least part of the fuse opening window 12 formed by removing the protective layer laminated on the upper part of the fuse layer forming region so that the fuse material can be cut is exposed. By having the antenna 137 (antenna material 18 shown in FIG. 20) formed by the uppermost wiring layer laminated on the upper part of the formation region, the surface when the semiconductor device is charged as in the first to third embodiments. A retraction path for charged particles adhering to the surface is formed. Then, the charged particles generated by the charging are introduced into the antenna 137 formed in the upper layer portion before penetrating the fuse cutting portion, and discharged to the substrate. This prevents charging damage to the device, which has been caused by the penetration of charged particles from the conventional fuse cutting portion, and realizes a highly reliable semiconductor device.

(Embodiment 5)
The semiconductor memory according to the fifth embodiment of the present invention includes a memory cell region and any one of the semiconductor devices described in the first to fourth embodiments as a redundant circuit for performing redundancy control of the memory cell region. And an I / O that is an input / output unit with respect to the external device, and a peripheral circuit for performing interface control with the external device (see FIG. 6 for a schematic configuration of the semiconductor memory). The memory cell region, the semiconductor device described in the first to fourth embodiments as a redundant circuit, the I / O, and the peripheral circuit are each integrally formed on the same substrate. In the memory cell region, a row decoder driver and a row address buffer are connected in series to the word line. In addition, a sense amplifier, a column decoder driver, and a column address buffer are connected in series to the bit line in the memory cell region.

  In the present embodiment, when a defect exists in the memory cell region, a defective bit in the memory cell region can be obtained by cutting the fuse of any one of the semiconductor devices described in the first to fourth embodiments as a redundant circuit. Normal operation is realized by replacing a word line or a bit line connected to a redundant line.

In the present embodiment, the surface of the semiconductor memory is charged by providing any one of the semiconductor devices of the first to fourth embodiments as the redundant circuit, and in the conventional case, the fuse is disconnected after switching the redundant system. The semiconductor memory is prevented from being damaged due to penetration of charged particles from the portion, and a highly reliable semiconductor memory is realized.
In the above description of the embodiment, the DRAM is used as an example. However, the semiconductor device of the present invention is not limited to the DRAM. That is, the present invention can be applied not only to other memories (SRAM, flash memory, etc.) but also to semiconductor devices other than a memory having fuses.

It is a figure which shows schematic structure of the fuse area | region (upper surface) in the conventional semiconductor device. It is a figure which shows the uncut fuse cross section (A-A ') in FIG. It is a figure which shows the uncut fuse cross section (A-A ') in FIG. It is a figure which shows the uncut fuse cross section (A-A ') in FIG. It is a figure which shows the fuse cross section (B-B ') cut | disconnected in FIG. It is a figure which shows the fuse cross section (B-B ') cut | disconnected in FIG. It is a figure which shows the fuse cross section (B-B ') cut | disconnected in FIG. It is a figure which shows the manufacturing process of the conventional semiconductor device. In FIG. 3A, it is a figure which shows the state which the electric charge by charging produced on the surface. In FIG. 3B, it is a figure which shows the state which the electric charge by charging produced on the surface. In FIG. 3C, it is a figure which shows the state which the electric charge by charging produced on the surface. 1 is a block diagram of a semiconductor memory including a semiconductor device according to an embodiment of the present invention as a redundant circuit. It is a figure which shows schematic structure of the fuse area | region (upper surface) in the semiconductor device concerning Embodiment 1 of this invention. It is a figure which shows the fuse cross section (C-C ') cut | disconnected in FIG. It is a figure which shows the fuse cross section (C-C ') cut | disconnected in FIG. It is a figure which shows the fuse cross section (C-C ') cut | disconnected in FIG. It is a figure which shows a cross section (D-D ') in FIG. It is a figure which shows a cross section (D-D ') in FIG. It is a figure which shows a cross section (D-D ') in FIG. In FIG. 9A, it is a figure which shows the state which the electric charge by charging produced on the surface. FIG. 9B is a diagram showing a state in which electric charges are generated on the surface in FIG. 9B. In FIG. 9C, it is a figure which shows the state which the electric charge by charging produced on the surface. It is a figure which shows the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. FIG. 5 is a diagram illustrating a process of forming a first wiring layer in the manufacturing process of the semiconductor device according to the first embodiment. FIG. 10 is a diagram showing a step of forming a second wiring layer in the semiconductor device manufacturing process according to the first embodiment. FIG. 6 is a diagram showing a step of forming a third wiring layer in the semiconductor device manufacturing process according to the first embodiment. FIG. 5 is a diagram illustrating a process of forming a protective film layer in the manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a diagram illustrating a process of opening a protective film layer in the manufacturing process of the semiconductor device according to the first embodiment. It is a figure which shows the process from laser trimming to wire bonding among the manufacturing processes of the semiconductor device concerning Embodiment 1. FIG. It is a figure which shows schematic structure of the fuse area | region (upper surface) in the semiconductor device concerning Embodiment 2 of this invention. It is a figure which shows schematic structure of the fuse area | region (upper surface) in the semiconductor device concerning Embodiment 3 of this invention. It is a figure which shows schematic structure of the fuse area | region (upper surface) in the semiconductor device concerning Embodiment 4 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Fuse material 11 ... Connection layer 12 ... Fuse window 13 ... Cut fuse 14 ... Redundant control circuit area 51 ... Memory cell area 52 ... Redundant circuit 53 ... Row address buffer 54 ... Row decoder driver 55 ... Sense up 56 ... Column Decoder driver 57 ... column address buffer 58 ... peripheral circuit 59 ... I / O
60 ... Bit line 61 ... Word line 105 ... Plug 106 ... Diffusion layer region 107 ... Groove type isolation region 108 ... Word line / gate electrode 109 ... Plug 110 ... First wiring layer (bit line)
111 ... Lower electrode 112 ... Insulating film 113 ... Upper electrode 114 ... Plug 115 ... Second wiring layer 116 ... Plug 117 ... Third wiring layer 118 ... Nitride film 119 ... Polyimide film 120 ... Insulating film 131 ... Fuse opening window 132 ... Fuse 133 ... Fuse exposed portion 134 ... charged particle 137 ... antenna 140 ... bonding pad 141 ... bonding pad opening

Claims (15)

A substrate,
A plurality of wiring layers formed on the substrate;
Of the plurality of wiring layers, a fuse portion is formed by the wiring layer formed below the upper wiring layer which is the uppermost layer,
An antenna portion electrically connected to the substrate is formed by the upper wiring layer formed in an upper region of the fuse portion. The semiconductor device according to claim 1,
The substrate has a diffusion layer on an upper surface of the substrate;
The plurality of wiring layers are formed on the diffusion layer,
A protective layer formed on the upper wiring layer;
A semiconductor device comprising: a fuse window formed by removing the protective layer laminated on the fuse part so that the fuse part can be cut. The semiconductor device according to claim 2,
The antenna unit is a semiconductor device arranged so that at least a part of the antenna unit is exposed in the fuse window. The semiconductor device according to claim 2 or 3,
The antenna unit is
Of the two end portions of each of the fuse portions, a first antenna portion that is linearly arranged in the fuse window portion along the outer edge of one end portion;
A semiconductor device comprising: a second antenna portion linearly arranged in the fuse window along the outer edge of the other end. The semiconductor device according to claim 2 or 3,
The antenna unit is a semiconductor device in which the inside of the fuse window is annularly arranged along outer edges of two end portions of each of the fuse units. The semiconductor device according to claim 2 or 3,
The antenna unit is
Of the two end portions of each of the fuse portions, a third antenna portion arranged in a straight line so that at least a part thereof is exposed in the fuse window portion along the outer edge of one end portion;
And a fourth antenna portion arranged in a straight line so that at least part of the fuse window portion is exposed along the outer edge of the other end portion. The semiconductor device according to claim 2 or 3,
The antenna unit is a semiconductor device arranged in an annular shape so that at least a part of the antenna unit is exposed in the fuse window along the outer edges of two end portions of each of the fuse units. A memory cell area;
The semiconductor device according to any one of claims 1 to 6, for performing redundancy control of the memory cell region;
I / O that is an input / output unit with an external device;
A peripheral circuit for interface control with an external device,
A semiconductor memory in which the memory cell region, the semiconductor device, the I / O, and the peripheral circuit are integrally formed on the same substrate. A fuse part forming step for forming a wiring layer to be a fuse part on the substrate;
An antenna portion forming step for forming an upper wiring layer to be an antenna portion in an upper region of the fuse portion;
In the fuse portion forming step, the antenna portion is a method for manufacturing a semiconductor device in which the antenna portion is electrically connected to the substrate. In the manufacturing method of the semiconductor device according to claim 9,
Furthermore, a protective layer forming step of forming a protective layer on the upper wiring layer,
A fuse window portion forming step of forming a fuse window portion by removing the protective layer laminated on an upper region of the fuse portion so that the fuse portion can be cut. In the manufacturing method of the semiconductor device according to claim 10,
The antenna part forming step is a method of manufacturing a semiconductor device in which the upper wiring layer is formed so that at least a part of the antenna part is exposed to the fuse window part. In the manufacturing method of the semiconductor device according to claim 10 or 11,
The antenna part forming step includes a first antenna part in which the antenna part is linearly arranged in the fuse window part along an outer edge of one of the two end parts of the fuse part. A method of manufacturing a semiconductor device, wherein the upper wiring layer is formed so as to be constituted by a second antenna portion that is linearly arranged in the fuse window portion along the outer edge of the other end portion. In the manufacturing method of the semiconductor device according to claim 10 or 11,
In the antenna part forming step, the upper wiring layer is formed so that the antenna part is annularly arranged in the fuse window along the outer edge of each of the two ends of the fuse part. . In the manufacturing method of the semiconductor device according to claim 10 or 11,
In the antenna portion forming step, the antenna portion is linearly formed so that at least a part of the antenna portion is exposed in the fuse window portion along the outer edge of one of the two end portions of the fuse portion. The third antenna part is formed, and the fourth antenna part is formed linearly so that at least a part is exposed in the fuse window part along the outer edge of the other end part. A method of manufacturing a semiconductor device for forming an upper wiring layer. In the manufacturing method of the semiconductor device according to claim 10 or 11,
In the antenna portion forming step, the upper wiring layer is arranged so that the antenna portion is arranged in an annular shape with at least a part exposed in the fuse window portion along an outer edge of each of the two end portions of the fuse portion. A method for manufacturing a semiconductor device to be formed.

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