JP2007122794A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of improving a test efficiency and a production yield. <P>SOLUTION: The semiconductor memory device is provided with an input command decoder, a command generator, a semiconductor memory, and a write-in determination circuit. First data is written in the semiconductor memory based on second command and first address information from the command generator. The write-in determination circuit compares the first data with the second data read out from the first address and determines whether write-in is performed normally or not. Third command is input further to the input command decoder relieving the first data. When it is determined that write-in is not performed normally, the input command decoder supplies fourth command to which the third command is decoded and the first address information to the command generator. The command generator supplies the second address information being different from the first address, the second command, and the first data to the semiconductor memory based on the fourth command. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device.

Conventionally, there has been proposed a semiconductor memory device capable of relieving data written in a defective block (see, for example, Patent Documents 1 to 4).
JP-A-2005-4504 (page 1-9, FIG. 1-5) Japanese Patent Laid-Open No. 5-204561 (page 1-8, FIG. 1-9) JP-A-6-274409 (page 1-10, FIG. 1-21) JP-A-8-115175 (page 1-13, FIG. 1-19)

  In the techniques of Patent Documents 1 to 4, defective blocks in a semiconductor memory device are relieved by control from a host program. However, since defective blocks tend to differ depending on the semiconductor memory device, a plurality of semiconductor memory devices are difficult to be tested while being simultaneously relieved. As a result, the semiconductor memory devices may be tested one by one, and the test efficiency tends to be reduced.

  If a plurality of semiconductor memory devices are tested at the same time without defective blocks being remedied, the test efficiency is improved, but the product yield tends to decrease.

  An object of the present invention is to provide a semiconductor memory device that can suppress a reduction in test efficiency and can improve a product yield.

  A semiconductor memory device according to the present invention includes a decode circuit, a command generator, a memory circuit, and a write determination circuit. The decoding circuit receives the first data, the first command, and the first address information. The first command is a command for writing the first data. The first address information is information on the first address. The first address is an address where the first data is written. The decode circuit generates a second command. The second command is a command obtained by decoding the first command. The command generator transfers the second command, the first data, and the first address information based on the second command received from the decoding circuit. The memory circuit is written with the first data based on the second command and the first address information received from the command generator. The write determination circuit determines whether or not writing to the memory circuit has been normally performed based on the first data and the second data. The second data is data read from the first address in the memory circuit. A third command is further input to the decode circuit. The third command is a command for relieving the first data. The decode circuit supplies the fourth command and the first address information to the command generator when the write determination circuit determines that the writing to the storage circuit is not normally performed. The fourth command is a command obtained by decoding the third command. The command generator supplies the second address information, the second command, and the first data to the storage circuit based on the fourth command received from the decoding circuit. The second address information is information on the second address. The second address is an address different from the first address.

  In this semiconductor memory device, the decode circuit supplies the fourth command and the first address information to the command generator when the write determination circuit determines that the writing to the storage circuit is not normally performed. The command generator supplies the second address information, the second command, and the first data to the storage circuit based on the fourth command. As a result, the first data can be relieved to an address that has not been normally written in the memory circuit without providing information on the address to be relieved from the outside.

  As described above, when the third command is input, if the writing is normally performed, the third command can be ignored. Therefore, even when there are a plurality of commands, the test can be performed while simultaneously relieving. Therefore, reduction in test efficiency can be suppressed and the yield of products can be improved.

  A method for controlling a semiconductor memory device according to the present invention is a method for controlling a semiconductor memory device having a memory circuit, and includes a first input step, a decode step, a transfer step, a first write step, a determination step, A second input step, a supplying step, and a second writing step are provided. In the first input step, first data, a first command, and first address information are input. The first command is a command for writing the first data. The first address information is information on the first address. The first address is an address where the first data is written. In the decoding step, a second command is generated. The second command is a command obtained by decoding the first command. In the transfer step, the second command, the first data, and the first address information are transferred based on the second command. In the first writing step, the first data is written to the memory circuit based on the second command and the first address information. In the determination step, it is determined based on the first data and the second data whether or not the data has been normally written in the storage circuit. The second data is data read from the first address in the memory circuit. In the second input step, the third command is input. The third command is a command for relieving the first data. In the supplying step, when it is determined in the determining step that the memory circuit is not normally written, the fourth command and the first address information are supplied. The fourth command is a command obtained by decoding the third command. In the second writing step, the second address information, the second command, and the first data are written to the memory circuit based on the fourth command. The second address information is information on the second address. The second address is an address different from the first address.

  In this semiconductor memory device control method, in the supply step, when it is determined in the determination step that the memory circuit is not normally written, the fourth command and the first address information are supplied. In the second writing step, the second address information, the second command, and the first data are written to the memory circuit based on the fourth command. As a result, the first data can be relieved to an address that has not been normally written in the memory circuit without providing information on the address to be relieved from the outside.

  As described above, when the third command is input, if the writing is normally performed, the third command can be ignored. Therefore, even when there are a plurality of commands, the test can be performed while simultaneously relieving. Therefore, reduction in test efficiency can be suppressed and the yield of products can be improved.

  In the semiconductor memory device according to the present invention, since the first data can be relieved autonomously, even when there are a plurality of data, it is possible to test while relieving at the same time. Therefore, reduction in test efficiency can be suppressed and the yield of products can be improved.

  In the method of controlling a semiconductor memory device according to the present invention, when the third command is input, if the writing is normally performed, the third command can be ignored. be able to. Therefore, reduction in test efficiency can be suppressed and the yield of products can be improved.

<First Embodiment>
FIG. 1 shows a configuration diagram of the semiconductor memory device according to the first embodiment of the present invention.

<Schematic configuration of semiconductor memory device>
The semiconductor memory device 1 mainly includes an input command decoder 10, a command generator 30, a semiconductor memory 40, a write determination circuit 60 and a data latch 70.

  The input command decoder 10 is connected to an external input terminal (not shown), and is also connected to the command generator 30, the data latch 70, and the write determination circuit 60. The command generator 30 is connected to the input command decoder 10 and the semiconductor memory 40. Further, the write determination circuit 60 is connected to an external output terminal (not shown), and is also connected to the input command decoder 10, the semiconductor memory 40, and the data latch 70.

<Schematic operation of semiconductor memory device>
(Normal operation)
The semiconductor memory device 1 is connected to a tester (not shown) in an assembled state before being shipped, and the electrical characteristics and the like are inspected. In this case, the first command C1, the first data D1, the chip enable signal CE1, and the first address information A1 are input to the input command decoder 10 of the semiconductor memory device 1 through the external input terminal. Here, the first command C1 is a command for writing the first data D1. The first address information A1 is information on the first address. The first address is an address where the first data D1 is written. The input command decoder 10 decodes the first command C1 to generate a second command C1a. The second command C1a is a command obtained by decoding the first command C1.

  The command generator 30 receives the second command C1a, the first data D1, and the first address information A1 from the input command decoder 10. The command generator 30 transfers the second command C1a, the first data D1, and the first address information A1 based on the second command C1a received from the input command decoder 10. The command generator 30 holds the second command C1a, the first data D1, and the first address information A1 until the next second command C1a is supplied.

  The first data D1 is written in the semiconductor memory 40 based on the first command C1. In the semiconductor memory 40, the second data D2 is read based on the fifth command C5. Here, the second data D2 is data read from the first address in the semiconductor memory 40.

  The data latch 70 receives the first data D1 from the input command decoder 10. The data latch 70 temporarily stores the first data D1 and supplies the first data D1 to the write determination circuit 60 at a predetermined timing.

  The write determination circuit 60 receives the first data D1 from the data latch 70. The write determination circuit 60 supplies the fifth command C5 to the semiconductor memory 40 and receives the second data D2 from the semiconductor memory 40. Then, the write determination circuit 60 determines whether or not the data has been normally written in the semiconductor memory 40 based on the first data D1 and the second data D2. The result determined by the write determination circuit 60 is supplied as an NG flag to the input command decoder 10 and the external output terminal. For example, the NG flag is OFF when the write determination circuit 60 determines that the writing to the semiconductor memory 40 is normally performed, and is “0”, but the writing to the semiconductor memory 40 is performed normally. If the write determination circuit 60 determines that it has not been turned on, it is turned on and becomes “1”. The write determination circuit 60 may supply the first data D1 and the first address information A1 to the external output terminal.

(Relief action)
The input command decoder 10 further receives a third command C3. The third command C3 is a command for relieving the first data D1. The input command decoder 10 supplies the fourth command C3a to the command generator 30 when the write determination circuit 60 determines that the writing to the semiconductor memory 40 is not normally performed. The fourth command C3a is a command obtained by decoding the third command C3.

  At this time, the command generator 30 supplies the second address information A2, the second command C1a, and the first data D1 to the semiconductor memory 40 based on the fourth command C3a received from the input command decoder 10. The second address information A2 is information on the second address. The second address is an address different from the first address. Further, the command generator 30 holds the second address information A2 until the next fourth command C3a is supplied.

  The first data D1 is written to the semiconductor memory 40 based on the first command C1 and the second address information A2. In the semiconductor memory 40, the third data D3 is read based on the fifth command C5. Here, the third data D3 is data read from the second address in the semiconductor memory 40.

  The write determination circuit 60 supplies the fifth command C5 to the semiconductor memory 40 and receives the third data D3 from the semiconductor memory 40. Then, the write determination circuit 60 determines whether or not the data has been normally written in the semiconductor memory 40 based on the first data D1 and the third data D3.

  Other points are the same as the normal operation.

<Detailed configuration of input command decoder>
The input command decoder 10 mainly includes a determination circuit 11 as shown in FIG. As shown in FIG. 4, the determination circuit 11 mainly includes a decoding unit 26 and a transfer determination unit 27.

  The decoding unit 26 decodes the input command. The decoding unit 26 mainly includes a command decoding circuit 12, a header program command decoding circuit 18, and an inverter 16.

  The command decode circuit 12 is connected to an external input terminal (not shown), and is also connected to the transfer determination unit 27 and the header program command decode circuit 18. The relief program command decode circuit 13 and the header program command decode circuit 18 are further connected to the transfer determination unit 27. As a result, the command decoded by any one of the command decode circuit 12, the relief program command decode circuit 13, and the header program command decode circuit 18 is supplied to the transfer determination unit 27.

  The inverter 16 is connected to the transfer determination unit 27. Accordingly, the chip enable signal CE1 input to the decoding unit 26 is supplied to the transfer determination unit 27 with its logic inverted.

  The transfer determination unit 27 determines whether or not the command decoded by the decoding unit 26 should be transferred, and transfers the command based on the determined result. The transfer determination unit 27 mainly includes an AND gate 17, an AND gate 21, and an OR gate 19.

  The AND gate 17 has a command decode circuit 12 and an inverter 16 connected to the input side, and an AND gate 21 connected to the output side.

  The OR gate 19 has a header program command decode circuit 18 and an NG flag NGF input terminal connected to the input side, and an AND gate 21 connected to the output side.

  The AND gate 21 has an OR gate 15 and an OR gate 19 connected to the input side, and a command generator 30 connected to the output side.

<Detailed operation of input command decoder>
(Normal operation)
The normal operation shown in FIG. 2 is executed at a predetermined clock timing.

  The command decode circuit 12 receives the first command C1 and the first data D1. The command decode circuit 12 decodes the first command C1 and generates a second command C1a. Then, the command decode circuit 12 supplies the second command C1a and the first data D1 to the AND gate 17. Further, an “L” active chip enable signal CE1 is input to the AND gate 17 with its logic inverted. Thereby, the AND gate 17 transfers the second command C1a to the AND gate 21 when the chip enable signal CE1 becomes active. At this time, the header program command decode circuit 18 is not used and its output is “0”.

  On the other hand, the NG flag NGF is input to the OR gate 19. Here, the NG flag NGF is “1” when turned ON, and is “0” when turned OFF.

  The AND gate 21 receives the output of the AND gate 17 and the output of the OR gate 19. That is, when the NG flag NGF is turned OFF, the AND gate 21 blocks the transfer of the second command C1a and the first data D1 to the command generator 30. The AND gate 21 transfers the second command C1a and the first data D1 to the command generator 30 when the NG flag NGF is turned on. As a result, when the write determination circuit 60 determines that the data is normally written to the semiconductor memory 40 (when the NG flag NGF is turned OFF) and the first data D1 is relieved, the next second The command C1a can be prevented from being transferred to the command generator 30. Further, when the first data D1 is not normally written and the NG flag NGF is set (NG flag NGF is turned ON), the next second command C1a is transferred to the command generator 30. it can.

(Relief action)
The relief operation shown in FIG. 3 is executed at the same clock timing as the normal operation.

  The command decode circuit 12 receives the third command C3. The relief program command is also transmitted under the control of the NG flag NGF as in the normal operation.

  The header program command decode circuit 18 decodes the header program third command C32 and generates a header program enable signal. Then, the header program command decode circuit 18 supplies a header program enable signal C32a to the OR gate 19.

  On the other hand, a header program enable signal C32a is input to the OR gate 19. Thus, regardless of whether the NG flag NGF is ON or OFF, the OR gate 19 outputs “1” when the header program enable signal C32a is input. As a result, the header program command is input to the AND gate 22 and is output from the AND gate 22 when “1” is input from the AND gate 17 to the AND gate 22.

  Thus, when the write determination circuit 60 determines that the writing to the semiconductor memory 40 is not normally performed (the NG flag NGF is turned ON) and the first data D1 is relieved, the fourth command C3a and The header program command can be transferred to the command generator 30. Further, the fourth command C3a can be prevented from being transferred to the command generator 30 when the repair of the first data D1 is completed and the NG flag NGF is cleared (NG flag NGF is turned OFF).

<Detailed configuration of semiconductor memory>
As shown in FIG. 5, the semiconductor memory 40 mainly includes a normal data storage area 41, a repair data storage area 43, and a management information storage area 42.

  The normal data storage area 41 is an area where normal writing is performed, and includes a first address. The normal data storage area 41 has 512 bytes as one page and 64K pages.

  The relief data storage area 43 is an area where writing for relief is performed when the normal data storage area 41 is not normally written, and includes a second address. As in the normal data storage area 41, the relief data storage area 43 has 512 bytes as one page, and is provided with 1K pages.

  The management information storage area 42 is an area where management information is written. The management information is information for managing that the relief data storage area 43 has been written for relief. In the management information storage area 42, 4 bytes are allocated to each page, and management information for 64K pages is provided.

  Specifically, as shown in FIG. 6, the management information mainly includes a repair execution flag 42a, a repair data storage address 42b, and an ECC parity 42c. The relief execution flag 42a is information indicating the presence or absence of relief. For example, the relief execution flag 42a is "1" when there is relief, and is "0" when there is no relief. The relief data storage address 42b is information on the address where the first data D1 is stored. For example, the relief data storage address 42b becomes the second address when there is relief, and becomes the first address when there is no relief. The ECC parity 42c is information indicating whether or not the second address is defective.

<Detailed operation of semiconductor memory>
(Normal operation)
The normal data storage area 41 stores the first data D1 at the first address based on the second command C1a and the first address information A1. In the management information storage area 42, in the management information corresponding to the first address, the repair execution flag 42a is set to “0”, and the repair data storage address 42b is left at the initial value “FFFh”.

  In the management information storage area 42, based on the fifth command C5, the management data relief data storage address 42b is not referred to, and the first address is specified as an address to be read.

  In the normal data storage area 41, the second data D2 is read from the first address based on the fifth command C5. The read second data D2 is supplied to the write determination circuit 60.

(Relief action)
The relief data storage area 43 stores the first data D1 at the second address based on the second command C1a and the second address information A2. In the management information storage area 42, in the management information corresponding to the first address, the repair execution flag 42a is set to “1”, and the repair data storage address 42b is set to the second address.

  In the management information storage area 42, based on the fifth command C5, the management data relief data storage address 42b is referred to, and the second address is specified as the address to be read.

  In the relief data storage area 43, the third data D3 is read from the second address based on the fifth command C5. The read third data D3 is supplied to the write determination circuit 60.

<Processing flow when the semiconductor memory device is inspected before shipping>
The flow of processing when the semiconductor memory device is inspected before shipping will be described with reference to the flowcharts shown in FIGS.

  In step S1 shown in FIG. 7 ((1) shown in FIG. 7), the first command and the first data are input to the semiconductor memory device. That is, the first command C1, the first data D1, the chip enable signal CE1, and the first address information A1 are input to the input command decoder 10 of the semiconductor memory device 1 through the external input terminal. Here, the first command C1 is a command for writing the first data D1. The first address information A1 is information on the first address. The first address is an address where the first data D1 is written. The input command decoder 10 decodes the first command C1 to generate a second command C1a. The second command C1a is a command obtained by decoding the first command C1.

  The command generator 30 receives the second command C1a, the first data D1, and the first address information A1 from the input command decoder 10. The command generator 30 transfers the second command C1a, the first data D1, and the first address information A1 based on the second command C1a received from the input command decoder 10. The command generator 30 holds the second command C1a and the first data D1 until the next first command C1 is supplied.

  In the initial state, the NG flag is OFF and is “0”. In the initial state, the FP flag is also OFF and is “0”. Here, the FP flag is a flag indicating whether or not the semiconductor device is a defective product. The FP flag is discarded as a defective product when turned on, and is a good product when turned off. Will be shipped.

  In step S2, the first data is written into the semiconductor memory. That is, the first data D1 is written in the normal data storage area in the semiconductor memory 40 based on the first command C1. In the semiconductor memory 40, the second data D2 is read based on the fifth command C5. Here, the second data D2 is data read from the first address in the semiconductor memory 40.

  In step S3, it is determined whether or not data has been normally written to the semiconductor memory. That is, the data latch 70 receives the first data D1 from the input command decoder 10. The data latch 70 temporarily stores the first data D1 and supplies the first data D1 to the write determination circuit 60 at a predetermined timing.

  The write determination circuit 60 receives the first data D1 from the data latch 70. The write determination circuit 60 supplies the fifth command C5 to the semiconductor memory 40 and receives the second data D2 from the semiconductor memory 40. Then, the write determination circuit 60 determines whether or not the data has been normally written in the semiconductor memory 40 (normal data storage area 41) based on the first data D1 and the second data D2. Specifically, the write determination circuit 60 compares the first data D1 and the second data D2, and determines that the writing is normally performed if they are the same, and the writing is normally performed if they are different. Judge that it is not. If it is determined that the writing has been normally performed, the process proceeds to step S5. If it is determined that the writing has not been performed normally, the process proceeds to step S4.

  In step S4, the NG flag is turned ON. That is, the write determination circuit 60 turns on the NG flag to “1”.

  In step S5, it is determined whether or not the process of step S2 has been performed for one page. If it is determined that one page has been performed, the process proceeds to step S6. If it is determined that one page has not been performed, the process proceeds to step S2.

  In step S6, the NG flag is output. That is, the result determined by the write determination circuit 60 is supplied as an NG flag to the input command decoder 10 and the external output terminal.

  In step S7, the third command is input. That is, the third command C3 is further input to the input command decoder 10. The third command C3 is a command for relieving the first data D1. The input command decoder 10 supplies the command generator 30 with the fourth command C3a, the header program command, and the first address information A1 when the write determination circuit 60 determines that the writing to the semiconductor memory 40 is not normally performed. To do. The fourth command C3a is a command obtained by decoding the third command C3.

  In step S17, it is determined whether or not the NG flag is ON. When it is determined that the NG flag NGF is ON, the process proceeds to step S8 ((2) shown in FIG. 7), and when it is determined that the NG flag NGF is not ON, step S16 (shown in FIG. 7). Go to (3)).

  In step S8 shown in FIG. 8 ((2) shown in FIG. 8), it is determined whether or not relief is possible. That is, the command generator 30 determines whether or not the second address exceeds the upper limit (for example, 1023) of the address of the repair data storage area 43 based on the held second address information A2. If it is determined that the upper limit is not exceeded, it is determined that relief is possible and the process proceeds to step S9. If it is determined that the upper limit is exceeded, it is determined that relief is not possible and the process proceeds to step S14. .

  In step S9, the second address is counted up. That is, the command generator 30 counts up the second address based on the fourth command C3a received from the input command decoder 10 and the held second address information A2. Then, the command generator 30 supplies the second address information A2, the second command C1a, and the first data D1 to the semiconductor memory 40. The second address information A2 is information on the second address. The second address is an address different from the first address. Further, the command generator 30 holds the second address information A2 until the next fourth command C3a is supplied.

  In step S10, the first data is replaced from the normal data storage area to the relief data storage area. That is, the first data D1 is written in the repair data storage area in the semiconductor memory 40 based on the first command C1 and the second address information A2. In the semiconductor memory 40, the third data D3 is read based on the fifth command C5. Here, the third data D3 is data read from the second address in the semiconductor memory 40.

  In step S15, it is determined whether or not the first data has been replaced for one page. That is, if it is determined that one page has been replaced, the process proceeds to step S11. If it is determined that one page has not been replaced, the process proceeds to step S10.

  In step S11, it is determined whether or not data has been normally written in the semiconductor memory. That is, the data latch 70 receives the first data D1 from the input command decoder 10. The data latch 70 temporarily stores the first data D1 and supplies the first data D1 to the write determination circuit 60 at a predetermined timing.

  The write determination circuit 60 receives the first data D1 from the data latch 70. The write determination circuit 60 supplies the fifth command C5 to the semiconductor memory 40 and receives the third data D3 from the semiconductor memory 40. Then, the write determination circuit 60 determines whether or not the data has been normally written in the semiconductor memory 40 (the relief data storage area 43) based on the first data D1 and the third data D3. Specifically, the write determination circuit 60 compares the first data D1 and the third data D3, determines that the writing is performed normally if they are the same, and performs the writing normally if they are different. Judge that it is not. If it is determined that the writing has been normally performed, the process proceeds to step S12. If it is determined that the writing has not been normally performed, the process proceeds to step S14.

  In step S16 ((3) shown in FIG. 8), writing to the management information storage area by the header program command is performed.

  In step S12, the NG flag is cleared. That is, the write determination circuit 60 turns off the NG flag to “0”.

  In step S13, it is determined whether writing has been performed for all pages (for example, 64K pages). If it is determined that writing has not been performed for all pages, the process proceeds to step S1 ((1) shown in FIG. 7). If it is determined that writing has been performed for all pages, processing is performed. Is terminated.

  In step S14, the FP flag is turned ON. That is, the write determination circuit 60 receives information from the command generator 30 that the FP flag is ON and is “1”. Alternatively, the write determination circuit 60 turns on the FP flag to “1” when it is determined that the writing is not normally performed in the semiconductor memory 40 (relief data storage area 43). The write determination circuit 60 outputs the FP flag to the external output terminal.

<Characteristics of semiconductor memory device>
(1)
Here, the input command decoder 10 supplies the fourth command C3a and the first address information A1 to the command generator 30 when the write determination circuit 60 determines that the writing to the semiconductor memory 40 is not normally performed. To do. The command generator 30 supplies the second address information A2, the second command C1a, and the first data D1 to the semiconductor memory 40 based on the fourth command C3a. As a result, the first data D1 can be relieved to an address that has not been normally written in the semiconductor memory 40 without giving information on the address to be relieved from the outside.

  As described above, when the third command C3 is input, if the writing is performed normally, the third command C3 can be ignored. Therefore, even when there are a plurality of commands, the test can be performed while relieving at the same time. It has become. Therefore, the reduction in test efficiency is suppressed and the product yield is improved.

(2)
Here, the input command decoder 10 cuts off the supply of the fourth command C3a to the command generator 30 when the write determination circuit 60 determines that the writing to the semiconductor memory 40 is normally performed. As a result, the first data D1 is not saved in vain with respect to the address at which data is normally written in the semiconductor memory 40.

(3)
Here, the transfer determination unit 27 of the input command decoder 10 determines whether or not the fourth command C3a should be transferred based on the result determined by the write determination circuit 60 and the fourth command C3a. As a result, when the write determination circuit 60 determines that the semiconductor memory 40 is not normally written, the fourth command C3a is supplied to the command generator 30, and the semiconductor memory 40 is normally written. If the write determination circuit 60 determines, the supply of the fourth command C3a to the command generator 30 is cut off.

(4)
Here, the transfer determination unit 27 of the input command decoder 10 determines whether or not the first data D1 and the second command C1a should be transferred based on the determination result of the write determination circuit 60 and the second command C1a. Further determine. Thereby, when the write determination circuit 60 determines that the writing to the semiconductor memory 40 is normally performed, the supply of the first data D1 and the second command C1a to the command generator 30 is cut off, and the semiconductor memory 40 is When the write determination circuit 60 determines that writing has not been performed normally, the first data D1 and the second command C1a are supplied to the command generator 30.

(5)
Here, when the write determination circuit 60 determines that the normal data storage area 41 is not normally written in the relief data storage area 43 of the semiconductor memory 40, the second command C1a and the second address information A2 are stored. Based on this, the first data D1 is written. The management information storage area 42 stores a second address as an area to be used when the write determination circuit 60 determines that the normal data storage area 41 is not normally written. As a result, the first data D1 is relieved.

Second Embodiment
FIG. 9 shows a configuration diagram of a semiconductor memory device according to the second embodiment of the present invention.

  The semiconductor memory device 100 has the same basic configuration as that of the first embodiment, but includes an input command decoder 110 instead of the input command decoder 10 and a command generator 130 instead of the command generator 30. The semiconductor memory 140 is provided instead of the semiconductor memory 40, and the write determination circuit 160 is provided instead of the write determination circuit 60, which is different from the first embodiment.

  That is, when the write determination circuit 160 determines that the writing to the semiconductor memory 140 has not been performed normally, the input command decoder receives information indicating that the NG flag is still OFF without turning off the FP flag. 110.

  The input command decoder 110 supplies the fourth command C3a to the command generator 130 when the write determination circuit 160 determines that the writing to the semiconductor memory 140 is not normally performed.

  At this time, the command generator 130 supplies the third address information A2, the second command C1a, and the first data D1 to the semiconductor memory 140 based on the fourth command C3a received from the input command decoder 110. The third address information A3 is information on the third address. The third address is an address in the relief data storage area, and is an address different from the first address and the second address. Further, the command generator 130 holds the third address information A3.

  The first data D1 is written in the semiconductor memory 140 based on the first command C1 and the third address information A3. In the semiconductor memory 140, the fourth data D4 is read based on the fifth command C5. Here, the fourth data D4 is data read from the third address in the semiconductor memory 140.

<Processing flow when the semiconductor memory device is inspected before shipping>
FIG. 10 and FIG. 11 show the flow of processing when the semiconductor memory device is inspected before shipping. The flow of processing when the semiconductor memory device is inspected before shipping is basically the same as that of the first embodiment, but differs from the first embodiment in the following points.

  In step S108 shown in FIG. 11 ((2) shown in FIG. 11), it is determined whether or not relief is possible. That is, the command generator 130 determines whether or not the second address exceeds the upper limit (for example, 1023) of the address of the repair data storage area based on the held second address information A2. Alternatively, based on the held third address information A3, it is determined whether or not the third address exceeds the upper limit (for example, 1023) of the address of the relief data storage area. If it is determined that the upper limit is not exceeded, it is determined that relief is possible and the process proceeds to step S109. If it is determined that the upper limit is exceeded, it is determined that relief is not possible and the process proceeds to step S14. .

  In step S109, the second address (third address) is counted up. That is, the command generator 130 generates a second address (third address) based on the fourth command C3a received from the input command decoder 110 and the second address information A2 (third address information A3) held therein. Count up. Then, the command generator 130 supplies the second address information A2, the second command C1a, and the first data D1 to the semiconductor memory 140. The second address information A2 is information on the second address. The second address is an address different from the first address. The command generator 130 holds the second address information A2 until the next fourth command C3a is supplied.

  In step S110, the first data is replaced from the normal data storage area to the relief data storage area. That is, the first data D1 is written in the relief data storage area in the semiconductor memory 140 based on the first command C1 and the second address information A2. In the semiconductor memory 140, the third data D3 (fourth data D4) is read based on the fifth command C5. Here, the third data D3 (fourth data D4) is data read from the second address (third address) in the semiconductor memory 140.

  In step S111, it is determined whether or not data has been normally written to the semiconductor memory. That is, the data latch 70 receives the first data D1 from the input command decoder 10. The data latch 70 temporarily stores the first data D1 and supplies the first data D1 to the write determination circuit 160 at a predetermined timing.

  The write determination circuit 160 receives the first data D1 from the data latch 70. The write determination circuit 160 supplies the fifth command C5 to the semiconductor memory 140 and receives the third data D3 from the semiconductor memory 140. Then, the write determination circuit 160 determines whether or not the data has been normally written in the semiconductor memory 140 (relief data storage area) based on the first data D1 and the third data D3. Specifically, the write determination circuit 160 compares the first data D1 and the third data D3 (fourth data D4), determines that the writing is performed normally if they are the same, and if they are different, It is determined that writing has not been performed normally. If it is determined that the writing has been normally performed, the process proceeds to step S12. If it is determined that the writing has not been normally performed, the process proceeds to step S108.

<Characteristics of semiconductor memory device>
If the third command C3 is input and the data is normally written, the third command C3 can be ignored. Therefore, even when there are a plurality of commands, the test can be performed while relieving at the same time. The point is the same as in the first embodiment. Therefore, even with such a semiconductor memory device 100, the reduction in test efficiency is suppressed, and the yield of products is improved.

  In addition, when the write determination circuit 160 determines that the writing is not normally performed, the first data D1 is written in the relief data storage area based on the fourth command C1a and the third address information A3. Further, in the management information storage area, when the write determination circuit 160 determines that writing has not been normally performed in the relief data storage area, the second address is stored as an unused area, and the third area is used as an used area. The address is stored. As a result, the first data D1 is further relieved with respect to the address where the writing is not normally performed in the semiconductor memory 140.

  The semiconductor memory device according to the present invention is effective as a semiconductor memory device and the like because it can suppress a reduction in test efficiency and can improve the yield of products.

1 is a configuration diagram of a semiconductor memory device according to a first embodiment of the present invention. The block diagram of the input command decoder in 1st Embodiment of this invention. The block diagram of the input command decoder in 1st Embodiment of this invention. The block diagram of the determination circuit in 1st Embodiment of this invention. The block diagram of the semiconductor memory in 1st Embodiment of this invention. The figure which shows the structure of management information. 6 is a flowchart showing a flow of processing when a semiconductor memory device is inspected before shipping. 6 is a flowchart showing a flow of processing when a semiconductor memory device is inspected before shipping. The block diagram of the semiconductor memory device concerning 2nd Embodiment of this invention. 6 is a flowchart showing a flow of processing when a semiconductor memory device is inspected before shipping. 6 is a flowchart showing a flow of processing when a semiconductor memory device is inspected before shipping.

Explanation of symbols

1,100 Semiconductor memory device 10, 110 Input command decoder 30, 130 Command generator 40, 140 Semiconductor memory 60, 160 Write determination circuit 70 Data latch

Claims (7)

First data, a first command that is a command for writing the first data, and first address information that is information of a first address that is an address to which the first data is written are input, and the first command A decoding circuit for generating a second command which is a decoded command;
A command generator for transferring the second command, the first data, and the first address information based on the second command received from the decoding circuit;
A storage circuit to which the first data is written based on the second command and the first address information received from the command generator;
A write determination circuit configured to determine whether or not data has been normally written to the storage circuit based on the first data and second data read from the first address in the storage circuit; ,
With
When the third command, which is a command for relieving the first data, is further input to the decode circuit and the write determination circuit determines that the write is not normally performed in the storage circuit, the third command is A fourth command, which is a decoded command, and the first address information are supplied to the command generator;
The command generator, based on the fourth command received from the decoding circuit, second address information that is second address information that is different from the first address, the second command, and the second command 1 data is supplied to the memory circuit,
Semiconductor memory device. The decoding circuit shuts off the supply of the fourth command to the command generator when the write determination circuit determines that the writing to the storage circuit is normally performed.
The semiconductor memory device according to claim 1. The decoding circuit includes:
A decoding unit that receives the third command and generates a fourth command that is a decoded command of the third command;
A transfer determination unit that determines whether or not to transfer the first data and the fourth command based on a result determined by the write determination circuit and the fourth command;
Having
The semiconductor memory device according to claim 1. The decoding unit of the decoding circuit further receives the first data and the first command, further generates the second command,
The transfer determination unit of the decode circuit further determines whether or not to transfer the first data and the second command based on a result determined by the write determination circuit and the second command;
The semiconductor memory device according to claim 3. The memory circuit is
A normal data storage area where normal writing is performed, and
A relief data storage area, which is an area where writing for relief is performed when writing to the normal data storage area is not normally performed;
A management information storage area in which management information, which is information for managing that writing for repairing has been performed, is written in the repair data storage area;
Have
The address group of the normal data storage area includes the first address,
The address group of the relief data storage area includes the second address;
The write determination circuit determines whether the normal data storage area has been normally written based on the first data and the second data,
In the relief data storage area, when the write determination circuit determines that the normal data storage area is not normally written, the first data is based on the second command and the second address information. Is written,
In the management information storage area, when the write determination circuit determines that the normal data storage area is not normally written, the second address is stored as an area to be used.
The semiconductor memory device according to claim 1. The write determination circuit normally writes in the relief data storage area based on the first data and the third data read from the second address in the relief data storage area. Further determine whether or not
The decoding circuit supplies the fourth command to the command generator;
The command generator, based on the fourth command, third address information which is information of a third address which is an address different from the first address and the second address, the second command, and the first command Data to the storage circuit,
In the management information storage area of the storage circuit, the second address is stored and used as an unused area when the write determination circuit determines that writing has not been normally performed in the relief data storage area. The third address is stored as an area to be
The semiconductor memory device according to claim 5. A method for controlling a semiconductor memory device having a memory circuit, comprising:
First input step in which first data, a first command that is a command for writing the first data, and first address information that is information on a first address that is an address to which the first data is written are input. When,
A decoding step in which a second command, which is a command obtained by decoding the first command, is generated;
A transfer step in which the second command, the first data, and the first address information are transferred based on the second command;
A first writing step in which the first data is written to the memory circuit based on the second command and the first address information;
A determination step of determining whether or not data has been normally written to the storage circuit based on the first data and second data that is data read from the first address in the storage circuit; ,
A second input step in which a third command which is a command for relieving the first data is input;
A supply step of supplying a fourth command, which is a command obtained by decoding the third command, and the first address information when it is determined in the determination step that the memory circuit is not normally written; When,
Based on the fourth command, second address information that is second address information that is different from the first address, the second command, and the first data are written to the storage circuit. A writing step;
With
A method for controlling a semiconductor memory device.

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