JP2007121571A - Display device and liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance a display quality by reducing the display unevenness that generates in a display device of a delta arrangement. <P>SOLUTION: The display device is delta arranged with pixels of three colors, first to third colors, in which the respective pixels are connected to source lines and gate lines and in which the source lines are sequentially selected and signal potentials are sequentially written into the pixels via the source lines. The arbitrary three pixels forming the delta are defined as first to third pixels, and the first to the third pixels are the pixels of the first to the third color. On assumption that the second to the third pixels exist in the same row, the first and the second pixels are connected to the same source line and are disposed on the same side with respect to the source line; in addition, the signal potentials corresponding to the first and the second colors are alternately sent for each horizontal period to the source line. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display device (for example, a liquid crystal display device) and a driving method thereof.

  First, display unevenness that occurs in a conventional liquid crystal display device will be described. FIG. 8 shows the configuration of a delta array active matrix display device (hereinafter referred to as a conventional display device) driven by a dot sequential three-point simultaneous sampling method. FIG. 9 shows operation timings and driving waveforms of each part of the conventional display device shown in FIG.

  As shown in FIG. 8, the conventional display device 100 includes a source driver 101, a gate driver 109, and a display unit 103, and the source driver 101 includes a sampling pulse generation circuit 102 and an analog switch group 105. Includes a gate line GL, a source line SL, and a pixel P. The pixel P (i, j) is the j-th pixel from the row end belonging to the i-th row, the gate line GLi is the i-th gate line, and the source line SLj is (from the left end) the j-th source line. To do. The pixel P has a thin film transistor TR and a pixel capacity connected to its drain (source). Hereinafter, the horizontal direction in the figure is the row direction, and the gate lines GL are arranged along this row direction.

  Here, the pixels P are arranged in a delta (triangular) arrangement, and the arrangement positions of the odd-numbered pixels P (odd number, j) and the even-numbered pixels P (even number, j) are shifted by half a pixel. For example, the center position of the pixel P (2,1) that is the first pixel from the row end of the second row is the center position of the pixel P (1,1) that is the first pixel from the row end of the first row. Is shifted to the left by a half of the width of one pixel in the row direction, and the center position and the row direction (left-right direction) of the pixel P (3, 1) which is the first pixel from the row end of the third row Agree on.

  The gate line GLi is connected to the gate of the thin film transistor TR included in each pixel P (i, j) in the i-th row. The source line SLj has a zigzag shape, and the source of the thin film transistor TR of the jth pixel P (odd number, j) from the left in the odd row and the j−1th pixel P (even number, j− from the left in the even row). It is connected to the source of the thin film transistor TR included in 1). Therefore, pixels connected to the same source line SL and located in adjacent rows are shifted from each other by one and a half pixels (1.5 pixels). The pixels P (odd number, j) in the odd rows are arranged on the right side (scanning direction side) of the source line SLj that supplies the signal potential to the pixels P (odd number, j).

  The analog switch group 105 includes a plurality of analog switches ASW arranged in the row direction. ASWj is the jth analog switch from the left end. The analog switches ASWj are grouped every three from the left end. In each group, j is a multiple of 3 that is an analog switch for B connected to the video signal line for B (blue), and the one before (left) of the analog switch for B is G ( A green analog switch connected to a video signal line for green), and an analog for R connected to the video signal line for R (red) one before (left) of the analog switch for G Switch. Further, the analog switch ASWj (jth analog switch from the left end) is connected to the source line SLj (jth source line from the end), and the source line SLj whose j is a multiple of 3 is for B (blue). The source line for B (left) is the G (green) source line, and the G source line (left) is the R source line.

  For example, analog switches ASW1 to ASW3 and ASW4 to ASW6 are grouped, respectively. In the group ASW1 to ASW3, ASW3 is an analog switch for B connected to a video signal line for B (blue), and the previous (left) of this ASW3 is a video signal line for G (green). An analog switch ASW2 for G to be connected, and an analog switch ASW1 for R connected to the video signal line for R (red) is the one before (left) of this ASW2. Similarly, in the group of ASW4 to ASW6, ASW6 is a B analog switch connected to a video signal line for B (blue), and the video signal for G (green) is the one before (left) of this ASW6. An analog switch ASW5 for G connected to the signal line, and an analog switch ASW4 for R connected to the video signal line for R (red) is the one before (left) of this ASW5. Further, the analog switch ASW1 is connected to the source line SL1, the analog switch ASW2 is connected to the source line SL2, and the analog switch ASW3 is connected to the source line SL3. The source line SL3 is for B, and the source line one before (left) SL2 is for G, and the previous (left) source line SL1 is for R. Similarly, the analog switch ASW4 is connected to the source line SL4, the analog switch ASW5 is connected to the source line SL5, and the analog switch ASW6 is connected to the source line SL6. The source line SL6 is for B, and the one before (left) source The line SL5 is for G, and the previous (left) source line SL4 is for R.

  In the point-sequential three-point simultaneous sampling method, each group is sequentially selected, and the three analog switches of the selected group are turned ON simultaneously. For example, the group of analog switches ASW1 to ASW3 is selected and the analog switches (ASW1 to ASW3) are simultaneously turned on, and then the group of analog switches ASW4 to ASW6 is selected and the analog switches (ASW4 to ASW6) are simultaneously turned on. The

  In the following, the driving waveform of each part of the conventional display device shown in FIG. 8 will be described with reference to FIG.

  The gate driver 109 sequentially outputs a gate selection (ON) signal to each gate line (GL1...) According to the driving clock. When a gate selection signal is output, a start pulse SPS pulse is input to the sampling pulse generation circuit 102, and sampling pulses Sam1, Sam2,... For sampling a video signal based on the control clock CKS are supplied to each group of analog switches. Output sequentially. As a result, the three analog switches of the group to which the sampling pulse Sam is input are simultaneously turned on by the ASW, and the video data (signal potential) of the video signal line connected to the turned-on analog switch ASW is the source line connected to the analog switch ASW. Output to SL.

  The operation during one horizontal period will be specifically described as follows. When the gate selection signal is output to GL1, the sampling pulse Sam1 is input to the group of analog switches ASW1 to ASW3, and the analog switches ASW1 to ASW3 are simultaneously turned on. As a result, R video data is output to the source line SL1 via ASW1, G video data is output to the source line SL2 via ASW2, and B video data is output to the source line SL3 via ASW3. The As a result, the R signal potential is written to the pixel capacitance of the pixel P (1,1), the G signal potential is written to the pixel capacitance of the pixel P (1,2), and the B signal potential is changed to the pixel P (1). , 3). Next, the sampling pulse Sam2 is input to the group of analog switches ASW4 to ASW6, and the analog switches ASW4 to ASW6 are simultaneously turned ON. As a result, the R video data is output to the source line SL4 via the ASW4, the G video data is output to the source line SL5 via the ASW5, and the B video data is output to the source line SL6 via the ASW6. The As a result, the R signal potential is written to the pixel capacitance of the pixel P (1, 4), the G signal potential is written to the pixel capacitance of the pixel P (1, 5), and the B signal potential is changed to the pixel P (1). , 6).

This is repeated to complete one horizontal period. In liquid crystal driving, 1H inversion driving is generally performed. That is, a signal potential whose polarity is inverted every 1H (horizontal period) is output to each source line SL, and the signal potential whose polarity is inverted is also applied to the source lines SL1 to SL6 during the period when the gate line GL2 is turned on. Is output.
Japanese Patent Laid-Open No. 3-21189 (released on January 29, 1991) JP-A-8-30241 (released February 2, 1996) JP 7-261706 (released on October 13, 1995) JP 10-74069 (published March 17, 1998)

  However, in the conventional display device, the pixels P (odd number, j) in the odd rows are arranged on the right side (scanning direction side) of the source line SLj that supplies the signal potential to the pixels P (odd number, j). Become. Therefore, a parasitic capacitance Csd is generated between the pixel P (odd number, j) and the adjacent source line SL (j + 1). As shown in FIG. 10, the parasitic capacitance Csd includes the pixel electrode (the drain of the thin film transistor TR) of the pixel P (odd number, j) and the pixel P (odd number, j + 1) adjacent to the right side (pixel adjacent to the scanning direction side). And a source line SL (j + 1) for supplying a signal potential to the signal line.

  This parasitic capacitance Csd gives a potential variation to the pixel electrode of the pixel P (odd number, multiple of 3) in the point-sequential three-point simultaneous sampling method in which three source lines SL are selected three by one (see FIG. 9). For example, in the pixel P (1, 3), the potential of the source line SL4 is inverted while the signal potential is being written to the pixel electrode. This is because the source line SL4 is given a signal potential that is inverted with respect to the signal potential given one horizontal period before. As a result, the pixel electrode of the pixel P (1, 3) receives a potential fluctuation through the parasitic capacitance Csd, and the potential waveform jumps during writing (charging) as shown in FIG. This potential fluctuation amount is expressed by (Csd / Cpix) × ΔV where Cpix is the total pixel capacity of the pixel pixel P (1,3) and ΔV is the potential change amount of the source line SL4. Note that the pixel electrode of the pixel P (1,3) once subjected to the potential fluctuation is recharged to the signal potential to be originally charged through the source line SL3 until the gate line GL1 is turned off.

  Here, in the case of dot sequential driving, during the writing period to each pixel P (pixel electrode), the source line SL connected to the thin film transistor TR of the pixel P is selected (the analog switch ASW connected to the source line SL is turned on). ) Until the gate line GL connected to the thin film transistor TR of the pixel P is turned off. Accordingly, the writing time is shorter for the pixels P arranged on the scanning direction side (right side).

  As a result, among the pixels P (odd number, multiples of 3), particularly those arranged on the scanning direction side (right side), the gate line GL1 is turned off before recharging (rewriting) is sufficiently performed. A phenomenon occurs in which the signal potential that should be charged is not obtained (see FIG. 9).

  As described above, in the conventional liquid crystal display device, in the dot-sequential three-point simultaneous sampling method, display unevenness occurs in the pixel P (odd number, multiple of 3), that is, the pixel (B pixel) located at the sampling block boundary of the odd row. In addition, there is a problem that the unevenness of display is deeper as the display unevenness is arranged on the scanning direction side (right side).

  The present invention has been made in view of the above problems, and an object of the present invention is to suppress display unevenness occurring in a delta arrangement display device and to improve display quality.

    In order to solve the above-described problem, the infrared communication device of the present invention has pixels of the first to third colors in a delta arrangement and each pixel is connected to a source line and a gate line. Are sequentially selected, and a signal potential is written to the pixels through the selected source line, and any three pixels forming the delta are defined as first to third pixels, The three pixels are pixels of the first to third colors, and the second and third pixels are located in the same row, and the first and second pixels are connected to the same source line. The signal lines are arranged on the same side with respect to the source line, and signal potentials corresponding to the first and second colors are alternately sent to the source line every horizontal period.

  The above configuration connects two pixels belonging to different rows among arbitrary three pixels forming a delta to the same source line (that is, pixels connected to the same source line and located in adjacent rows are connected to each other). By shifting the pixels by half a pixel from each other, the pixels arranged in the delta arrangement are arranged on the same side of the source line connected to each pixel. Therefore, if each pixel is arranged on the opposite side of the selection (scanning) direction of the source line connected to each pixel, the source line connected to each pixel (pixel electrode included in each pixel) and the adjacent pixel on the selection direction side. It is possible to prevent parasitic capacitance from being formed between the two. Thereby, display unevenness due to the parasitic capacitance can be suppressed and display quality can be improved.

  The above-described configuration may be a configuration in which three source lines are selected. By so doing, it is possible to eliminate display unevenness (display unevenness at the sampling block boundary of odd rows) that has occurred when the conventional display device adopts the three-point simultaneous sampling method.

In the above configuration, one end of the source line to which the first and second pixels are connected is connected to the first color video signal line via the first analog switch, and the other end is connected. Is connected to the video signal line for the second color through the second analog switch,
The first and second analog switches may be driven alternately every horizontal period.

In the above configuration, the source line to which the first and second pixels are connected is connected to the first color video signal line and the second color video signal line through an analog switch.
The analog switch may be configured such that the first color video signal line and the second color video signal line are alternately connected to the source line every horizontal period.

  In the above configuration, the source line to which the first and second pixels are connected is connected to one video signal line via an analog switch, and the signal potential output from the video signal line is in one horizontal period. Alternatively, the first color or the second color may be switched.

  In the above configuration, each pixel and the driver for driving each line may be monolithically formed.

  The liquid crystal display device of the present invention includes the above display device.

  As described above, according to the display device of the present invention, each pixel can be arranged on the side opposite to the selection (scanning) direction of the source line connected to each pixel, and each pixel (pixel electrode included in each pixel); It is possible to prevent a parasitic capacitance from being formed between source lines connected to pixels adjacent to the selection direction. Thereby, display unevenness due to the parasitic capacitance can be suppressed, and a display device with high display quality can be realized.

  An embodiment of the present invention will be described as follows. FIG. 1 is a schematic diagram illustrating a display unit of a display device (for example, a liquid crystal display device) according to this embodiment. As shown in the figure, in the display unit 3 of the display device 1, pixels P of three colors R (red), G (green), and B (blue) are arranged in a delta arrangement. Here, assuming that i and j are natural numbers, the j-th pixel p (i, j) from the end of the i-th row has a thin film transistor Tr and a pixel electrode connected to its drain (source). The gate is connected to the gate line gL, the drain is connected to the pixel electrode, and the source is connected to the source line sL. Hereinafter, the row direction (the direction along the gate line gL) is the left-right direction, and particularly the right direction is the scanning (selection) direction.

  Specifically, the pixel p (even number, j) in the even-numbered row is shifted to the right by half a pixel as compared with the pixel p (odd-number, j) in the even-numbered row. For example, the center position of the pixel p (2,1) which is the first pixel from the row end of the second row is the center position of the pixel p (1,1) which is the first pixel from the row end of the first row. Is shifted to the right by half the width of one pixel in the row direction, and the center position and the row direction (left-right direction) of the pixel p (3, 1), which is the first pixel from the row end of the third row. Agree on. The gate line gLi (i-th gate line) is connected to the gate of the thin film transistor Tr included in the i-th pixel p (i, j). The source line sLj (jth source line from the left) is the jth pixel P (odd number, j) from the left in the odd-numbered row and the j−1th pixel P (even number, j−1 from the left in the even-numbered row). ) Are zigzag so as to pass through the right side of (), and are connected to the source of the thin film transistor Tr of the pixel P (odd number, j) and the source of the thin film transistor Tr of the pixel P (even number, j−1).

  From the above, in the display unit 3, as shown in FIG. 1, any three pixels forming deltas (pixels having different colors) are represented by p (i, j), p (i + 1, j−1). And p (i + 1, j) (i is an odd number in this case), the pixel p (i, j) and the pixel p (i + 1, j-1) are connected to the same source line sLj, and the source line Arranged on the left side of sLj (opposite to the scanning direction). Also, arbitrary three pixels forming deltas (pixels having different colors) are designated as p (i, j), p (i + 1, j) and p (i + 1, j + 1) (in this case, i is an even number) ), The pixel p (i, j) and the pixel p (i + 1, j + 1) are connected to the same source line sL (j + 1), and the left side of the source line sL (j + 1) (opposite side in the scanning direction) Arranged.

  For example, the source line sL2 includes the G pixel p (1,2), the B pixel p (2,1), the G pixel p (3,2), the B pixel p (4,1), and the G pixel. p (5,2)... and passes to the right of these pixels. Signal potentials corresponding to G and B are alternately sent to the source line sL2 every horizontal period (scanning of one gate line). Similarly, the source line sL3 includes the B pixel p (1,3), the R pixel p (2,2), the B pixel p (3,3), the R pixel p (4,2), and the B pixel. .. Are connected to the pixels p (5, 3)... Signal potentials corresponding to B and R are alternately sent to the source line sL3 every horizontal period (scanning of one gate line). Similarly, the source line sL4 includes the R pixel p (1,4), the G pixel p (2,3), the R pixel p (3,4), the G pixel p (4,3), and the R pixel. Are connected to the pixels p (5, 4)... And pass through the right side of these pixels. Signal potentials corresponding to R and G are alternately sent to the source line sL4 every horizontal period (scanning of one gate line).

  Thus, in the display unit of the present display device, the plurality of pixels p connected to all the source lines sL are all arranged on the left side (opposite side in the scanning direction) of the source lines sL. Therefore, if one or a plurality of source lines sL are sequentially selected in the right direction (scanning direction), the pixel electrode (the drain of the thin film transistor TR) of the pixel p (i, j) and the pixel p adjacent to the right side thereof. Parasitic capacitance (parasitic capacitance such as Csd in FIG. 10) does not occur between the source line sL that supplies a signal potential to (i, j + 1) (pixel adjacent in the scanning direction).

  Therefore, even when the inversion driving is performed for one horizontal period using the dot-sequential three-point simultaneous sampling method in which three source lines sL are selected, unlike the conventional display device, the pixel p ( The potential variation does not occur in the pixel electrodes of (multiple of i, 3). Thereby, a high-quality display without display unevenness is realized.

  A configuration example for sending signal potentials corresponding to two colors to the same source line sL will be described below.

  In the first configuration example, as shown in FIG. 2, in order to switch the corresponding color of the signal potential output to each source line sL every horizontal period, the two source drivers 10a and 10b are arranged above and below across the display unit 3. Is provided. Here, one end of each source line sL is connected to the video signal line of the first color via the analog switch ASw in the source driver 10a, and the other end is connected via the analog switch ASw in the source driver 10b. Connected to the video signal line of the second color.

  The analog switch ASw in the source driver 10a is arranged in the row direction, and the jth analog switch ASwj from the left end is connected to the upper end of the source line sLj. The analog switches ASwj (j = 1, 2,...) Are grouped every three from the left end, and are simultaneously selected by a sampling pulse. In each group, j is a multiple of 3 that is an analog switch for B connected to the video signal line for B (blue), and the one before (left) of the analog switch for B is G ( A green analog switch connected to a video signal line for green), and an analog for R connected to the video signal line for R (red) one before (left) of the analog switch for G Switch.

  The analog switch Asw in the source driver 10b is also arranged in the row direction, and the jth analog switch Aswj from the end is connected to the lower end of the source line sLj. Analog switches Aswj (j = 1, 2,...) Are grouped every three from the left end, and are simultaneously selected by a sampling pulse. In each group, one in which j is a multiple of 3 is a G analog switch connected to a video signal line for G (green), and the one before (left) of the G analog switch is R ( An analog switch for R connected to a video signal line for red), and an analog for B connected to the video signal line for B (blue) one before (left) of the analog switch for R Switch.

  The gate driver 9 sequentially outputs a gate selection (ON) signal to each gate line (gL1, gL2,...). When the gate selection signal is output to the odd-numbered gate line gL, the SPSe signal is input to the sampling pulse generation circuit 7a. Thus, the sampling pulse generation circuit 7a sequentially outputs sampling pulses (Sam1e, Sam2e...) For sampling the video signal (signal potential) based on the input control clock CKS to each group of the analog switches ASw. As a result, the three analog switches ASw of the group to which the sampling pulse is input are simultaneously turned ON, and the video data (signal potential) of the video signal line connected to the analog switch ASw turned ON is the source line sL connected to the analog switch ASw. Is output. On the other hand, when the gate selection signal is output to the even-numbered gate line gL, the SPSo signal is input to the sampling pulse generation circuit 7b. Thus, the sampling pulse generation circuit 7b sequentially outputs sampling pulses (Sam1o, Sam2o...) For sampling the video signal (signal potential) based on the input control clock CKS to each group of the analog switches Asw. As a result, the three analog switches Asw of the group to which the sampling pulse is input are simultaneously turned ON, and the video data (signal potential) of the video signal line connected to the analog switch Asw turned ON is the source line sL connected to the analog switch Asw. Is output.

  The operation in the two horizontal periods will be described as follows using the timing charts of FIGS.

  When the gate selection signal is output to the gate line gL1, the SPSe becomes “High”. As a result, the sampling pulse Sam1e (High) is input to the group of analog switches ASw1 to ASw3, and the analog switches ASw1 to ASw3 are simultaneously turned on. As a result, the R video data is output to the source line sL1 via ASw1, the G video data is output to the source line sL2 via ASw2, and the B video data is output to the source line sL3 via ASw3. The As a result, the R signal potential is written to the pixel capacitance of the pixel p (1, 1), the G signal potential is written to the pixel capacitance of the pixel p (1, 2), and the B signal potential is changed to the pixel p (1). , 3).

  Next, the sampling pulse Sam2e (High) is input to the group of analog switches ASw4 to ASw6, and the analog switches ASw4 to ASw6 are simultaneously turned on. As a result, the R video data is output to the source line sL4 via ASw4, the G video data is output to the source line sL5 via ASw5, and the B video data is output to the source line sL6 via ASw6. The As a result, the R signal potential is written to the pixel capacitance of the pixel p (1, 4), the G signal potential is written to the pixel capacitance of the pixel p (1, 5), and the B signal potential is changed to the pixel p (1). , 6).

  The above steps are repeated to complete one horizontal period (scanning of the gate line gL1).

  Next, when the gate selection signal is output to the gate line gL2, the SPSo becomes “High”. As a result, the sampling pulse Sam1o (High) is input to the group of analog switches Asw1 to Asw3, and the analog switches Asw1 to Asw3 are simultaneously turned on. As a result, the G video data is output to the source line sL1 via Asw1, the B video data is output to the source line sL2 via Asw2, and the R video data is output to the source line sL3 via Asw3. The As a result, the B signal potential is written into the pixel capacitance of the pixel p (2, 1), and the R signal potential is written into the pixel capacitance of the pixel p (2, 2).

  Next, the sampling pulse Sam2o (High) is input to the group of analog switches Asw4 to Asw6, and the analog switches Asw4 to Asw6 are simultaneously turned on. As a result, the G video data is output to the source line sL4 via Asw4, the B video data is output to the source line sL5 via Asw5, and the R video data is output to the source line sL6 via Asw6. The As a result, the G signal potential is written to the pixel capacitance of the pixel p (2, 3), the B signal potential is written to the pixel capacitance of the pixel p (2, 4), and the R signal potential is changed to the pixel p (2). , 5).

  The above steps are repeated to complete one horizontal period (scanning of the gate line gL2).

  In the second configuration example, as shown in the timing charts of FIGS. 3 and 7, the signal output control signal o / e and the SPS1 signal are input to the sampling pulse generation circuit 7a and the sampling pulse generation circuit 7b, and the signal output control is performed. When both the signal o / e and the SPS1 signal become “High”, a sampling pulse (Sam1e, Sam2e...) Is input to each group of the analog switch ASw of the source driver 10a, and the signal output control signal o / e is “ If the SPS1 signal becomes “High” at “Low”, the configuration may be such that sampling pulses (Sam1o, Sam2o...) Are input to the group of analog switches Asw of the source driver 10b.

  Further, in the third configuration example, as shown in FIG. 4, an analog switch A-SW connected to two (two colors) video signal lines and an o / e signal line is provided in the source driver 10c. Each analog switch A-SW is connected to each source line sL.

  More specifically, the analog switch A-SW is arranged in the row direction, and the jth analog switch A-SWj from the end is connected to the source line sLj. Analog switches A-SWj (j = 1, 2,...) Are grouped every three from the left end, and are simultaneously selected by a sampling pulse. In each group, a multiple of 3 is a B / R switching analog switch connected to the B and R video signal lines, and is one before the B / R switching analog switch ( The left) is an analog switch for G / B switching connected to the video signal lines for G and B, and the one before (left) of the analog switch for G / B switching is a video signal for R and G. This is an analog switch for R / G switching connected to a line.

  Here, the B / R switching analog switch selects the video signal line for B when the o / e signal is “High”, and the R / R switching analog signal switch when the signal is “Low”. When the o / e signal is “High”, the video signal line for G is selected when the signal is “Low”. When the o / e signal is “High”, the analog signal for switching B is selected. If it is “Low”, the video signal line for G is selected. Since the o / e signal is switched between “High” and “Low” every horizontal period (see FIG. 7), the signal potentials of two colors can be alternately sent to each source line sL every horizontal period. It becomes.

  In the fourth configuration example, as shown in FIG. 5, a video signal switching circuit 11 connected to three (three colors) video signal lines and an o / e signal line is provided. Note that the video signal switching circuit 11 may be provided in the source driver 10d. When the o / e signal is “High”, the video signal switching circuit 11 connects the switching line L1 and the R video signal line, connects the switching line L2 and the G video signal line, and switches the switching line. L3 and the video signal line for B are connected. On the other hand, if the o / e signal is “Low”, the switching line L1 and the video signal line for G are connected, the switching line L2 and the video signal line for B are connected, and the switching lines L3 and R are connected. Connect the video signal line. The source driver 10d is provided with an analog switch A-sw, and the switching lines L1 to L3 are connected to the source lines sL via the analog switches A-sw.

  More specifically, the analog switch A-sw is arranged in the row direction, and the jth analog switch A-swj from the end is connected to the source line sLj. Analog switches A-swj (j = 1, 2,...) Are grouped every three from the left end and are simultaneously selected by a sampling pulse. In each group, an analog switch A-swj in which j is a multiple of 3 is connected to the switching line L3, and the previous (left) analog switch is connected to the switching line L2, and the previous (left) analog switch is connected. An analog switch is connected to the switching line L1.

  Thereby, for example, if the o / e signal is “High”, the source lines sL1 to sL3 are connected to the R, G, and B video signal lines via the switching lines L1 to L3, respectively. On the other hand, if the o / e signal is “Low”, the source lines sL1 to sL3 are connected to the video signal lines for G, B, and R via the switching lines L1 to L3, respectively. Since the o / e signal is switched between “High” and “Low” every horizontal period (see FIG. 7), the signal potentials of two colors can be alternately sent to each source line sL every horizontal period. It becomes.

  It should be noted that the present invention is not limited to the above-described embodiment, and various modifications are possible within the scope shown in the claims, and an implementation obtained by appropriately combining technical means disclosed in the embodiment. The form is also included in the technical scope of the present invention.

  The display device according to the present invention is applicable to, for example, a liquid crystal display panel (particularly for AV).

It is a circuit diagram which shows the structure of the display part of this display apparatus. It is a circuit diagram which shows the example of 1 structure of this display apparatus. It is a circuit diagram which shows the other structural example of this display apparatus. It is a circuit diagram which shows the other structural example of this display apparatus. It is a circuit diagram which shows the other structural example of this display apparatus. 3 is a timing chart showing the operation of the display device of FIG. 4 is a timing chart showing the operation of the display device of FIG. 3. It is a circuit diagram which shows the structure of the conventional display apparatus. FIG. 9 is a schematic diagram for explaining the operation of the display device of FIG. 8 and the influence (potential fluctuation) of parasitic capacitance. FIG. 9 is a circuit diagram illustrating parasitic capacitance formed in the display device of FIG. 8.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Display apparatus 3 Display part 7 7a 7b Sampling pulse generation circuit 9 Gate driver 10 10a 10b Source driver 11 Video signal switching circuit p Pixel sL Source line gL Gate line ASw Asw A-SW A-sw Analog switch Csd Parasitic capacitance L1-L3 Switching line

Claims (7)

The pixels of the first to third colors are arranged in a delta arrangement and each pixel is connected to a source line and a gate line, and signals are sent to the pixels via the selected source line while sequentially selecting the source lines. A display device for writing a potential,
Arbitrary three pixels forming a delta are first to third pixels, the first to third pixels are pixels of first to third colors, respectively, and the second and third pixels are in the same row. As located in
The first and second pixels are connected to the same source line and arranged on the same side with respect to the source line, and the signal potential corresponding to the first and second colors is applied to the source line for one horizontal period. A display device that is alternately sent to each other.   2. The display device according to claim 1, wherein three source lines are selected. One end of the source line to which the first and second pixels are connected is connected to the first color video signal line through the first analog switch, and the other end is connected to the second analog line. It is connected to the video signal line for the second color through a switch,
2. The display device according to claim 1, wherein the first and second analog switches are alternately driven every horizontal period. The source line to which the first and second pixels are connected is connected to the first color video signal line and the second color video signal line via an analog switch,
2. The display device according to claim 1, wherein the first color video signal line and the second color video signal line are alternately connected to the source line every horizontal period by the analog switch. The source line to which the first and second pixels are connected is connected to one video signal line through an analog switch,
2. The display device according to claim 1, wherein the signal potential output from the video signal line is switched to the first color or the second color every horizontal period.   2. The display device according to claim 1, wherein each pixel and a driver for driving each line are formed monolithically.   A liquid crystal display device comprising the display device according to claim 1.

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