JP2007116664A - Voltage and current supply with compensation for power supply variation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus and method for providing a power supply with a compensated voltage or current. <P>SOLUTION: A supply compensated current and voltage source utilizes a differential amplifier 106 connected to a band-gap reference voltage and a scaled power supply voltage. When power supply varies, the differential amplifier regulates a stable compensated output. The output may be a compensated voltage or current. In addition, multiple currents and voltages may be referenced from the differential amplifier. The stable compensated output may be supplied as a reference bias for external circuitry. In addition, the compensated output may be supplied to a voltage controlled oscillator. The supply compensated voltage and current source includes: a first resistor connected in series with a second resistor via a reference node 122 wherein a power supply voltage is applied to a series circuit 102 comprising the first and the second resistors; a voltage reference power source 104; and a differential amplifier with first and second voltage inputs and a compensation output wherein the first input is connected to the reference node, and the second input is connected to the voltage reference power source. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

Government Rights The Government of the United States has obtained certain rights to the present invention under contract number DTRAO1-03-D-0018 and delivery number DTRA01-03-D-0018-0001 awarded by the Defense Threat Reduction Agency.

  The present invention relates generally to current and voltage sources, and more particularly to a voltage controlled oscillator that is stable with respect to power supply variations.

  Phase locked loops (“PLLs”) have been widely used in analog electrical systems and communication systems. In today's high performance systems operating within increasingly stringent timing constraints, PLLs are being introduced into more common digital electronic circuits. For example, application specific integrated circuits (“ASICs”) used in various circuit applications typically include an on-chip PLL for clock signal distribution.

  The main advantages that PLLs bring to clock distribution are phase / delay compensation, frequency multiplication, and duty cycle correction. The PLL allows one periodic signal or clock to be phase matched to a multiple of the reference clock frequency. The output of the PLL, as its name implies, locks to the received reference clock signal and generates a periodic signal having a frequency equal to the average frequency of the reference clock. If the output PLL signal tracks the reference signal, the PLL is said to be “locked”.

  However, the PLL only remains locked over a limited frequency range or shifts within a frequency called the hold-in range or lock range. The PLL generally tracks the reference signal over the lock range when the reference frequency changes gradually. This maximum “lock sweep rate” is the maximum rate of change of the reference frequency at which the PLL remains locked. If the frequency change is faster than this speed, the PLL is out of lock.

  Other factors can cause loss of locks that can occur unexpectedly and suddenly. For example, a deviation in the output frequency of the PLL may occur due to power supply voltage fluctuation. The PLL may be out of lock due to deviations in the output frequency. One example of a power supply fluctuation that can cause the PLL to go out of lock is an increased load on the power supply. The increased load may be introduced by an increased number of circuit components sharing the power source.

  Power supply fluctuations can also create other disturbances such as fluctuations in the output frequency itself. Although the PLL may still remain “locked”, the variable output frequency can refer to the PLL output and cause instability in the circuit.

  One source of power fluctuation is the voltage received by the voltage controlled oscillator (VCO) in the PLL. The function of the VCO is to generate a PLL periodic output signal. When the reference clock is tracked by the PLL, the phase detector, along with other components, generates a voltage (or current) that represents the phase difference between the reference clock and the output of the PLL. Basically, the VCO receives the generated voltage (or current) and converts it into a periodic output signal. For example, a high output voltage may be converted into an output signal having a high frequency. On the other hand, the low input voltage may be converted into an output signal having a low frequency.

  However, if the power supply fluctuates, the VCO may convert the input voltage into various periodic signals. That is, the periodic signal varies as the power source varies. As a result, detrimental circuit errors can occur due to PLL output deviations or loss of locks within the PLL. Accordingly, there is a need for a power supply compensation voltage and current source for a voltage controlled oscillator.

  An apparatus and method for providing a power supply compensation voltage and current source is provided.

  In one embodiment, the compensation voltage and current source comprises a differential amplifier that receives a bandgap reference voltage and a scaled power supply voltage as inputs. The differential amplifier also includes a current source driven by a threshold reference circuit. Even when the power supply is changed, a stable compensation current output is maintained by the differential amplifier. The compensation current is then supplied to an external circuit such as a VCO bias generator. In that case, the VCO bias generator may output a signal to the waveform generator to generate a supply compensation output.

  In other embodiments, the compensation voltage is generated by a differential amplifier. The compensation voltage may be used by an external circuit such as a VCO bias generator.

  These and other aspects and advantages will become apparent to those of ordinary skill in the art by reading the following detailed description, with reference where appropriate to the accompanying drawings. Further, it is understood that this summary is merely an example and is not intended to limit the scope of the claimed invention.

  Preferred embodiments herein are described below with reference to the accompanying drawings, wherein like reference numerals refer to like elements in the various figures.

  A power supply compensation voltage and current source are provided. The compensation voltage and current source may be used to supply voltage or current, or both, to an external circuit such as a voltage controlled oscillator (VCO). A stable PLL output can be generated using a compensation voltage and a VCO that is supplied with voltage or current by a current source. Other circuits that benefit from the benefits of power supply variation compensation can also benefit from embodiments of the present invention.

  Returning now to FIG. 1, the basic PLL 10 may comprise a phase frequency detector 12, a charge pump 14, a loop (low-pass) filter 16, a VCO 18, and a lock detector 30. The phase frequency detector 12 receives a reference clock 20 and a derived (or feedback) clock 22. The output of the phase frequency detector 12 is supplied to the charge pump 14. The output from the charge pump 14 is supplied to the low pass filter 16. The low pass filter 16 is connected to the VCO 18. The output of the VCO 18 is supplied to the frequency divider 28. The output of the frequency divider 28 is returned to the phase frequency detector 12 and supplied to a normal lock detector 30. The lock detector 30 is also provided with a reference clock 20 so that a normal lock detector signal 32 can be provided.

  In operation, the phase detector 12 compares the two output frequencies and generates an output that is the magnitude of their phase difference. For example, the phase frequency detector compares the input reference clock signal 20 (REFCLK) with the feedback clock signal 22 (FBKCLK) and generates an error signal 24 that is proportional to the magnitude of the phase / frequency difference between the two signals 20, 22. To do. In the figure, the output signal 24 of the phase detector 12 is shown as an up or down pulse 24 that is generally input to a counter (not shown) that acts as a loop filter 16 driving the VCO 18. In other embodiments, the phase detector 12 may output an n-bit phase error 24 that may be output to a standard digital filter.

  The error signal 24 is supplied to the charge pump 14 in order to reduce the loading of the phase detector 12 on the PLL circuit. The charge pump 14 current controls the amount of charge stored in the loop filter 16, thereby converting the output from the phase frequency detector 12 to a control voltage input 26 to the VCO 18. The VCO 18 generates an output frequency that is proportional to the control voltage 26.

  When the PLL 10 is locked, there is a constant phase difference (usually zero) between the REFCLK20 signal and the FBKCLK22 signal, and their frequencies match. If the two signals are equal, there is no magnitude output 24 from the phase detector 12. If the signals are different, the phase detector 12 outputs a corresponding voltage signal 24. In operation, phase detector 12 compares REFCLK 20 to the oscillator output (via frequency divider 28) and generates a periodic feedback clock output FBKCLK 22 that tracks REFCLK 20. When the frequency of FBKCLK 22 from the oscillator is delayed from that of REFCLK 20, the phase detector 12 causes the charge pump 14 to change the control voltage so that the speed of the oscillator 18 increases. Similarly, when FBKCLK 22 precedes REFCLK 20, the phase detector 12 causes the charge pump 14 to change the control voltage so as to reduce the speed of the oscillator 18. Since the low pass filter 16 smooths the sudden control input from the charge pump 14, the system tends to be in a state where the phase detector 12 performs little correction. As a result, the PLL output 34 is stable and can be used in various integrated circuit applications. One such application may be a clock generation circuit.

  However, there are many situations in which the PLL 10 cannot generate a stable output 34. The lock detector 30 indicates when a stable output is or is not output by measuring the REFCLK20 signal and the FBKCLK22 signal. If there is no stable output, the lock detector 30 generates a signal 32 corresponding to an unmet “lock” condition.

  As discussed above, one such situation that may result in an unfulfilled lock condition may be a variation in the current or voltage used to generate the VCO output. Specifically, small changes in the voltage and current used for amplification can cause large fluctuations in the VCO output. Unfortunately, small changes in voltage and current can occur when the power supply voltage fluctuates. As a result, slight variations in the reference current or voltage can cause the VCO 18 output (and in turn the PLL output 34) to be too fast or too slow compared to REFCLK20. This can make the PLL out of “lock”.

  Even if the lock condition is met, an increase or decrease in the PLL output frequency 34 can cause deleterious effects. One such effect is an increase in the frequency of the clock circuit in the ASIC that utilizes the PLL 10. The increase in frequency can cause other circuits in the ASIC to cycle at an undesirable rate. This undesirable cycle rate can cause synchronization errors between circuit components in the ASIC. Since power supply fluctuations can be intermittent or unexpected, it is important to provide a stable current and voltage to the VCO during power supply fluctuations.

  A VCO 36 for preventing instability of the VCO power supply is shown in FIG. VCO 36 includes a voltage / current source 38, a VCO bias generator 40 and a VCO waveform generator 42. Inputs to the VCO 36 are differential voltage controls 26a, 26b. In this embodiment, the differential voltage controls 26a, 26b are differential signals. However, this signal may be single-ended (voltage control 26) as shown in FIG. The output from the VCO 36 is a PLL output 34.

Within the VCO 36, the VCO bias generator 40 is supplied with a compensation current 44 ("ICOMP") output from a voltage / current source 38 (V / C source). V / C source 38 is further illustrated in FIG. In other embodiments, the V / C source 38 can output a voltage signal. Alternatively, in other embodiments, the V / C source 38 can output both current and voltage outputs. Regardless of the type of output signal, the V / C source 38 receives the bandgap voltage V _BG 45 and the power supply receives V _p and V _n , 46, 48.

  When VCO bias generator 40 receives ICOMP 44 and differential voltage controls 26a and 26b, VCO bias generator 40 outputs reference currents 50a to 50d ("IREF"). The IREFs 50a-d are supplied to a VCO waveform generator 42 that outputs a PLL output 34.

  Returning now to FIG. 3a, the waveform generator 42 includes delay cells 54a-d and a full swing-single-ended conversion 56 ("F / S"). Delay cells 54a-d receive IREFs 50a-d, respectively. Delay cells 54a-d also receive a differential input signal and output an amplified differential output. The differential output of the delay cell 54d is returned to the delay cell 54a and also input to the F / S 56. The F / S 56 converts the full swing differential signal into a single-ended, logic level, PLL output 34. If a full swing signal is desired for the PLL output 34, the F / S 56 may be omitted. Furthermore, more or fewer delay cells may be used in other embodiments. The frequency, stability, and power consumption of the VCO 36 will vary depending on the number of delay cells used. The effect of adding or reducing delay cells is discussed in detail in FIG. 3b.

A circuit diagram representing an individual delay cell 54a is shown in FIG. 3b. The nature and structure of the delay cells 54a-d are all the same as the circuit diagram of the delay cell 54a. The IREF 50a and the differential inputs V _{IN +} and V _IN− , 58a, 58b are input to the delay cell 54a. Outputs from the delay cell 54a are differential outputs V _{OUT +} and V _OUT− , 60a, 60b. In the delay cell 54a, the IREF 50a is supplied to the PMOS transistor 62. The PMOS transistor 62 is biased at its gate as determined by the voltage divider 64, the power supply voltage of the NMOS transistors 66 and 68, and the gate voltage of the NMOS transistor 70. The NMOS transistor 70 is used as a current source in the differential amplifier 72. In this embodiment, the differential amplifier includes active loads from PMOS transistors 74a, 74b and 76a, 76b. The output of the PMOS transistor 78 is connected to the gates of the active load PMOS transistors 74a and 76a.

  In operation, IREF 50a determines the bias of transistors 66, 68 and 70. The higher the current value of IREF 50a, the higher the gate-source bias on transistors 66, 68 and 70. When reducing the current value of the IREF 50a, an inverse correlation exists. As the gate-source bias of transistor 70 increases, more current is supplied to the end of differential amplifier 72.

When a differential voltage is applied to the differential amplifier, the signals applied at V _{IN +} and V _IN− , 58a, 58b are amplified and inverted at V _{OUT +} and V _OUT− , 60a, 60b. This is an equation,
(V _{OUT +} −V _OUT− ) = Av (V _{IN +} −V _IN− )
It is represented by The amplification transition time, that is, the delay time (“τ”) is proportional to the amount of current applied to the end of the differential amplifier 72. In essence, the more current supplied to the differential amplifier 72, the longer the latching time in the differential amplifier 72. Therefore, when the current through transistor 70 increases, delay time τ becomes longer. Also, if the current through transistor 70 decreases, it becomes easier for the differential amplifier to reverse and the delay time τ becomes shorter. Since transistor 70 is directly affected by IREF 50a, changing IREF 50a provides direct control of delay time τ.

  The delay time τ is also adjusted by transistor 78. Transistor 78, along with resistor 79, is used to bias transistors 74a, 76a. The function of transistors 78, 74a and 76a is to compensate for the delay times of active loads 74a, 74b and 76a, 76b. Basically, transistors 74a and 76a are turned on early before a "high" to "low" or "low" to "high" transition occurs. The additional current supplied by these transistors reduces the delay time τ by reducing the amount of time it takes the active load to transition. Since IREF 50a directly controls the amount of current through transistor 66, changing IREF 50a also affects delay time τ by adjusting the active load of differential amplifier 72.

  In the above embodiment of FIG. 3a, the feedback loop of delay cells 54a-d ultimately produces a steady state waveform. Initially, small perturbations in the differential input are then amplified until the amplification threshold is reached. The inverted differential outputs of the delay cells 54a and 54d generate an oscillation waveform having a leading edge that is delayed by the delay time τ in each individual delay cell. The leading edge cycles through delay cells 54a, 54d twice before returning to its original voltage level. Therefore, the entire frequency of the VCO 36 is calculated as follows.

f = 1 / (2Nτ)
Where N is the number of delay cells. As discussed above, fewer delay cells may be used, producing a faster frequency output. However, the trade-off of using fewer delay cells is a decrease in stability. Noise and other disturbances can cause this instability due to undesirable frequency deviations or phase shifts. Adding delay cells can increase the stability of the circuit, but increases the power consumption and reduces the frequency. These need to be taken into account by the circuit designer in selecting an appropriate tolerance for a given VCO. One advantage of the above embodiment where four delay cells are used is that there is a 90 degree phase shift between each delay cell. This type of phase shift can be convenient to determine the poles of the output frequency.

  Obviously, the IREFs 50a-d significantly affect the output frequency of the VCO 36. As pointed out above, unguaranteed variations in current (eg, variations caused by power supply variations) can have a significant impact on the delay time τ and directly affect the output frequency of the VCO 36.

To understand how the IREFs 50a-d are generated, a VCO bias generator 40 is shown in FIG. In this circuit, ICOMP 44 and voltage controls 26a and 26b are input. IREFs 50a-d are output. In other embodiments, frequency selections f ₁ 80a, f ₂ 80b are also input.

Within VCO bias generator 40 is a differential amplifier 82, current mirrors 84a-d, NMOS transistor 86, AND gate 88, and OR gate 90. ICOMP 44, the power supply compensation current, is used to bias transistors 92a, 92b in differential amplifier 82. Similar to the differential amplifier 72 of FIG. 3, the transistors 92a and 92b function as tail current sources. The differential voltage control signals 26a and 26b bias the PMOS transistors 94a and 94b. The gain can be increased by turning transistor 95 “on” or “off” with frequency selection f ₁ 80a. Also in the differential amplifier 82, the transistor 96 supplies a voltage from its drain that is mirrored to the gate of the PMOS transistor in the current mirrors 84a-d.

  The current mirrors 84a-d also receive the output from the PMOS transistor 96 and simultaneously receive the logical AND 88 of the frequency select signals 80a, 80b along with the logical OR 88 of the logical AND 88 and the frequency select 80b. The outputs of logic AND 88 and logic OR 90 are used to drive separate PMOS transistors 97a-d and 98a-d in current mirrors 84a-d. IREFs 50a-d are output from the drains of PMOS transistors 97a-d and 98a-d.

  During operation, when the VCO 36 reaches a steady state (eg, when REFCLK20 and FBKCLK22 match), the differential voltage control signals 26a, 26b remain relatively stable. Before VCO 36 reaches steady state, the differential control signal adjusts output currents IREF 50a-d (either up or down) until REFCLK20 and FBKCLK22 match. However, a positive or negative deviation in the frequency of REFCLK 20 and FBKCLK 22 also changes to a differential voltage that increases or decreases. Furthermore, increasing or decreasing IREF 50a-d increases or decreases the delay time τ that is inversely proportional to the output frequency. In order to change the IREFs 50a to 50d, the differential amplifier 82 directly controls the amount of current output by the IREFs 50a to 50d.

  ICOMP 44 controls the amount of current through the current source in differential amplifier 82, since power supply fluctuations can cause undesirable output, especially with amplification. The voltage from the gate of the NMOS transistor 86 determined by the ICOMP 44 is applied to the gates of the transistors 92a and 92b. ICOMP 44 is inversely proportional to absolute temperature. That is, as temperature increases, ICOMP 44 decreases and the current through the current source (ie, transistors 92a, 92b) in differential amplifier 82 increases. If ICOMP 44 is not inversely proportional to absolute temperature, differential amplifier 82 will increase in gain as temperature increases. Increasing the gain will erroneously increase the output frequency of the PLL 10. The generation of ICOMP 44 is further illustrated in FIG.

Another that has an effect on the gain of the differential amplifier 82 is the transistor 95. When f ₁ 80a is high (ie, frequency f ₁ is selected), transistor 95 is turned off. In essence, the gain of the amplifier is reduced when the resistance from the drain of transistor 92a to transistor 92b is increased. The ability to adjust the gain of the differential amplifier 82 affects the sensitivity of the output of the bias generator 40. When the gain is low, the output voltage of the differential amplifier 82 (from the drain of transistor 96) does not increase as much as the gain is high. Since the bias generator 40 is frequency selectable, adjusting the gain is useful for changing the sensitivity of the inputs 26a, 26b in different frequency ranges. Selecting different frequency ranges f ₁ 80a, f ₂ 80b is described below.

Upon receiving a voltage signal that increases or decreases from the voltage control signals 26a, 26b, the voltage at the drain of transistor 96 increases or decreases. Increasing the drain voltage decreases the current through the current mirrors 84a-d and vice versa. In various other embodiments and as described above, the current mirrors 84a-d may be adjustable to select the amount of output current with a frequency selection input. For example, in FIG. 4, frequency selections 80a, 80b are subjected to logic processing before being applied to the gates of PMOS transistors 97a-d. For example, if f ₁ 80a is selected (by logic “high”), the output of AND 88 is “low” and PMOS transistors 97a-d are turned on. However, if f ₂ 80a is selected, the output of AND 88 is “high” and the output of OR 90 is “low”. In this case, only PMOS transistors 98a-d are turned on. When only these PMOS transistors are turned on, lower IREF currents 50a-d are output. Therefore, a lower delay time τ occurs, and the output frequency becomes higher. In this embodiment, if both frequency selections f ₁ 80a, f ₂ 80b are selected, the bias generator 40 may turn off because transistors 97a-d and 98a-d are turned off.

  However, if it is desired that only one frequency be output, a single frequency input may be used and no frequency input may be used. In other embodiments, AND 88 and OR 90 may be eliminated and only one set of transistors (ie, 97a-d or 98a-d) may be used. A constant bias can be applied to either set of transistors. Gain adjustment through transistor 95 can also be eliminated in various embodiments.

  As explained above, more or less IREFs 50a-d may be used depending on the number of delay cells in the VCO 36. In bias generator 40, current mirrors 84a-d are used instead of current dividers. Current mirrors provide a determinable amount of current output that is not limited to intrinsic resistance, or variations due to processing that can cause subtle differences in current that can result from current dividers. . However, if a stable current output is available from the current divider, in another embodiment, IREFs 50a-d may be generated from the current divider.

  The independence of the overall power supply variation of the VCO 36 depends on the ICOMP 44. If ICOMP 44 changes due to power supply variations, the amount of current through differential amplifier 82 will increase or decrease unintentionally. An unintentional increase or decrease in ICOMP 44 will cause many problems with VCO 36. One problem is the lack of control of the output frequency. For example, power spikes can increase ICOMP 44 because there is no means or method to correct power supply instability. In that case, the ICOMP 44 increases the gain of the differential amplifier 82. Higher gains will translate to lower IREF 50a-d currents. If IREFs 50a-d decrease, the delay time τ of waveform generator 42 will decrease and the output frequency will increase. If ICOMP 44 is not independent of power fluctuations, many other types of unintentional harmful effects may occur.

Accordingly, FIG. 5 shows a circuit embodiment of a V / C SOURCE 38 with power supply compensation. V _BG input 44, power supply voltage V _p 46 and common voltage V _n 48 are supplied to V / C SOURCE 38. Power supply compensation current and voltage sources IREF44 and VCOMP100 are output. IREF 44 and VCOMP 100 are also inversely proportional to absolute temperature. VCOMP 100 is not used in the embodiments described above. However, other embodiments of the invention may use a compensation voltage instead of a compensation current. Alternatively, other embodiments may use both IREF 44 and VCOMP 100. Further, the V _BG input 44 may be an output from a normal bandgap reference current. The V _BG input 100 may alternatively be some other type of temperature compensation voltage. Also, V _p 46 and V _n 48 may be the same power source that is supplied to the other components in PLL 10. V _p 46 and V _n 48 may also be independent of the power source supplied to the other parts of the PLL.

  The V / C SOURCE 38 includes a voltage divider 102, a voltage reference circuit 104, and a differential amplifier 106. Further, the components included in this embodiment include a filter 108, a voltage mirror circuit 110, and a current mirror circuit 112.

The differential amplifier 106 includes PMOS transistors 114a and 114b, NMOS transistors 116a and 116b, a resistor 118, and NMOS transistors 124a and 124b. The sources of the active load PMOS transistors 114 a and 114 b are connected to the power supply 46. The drains of the transistors 114a and 114b are connected to the drains of the transistors 116a and 116b. The gate of transistor 116 a is biased by V _BG input 44 (which may be filtered by filter 108) and the gate of transistor 116 b is biased by node 120 in voltage divider 122. The resistor 118 is connected to the sources of the transistors 116a and 116b. The sources of the transistors 124a and 124b are also connected to the sources of the transistors 116a and 116b. Transistors 124a and 124b form a current source. In other embodiments, the current source may comprise a different arrangement of transistors or another type of current source. In addition, differential amplifier 106 and V / C SOURCE 38 may also include additional circuit elements (such as bipolar junction transistors instead of MOS transistors).

As explained above, the gate of transistor 116 a is biased by V _BG 44. By biasing transistor 116 a by V _BG 44, the gate of transistor 116 b can be compared to a constant voltage reference in differential amplifier 106. On the other hand, the gate of transistor 116 b is biased by node 122 in voltage divider 102. The voltage divider 102 includes two resistors connected in series. The power supply 46 (Vp-Vn) to the common voltage 48 is distributed through resistors connected in series. As power supply 46 fluctuates, the bias applied from node 122 to the gate of transistor 116 also changes. This variation is a reduced version of the power variation. For example, if a nominal voltage of 3V is used to bias the gate of transistor 116 and power supply 46 has a voltage level of 5V, then two resistors having values of 2KΩ and 3KΩ are in voltage divider 102. May be used. In this example, if the power supply spikes to 5.5V, the bias applied to the gate of transistor 116 will jump to 3.3V.

  Both transistors 116a, 116b are connected to transistors 124a, 124b. The gates of transistors 124 a and 124 b are biased by voltage reference circuit 104. The voltage reference circuit 104 includes transistors 126 to 136 and a resistor 138. In this embodiment, reference circuit 104 generates an output that is inversely proportional to absolute temperature at transistor 132 using a threshold reference current source. Other embodiments may include other reference circuits to generate a voltage or current output.

  In voltage reference circuit 104, the input current travels through transistors 126 and 134. Transistors 128 and 132 generate output current. Since the gate of transistor 132 is connected to the drain of transistor 134, the output current through transistors 128 and 132 is more dependent on the threshold voltage than on the input current through transistors 126 and 134. Thus, the effect of power supply variations on the output current through transistors 126 and 134 is attenuated. The output current from transistor 132 is mirrored and voltage 140 is generated and used to bias transistors 124a, 124b. Voltage 140 is inversely proportional to absolute temperature.

  As the temperature increases, the voltage 140 decreases and the current through the transistors 124a, 124b decreases. Also, the current through transistors 116b and 116a is reduced. ICOMP44 and VCOMP100 are also reduced. However, the opposite effect is seen when the temperature decreases. That is, ICOMP44 and VCOMP100 rise. The amount inversely proportional to the absolute temperature can be determined by the design of the V / C source 38. This may include the design of the components in the V / C source 38, including the voltage reference circuit 104, the voltage mirror circuit 110, the current mirror circuit 112 and / or the differential amplifier 106.

  Returning to the differential amplifier 106 again, power supply variation compensation can be confirmed in the following example. When the power supply does not fluctuate, the drain voltage of the transistor 116a (node 144) remains constant. A voltage mirror circuit 110 may be used to generate VCOMP 100 and a current mirror circuit 112 may be used to generate ICOMP 44. Additional voltage or current references may be generated by adding current and voltage mirrors.

As the power supply (ie, Vp to Vn) increases, the bias applied to the gate of transistor 116b increases and the current through transistor 116b also increases. Since transistor 116a has a reference voltage derived bias, the increase in current through transistor 116b is greater than the current through transistor 116a. Basically, the voltage at node 122 is compared to the gate voltage of transistor 116a (ie, representing V _BG 45). Also, the current through transistors 124a and 124b increases with the increased power supply. The compensation current from transistor 116b travels through resistor 108 to compensate for the increase in current through transistors 124a, 124b. The compensation current prevents a large increase in current in transistor 116a. Thus, voltage and current changes at node 44 are attenuated. When the power supply voltage decreases, the gate voltage applied to the transistor 116b decreases. The compensation current travels in the opposite direction through resistor 108. Furthermore, the overall effect of the voltage change at node 144 is reduced by compensating for the current traveling through resistor 108.

  The attenuation effect on the output voltage (or current) with varying power supply voltage can be seen in the graphs of FIGS. FIG. 6a shows an ICOMP 44 output having a temperature that is raised by the fluctuating power supply supplied to the uncompensated differential amplifier. FIG. 6 b shows the attenuation effect using the power compensated differential amplifier 106. 6a-b, the power supply voltage (VS) varies from 1.4 to 1.95. In both figures, the bias current (ICOMP 44) references node 44 using a current mirror (as shown in FIG. 5). In FIG. 6a, the bias current (ICOMP 44) varies considerably with the changing power supply voltage. However, in FIG. 6b, the change in bias current (ICOMP 44) due to the changing supply voltage is significantly reduced.

  The above embodiments describe a phase locked loop having a VCO with a power supply compensation current and a voltage source. In various embodiments, this current and voltage source can be used to provide a stable current and / or voltage to the VCO. The stable current or voltage supplied to the VCO allows the VCO to output a waveform that is less sensitive to power supply fluctuations that may have deleterious effects on the normal VCO.

  In various other embodiments, the power supply compensation current and voltage source may be used by other types of circuits that require a stable bias. The power supply compensation current and voltage source are not limited to being used in a VCO or PLL.

  It should be understood that the illustrated embodiments are merely examples and should not be considered as limiting the scope of the invention. The claims in the claims should not be construed as limited to the described order or elements unless stated to that effect. Therefore, all embodiments that come within the scope and spirit of the following claims and their equivalents are claimed as the present invention.

It is a block diagram of a phase lock loop. 1 is a block diagram of a voltage controlled oscillator according to an embodiment of the present invention. FIG. 3a is a block diagram of a VCO waveform generator according to one embodiment of the present invention.

FIG. 3b is a circuit diagram of a delay cell according to an embodiment of the present invention.
FIG. 3 is a circuit diagram of a VCO bias generator according to an embodiment of the present invention. FIG. 3 is a circuit diagram of a voltage and current source according to an embodiment of the present invention. FIG. 6a is a graph showing bias current output due to power supply fluctuation.

            FIG. 6b is a graph illustrating a bias current output according to a power supply variation according to an embodiment of the present invention.

Explanation of symbols

10 PLL
12 phase frequency detector, phase detector 14 charge pump 16 loop (low pass) filter 18 voltage controlled oscillator (VCO)
26a, 26b Differential voltage control, differential voltage control signal 28 Frequency divider 30 Lock detector 36 VCO
38 Voltage / Current Source, V / C SOURCE
40 VCO bias generator 42 VCO waveform generator 50a-d Reference current (IREF)
54a-d Delay cell 56 Full swing-single-ended conversion (F / S)
64 voltage divider 72 differential amplifier 78 PMOS transistor 82 differential amplifier 84a-d current mirror 102 voltage divider 104 voltage reference circuit 106 differential amplifier 108 filter 110 voltage mirror circuit 112 current mirror circuit

Claims (10)

A first resistor connected in series with a second resistor at a reference node, wherein a power supply voltage is distributed across the first and second resistors;
A voltage reference power supply;
A differential amplifier having first and second voltage inputs and a compensation output, wherein the first input is connected to the reference node and the second input is connected to the voltage reference power supply;
A power supply compensation voltage and current source. The differential amplifier is
A first NMOS transistor having a gate connected to the first input and a drain connected to a source of the first PMOS transistor;
A second NMOS transistor having a gate connected to the second input and a drain connected to a source of a second PMOS transistor;
A current source having first and second inputs, the first input connected to the source of the first NMOS transistor, and the second input connected to the source of the NMOS transistor;
A third resistor having first and second terminals, wherein the first terminal is connected to the source of the NMOS transistor, and the second terminal is connected to the source of the second NMOS transistor; ,
The apparatus of claim 1, further comprising:   The current source comprises third and fourth NMOS transistors, the drain of the third NMOS transistor is connected to the first input of the current source, and the drain of the fourth NMOS transistor is the current source of the current source. The apparatus of claim 2, connected to the second input.   4. The apparatus of claim 3, wherein the gates of the third and fourth NMOS transistors are connected to a second voltage reference power source.   The apparatus of claim 4, wherein the second voltage reference power source is a threshold reference voltage source.   The apparatus of claim 1, wherein the voltage reference power supply is a bandgap voltage reference power supply.   The apparatus of claim 1, further comprising a current mirror connected to the compensation output that outputs a power supply compensation current.   8. The apparatus of claim 7, further comprising a MOS transistor connected to the output of the current mirror operable to receive the compensation current and generate the compensation output.   The apparatus of claim 1, wherein the compensation output is provided to a reference input of a voltage controlled oscillator.   The apparatus of claim 7, wherein the compensation current is provided to a current reference input of a voltage controlled oscillator.

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