JP2007116626A - Control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control circuit which prevents a reset circuit from erroneous operation due to external noise. <P>SOLUTION: The control circuit for controlling an apparatus comprises a reset signal generation means for generating a reset signal, a reset means for making a reset operation of a circuit by the reset signal generated in the reset signal generation means, and a sensitivity blunting means for blunting the sensitivity of the reset signal, wherein the sensitivity blunting means is valid only within a period designated by the control circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a control circuit including reset signal generating means for generating a reset signal for performing an initialization operation of a circuit. Particularly in a control circuit in an apparatus such as an image forming apparatus in which noise is likely to be generated in synchronization with a high-voltage leak or drive of a driving load, and malfunction is caused by the noise being superimposed on a reset signal. It is valid.

  A control circuit in an image forming apparatus or the like has reset generation means for generating a reset signal in order to initialize a circuit such as a CPU or an ASIC. This is a signal intended to initialize and stably operate these circuits when power is turned on or when some abnormality occurs.

  However, in the image forming apparatus, noise may occur on the reset signal line due to high voltage used in an electrophotographic process mechanism unit or noise generated by driving a load such as a motor. The reset circuit may operate unstablely due to this noise, or the operation of the control circuit itself may become unstable due to resetting at an unintended timing.

  As means for preventing such a problem, for example, in Patent Document 1, when an external noise is detected, it is shaped into a reset signal having a predetermined time width. In order to perform the reset operation stably, a reset signal having a predetermined time width abnormality is required. However, according to Patent Document 1, a noise signal having a short spike-like width is shaped into a reset signal having a predetermined time width. As a result, the reset operation can be performed stably.

Patent Document 2 proposes a method for canceling noise of a reset signal generated at the timing when noise is generated in the apparatus. Specifically, when noise is generated when a discharge lamp that generates a high voltage is lit in the device, it is determined whether or not it is a reset signal generated when a high voltage is being generated. The reset signal is canceled or delayed for a predetermined period (a period until noise generation is sufficiently reduced). As a result, it is possible to prevent a malfunction of resetting during a noise generation period.
JP-A-5-035367 JP 2001-338777 A

  However, in the method of Patent Document 1, it is possible to stably perform the reset operation when there is external noise, but when the reset operation is not desired, external noise is generated and the reset circuit is activated. there is a possibility. For example, since a high voltage is generated during image formation in the image forming apparatus and a lot of inductive loads such as a motor, a solenoid, and a clutch are driven for paper conveyance, noise is inevitably generated. According to the method of Patent Document 1, a stable reset is applied due to these noises, but this means that the image forming operation is stopped halfway, which is not a desired operation for the user.

  On the other hand, according to the method of Patent Document 2, the reset signal is canceled or delayed until noise generation is stopped at the timing when noise occurs, but during image formation, high voltage leakage, CPU runaway, motor, etc. In such a case, it is important to promptly reset the control circuit, and it is not desirable to cancel the power supply voltage.

  Therefore, an object of the present invention is to provide a control circuit that can prevent the reset circuit from malfunctioning due to external noise.

  In order to achieve the above object, according to a first aspect of the present invention, there is provided a control circuit for controlling an apparatus, wherein a reset signal generating means for generating a reset signal, and a reset operation of the circuit by a reset signal generated by the reset signal generating means. And a resetting means for reducing the sensitivity of the reset signal.

  The invention described in claim 2 is characterized in that, in the invention described in claim 1, the sensitivity dulling means is effective only for a predetermined period designated by the control circuit.

  According to the first aspect of the present invention, it is possible to prevent the reset circuit from malfunctioning due to external noise by providing means for reducing the sensitivity of the reset signal.

  According to the second aspect of the present invention, by limiting the operation of the sensitivity blunting means in the first aspect of the invention to a period specified by the control circuit, the sensitivity blunting means is limited to a period during which noise is likely to occur in the apparatus. It is possible to operate. That is, a normal reset operation is possible while noise is not generated, and a safer circuit can be realized.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

  The overall configuration of the image forming apparatus according to the embodiment of the present invention will be described with reference to FIG.

  FIG. 2 is a block diagram showing the internal structure of the image forming apparatus according to the embodiment of the present invention. The image forming apparatus includes a scanner unit B, an image forming unit C, and a sheet deck D in each unit of the image forming apparatus main body A.

  The image forming apparatus main body A has a scanner unit B as image reading means for reading the current image information of the book at the upper part, an image forming part C as image forming means at the lower part, and a sheet at the lower part. The deck D is assembled.

  More specifically, the scanner unit B includes an operation system light source 201, a platen glass 202, a document pressure plate 203 that can be opened and closed with respect to the image forming apparatus main body A, a mirror 204, a lens 205, a light receiving element (photoelectric conversion element) 206. And an image processing unit. Then, a book document such as a book / thick paper / curl paper or a sheet-like document is placed on the platen glass 202 with the document surface facing downward, and the back surface is pressed by the document pressure plate 203 and set in a stationary state. When the start key is pressed, the scanning light source 201 scans the lower part of the platen glass 202 in the direction of arrow a and reads the image information on the document surface. The document image information read by the scanning light source 201 is processed by the image processing unit, converted into an electrical signal, and transmitted to the laser scanner 111 of the image forming unit C.

  Here, the image forming apparatus main body A functions as a copying machine when the processing signal of the image processing unit is input to the laser scanner 111 of the image forming unit C, and functions as a printer when the output signal of the external device (computer) is input. To do. The image forming apparatus main body A also functions as a facsimile apparatus if it receives a signal from another facsimile apparatus or transmits a signal from the image processing unit to another facsimile apparatus.

  On the other hand, a sheet cassette 1 is mounted at the lower part of the image forming section C. The sheet cassette 1 is configured as one feeding unit with two cassettes, a lower cassette 1a and an upper cassette 1b. In the present embodiment, two supply units U1 and U2 are mounted, and four cassettes are mounted. One feeding unit U1 positioned above is detachably attached to the image forming apparatus main body A, and the lower feeding unit U2 is detachably attached to the sheet deck D.

  The sheets (recording materials) accommodated in the lower cassette 1a and the upper cassette 1b are fed out by a pickup roller 3 serving as a feeding rotating body, as will be described later, and cooperation between the feed roller 4 and the retard roller 5 is performed. After being separated and fed one by one by the action, they are conveyed by the conveying rollers 104 and 105, guided by the registration rollers 106, and fed to the image forming unit C by the registration rollers 106 so as to be synchronized with the image forming operation. Sent.

  In addition to the sheet cassette 1 described above, a manual feed tray 10 is disposed on the side surface of the image forming apparatus main body A, and the sheet S on the manual feed tray 10 is fed to the registration roller 106 by the manual feed roller 11. It is.

  The image forming unit C includes an electrophotographic photosensitive drum 112, an image writing optical system 113, a developing device 114, a transfer charger 115, and the like. Then, a laser beam corresponding to the image information emitted from the laser scanner 111 is scanned by the image writing optical system 113 on the surface of the photosensitive drum 112 uniformly charged by the transfer charger 115 to form a latent image, A toner image is formed on the latent image by the developing device 114, and the toner image is transferred by the transfer charger 115 to the first surface of the sheet conveyed by the registration roller 106 in synchronization with the rotation of the photosensitive drum 112. .

  In the figure, reference numeral 117 denotes a conveyance unit that conveys a sheet on which a toner image is formed, 118 denotes a fixing device, and 119 denotes a discharge roller. The sheet on which the toner image is formed is conveyed to the fixing device 118 by the conveying unit 117 and heated and pressed to fix the toner image on the surface of the sheet. Then, the discharge roller 119 is placed on the sorter 120 disposed outside the apparatus. Discharged and loaded by.

  When recording images on both sides of the sheet, the sheet discharged from the fixing device 118 is held between the discharge rollers 119, and the discharge roller 119 is reversed when the trailing edge of the sheet passes the branch point 207. After the sheet is once placed on the sheet double-sided tray 121, the sheet is conveyed by the conveying rollers 104 and 105, reaches the registration roller 106, and the inverted sheet forms an image on the second surface in the same manner as described above. Then, it is configured to be discharged and stacked on the sorter 120.

  Next, a control circuit of the image forming apparatus in the present embodiment will be described.

  FIG. 3 is a schematic block diagram of a control circuit in the image forming apparatus of the present embodiment. Reference numeral 501 denotes a CPU which controls this control circuit. Reference numeral 504 denotes a read only memory (ROM), which stores a program for controlling the control circuit. Reference numeral 503 denotes a random access memory (RAM) for performing a program operation of the CPU.

  Further, data backup is possible even when the power is turned off by a battery (not shown). Reference numeral 502 denotes an ASIC, which has a support function such as control of a load connected to the control circuit and interrupt to the CPU. The CPU 501, the ASIC 502, the ROM 503, and the RAM 504 are connected by a CPU bus, and the CPU can read / write data from / to each IC.

  A motor driver circuit 505 controls the rotation of the motor 510 based on the control signal generated by the ASIC 502. A solenoid driver 506 performs drive control of the solenoid 511. Reference numeral 507 denotes a sensor signal input circuit unit to which an input signal from a sensor such as a photo interrupter is input. This sensor input signal is input to the ASIC 502, and it is possible to detect the timing of paper conveyance in the image forming apparatus.

  Next, the reset IC 500 will be described.

  This generates a reset signal “RESET *” based on a power supply voltage or a watchdog monitoring signal from the CPU. The RESET * signal is “Low” for reset logic, and “High” for reset release. The operation of the reset IC will be described with reference to FIGS.

  FIG. 4 is a timing chart showing the operation when the power is turned on. When power is turned on at timing T0, the power supply voltage “Vcc” gradually rises to a predetermined voltage. After reaching the threshold voltage “Vth” at T1, the “RESET *” signal holds “Low” only for the reset time “T_rst” and then is inverted to “High” to cancel the reset.

  In addition, when the power supply voltage temporarily decreases and falls below Vth at the timing of T2, the RESET * signal becomes “Low” and the reset state is entered. After that, when the power supply voltage is restored and becomes higher than Vth at the timing of T3, the RESET * signal becomes “High” after holding “Low” for the time T_rst, and the reset is released. By doing so, it is possible to stably operate the CPU and ASIC in the control circuit.

  Next, the operation of the watch dog during normal operation will be described with reference to FIG.

  A Watch Dog signal as shown in FIG. 5 is output from the CPU 501 and is input to the reset IC 500. The WatchDog signal is a repetitive waveform having a predetermined cycle “Tcyc” generated by the CPU. The reset IC 500 holds the RESET * signal at “High” by confirming that the WatchDog signal is input at a predetermined cycle.

  If the CPU goes out of control for some reason at the Terr timing, the Watch Dog signal will not be output. Therefore, even if more than Tcyc has elapsed since the last Watch Dog signal was generated, the next Watch Dog signal is not input, and the reset IC The output RESET * signal becomes “Low”, and the CPU is reset. The reset signal is held “Low” for the time Tcyc and then the reset is released, and the WatchDog signal is output again at a cycle of Tcyc from the CPU.

  Next, the timing at which noise that affects the reset signal line is likely to occur during the printing operation of the image forming apparatus according to the present embodiment will be described with reference to FIG.

  In FIG. 6, the hatched portion indicates a time zone where there is a high possibility that noise will occur. When the motor is started at the timing of “Motor_On”, noise may occur for a predetermined time from that point. Next, noise may occur between HVT_On and HVT_Off due to high-voltage leakage or the like. Further, if the motor is turned off at the Motor_Off timing, noise may occur for a predetermined time.

  Next, the operation of the reset circuit in the present embodiment will be described with reference to FIG.

  In FIG. 1, the reset signal “RESET *” generated by the reset IC 500 is input to the ASIC 502 via a low-pass filter including a resistor and a capacitor. This low-pass filter is for removing minor noise on the RESET * signal. The signal that has passed through the low-pass filter is SG1 and is input to the AND gate 553 and is input to the sensitivity dampening circuit 551. The SG1 signal processed by the sensitivity desensitizing circuit 551 is output as SG2, and is input to the OR gate 552 together with the SnsChg signal. Here, the SnsChg signal is a signal for switching whether or not the sensitivity desensitizing circuit is enabled, and is configured to be valid when “High” and invalid when “Low”. The output SG3 of the OR gate 552 is input to the AND gate 553 together with the SG1 signal, and the output becomes an “Rst *” signal that resets the ASIC.

  Next, the sensitivity blunting circuit 551 will be described.

  FIG. 10 shows an example of a sensitivity desensitizing circuit. The input SG1 is delayed by 4 clocks by the D flip-flop. The delayed signal and the SG1 signal are input to the subsequent AND gate. In this way, a “Low” pulse having a width of 4 clocks or less is canceled. When a normal reset signal is input, it is delayed by 4 clocks and output as an SG2 signal. In this embodiment, the reset blunt circuit cancels a signal having a width of 4 clocks. However, the signal may be set to an appropriate width or variable according to the width of noise mixed in the reset signal.

  Next, the operation when the reset sensitivity blunting means is disabled will be described with reference to FIG.

  FIG. 7 is a timing chart when the reset sensitivity dulling means is disabled, and the signal names shown on the left side of the signals correspond to the signal names in the block diagram of FIG. Small noise is mixed at the timing of T_n1, but this is removed by the low-pass filter of the input unit, and thus does not cause a reset operation.

  Next, at the timing of T_n2, the RESET * signal contains a larger noise than before, but this cannot be completely removed by the low-pass filter of the input terminal section, and the Rst * signal is output as “Low”. Therefore, a reset operation is caused inside the ASIC. Further, the reset signal RESET * generated at the timing of T_n3 is a normal reset signal, and at the same time, the Rst * signal becomes “Low”, so that the reset operation can be performed normally.

  Next, the operation when the SnsChg signal is switched will be described.

  FIG. 8 is a timing chart showing the timing for switching the SnsChg signal. By switching the SnsChg signal to “High” at the timing at which noise described with reference to FIG. 6 is likely to occur, the reset sensitivity reduction circuit is enabled. The operation when the SnsChg signal is set to “High” will be described based on the timing chart of FIG.

  The short-width noise generated at the timing of T_n2 is transmitted to SG1, but is removed at the output SG2 of the sensitivity desensitizing circuit. Since the SnsChg signal is “High” and the sensitivity desensitizing circuit is enabled, SG3 = SG2. Therefore, the Rst * signal becomes AND of SG1 and SG3, and "High" is held as shown in the lowermost stage of FIG. Thereafter, the reset signal generated at the timing of T_n3 is delayed by 4 clocks after the RESET * signal is input, and the reset signal becomes “Low”.

  As described above, according to the present embodiment, an unintended reset operation can be prevented by enabling the reset sensitivity reduction circuit only during a period in which noise is likely to be generated in advance.

  Even if the reset blunting circuit is enabled, the reset operation can be performed when a normal reset signal is generated although the reset timing is delayed. Furthermore, since the reset signal can be directly reflected during the period in which the reset sensitivity reduction circuit is disabled, the reset operation can be promptly performed in response to a drop in power supply voltage or a runaway CPU. .

  In general, a reset during image formation often occurs during an abnormality, and a reset during non-image formation often occurs when the apparatus is normal, such as when the apparatus is turned off. Therefore, it is important to cancel some noises reliably during image formation, and to reset reliably when there is an abnormality. Further, it is important to perform a reset operation in response to a decrease in power supply voltage or a reset instruction from another unit at the time of non-image formation. As described in the present embodiment, according to the present invention, the above two objects can be achieved.

It is a circuit block diagram around the reset signal in the embodiment of the present invention. 1 is a diagram illustrating a cross section of an image forming apparatus according to an embodiment of the present invention. FIG. 3 is a block diagram of a control circuit of the image forming apparatus in the embodiment of the present invention. 3 is a timing chart showing the operation of the reset IC in the embodiment of the present invention. 3 is a timing chart showing the operation of the reset IC in the embodiment of the present invention. FIG. 4 is a diagram illustrating timing at which noise is likely to occur in the image forming apparatus according to the embodiment of the present invention. 5 is a timing chart showing an operation when the reset sensitivity blunting circuit is invalid in the embodiment of the present invention. It is a timing chart for demonstrating the timing which makes a reset blunt circuit effective in embodiment of this invention. It is a timing chart which shows operation at the time of enabling a reset sensitivity blunting circuit in an embodiment of the invention. It is a figure which shows an example of the reset blunting circuit in embodiment of this invention.

Explanation of symbols

500 Reset IC
501 CPU
502 ASIC
551 Reset sensitivity slowdown circuit

Claims (2)

In the control circuit that controls the device,
Control comprising: a reset signal generating means for generating a reset signal; a reset means for performing a reset operation of the circuit by the reset signal generated by the reset signal generating means; and a sensitivity blunting means for reducing the sensitivity of the reset signal. circuit.   2. The control circuit according to claim 1, wherein the sensitivity dulling means is valid only for a predetermined period specified by the control circuit.

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