JP2007116011A - Method for manufacturing semiconductor integrated-circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the resolution of lithography in a dual damascene process by reducing a reflectance of an antireflection film formed on an interlayer insulating film. <P>SOLUTION: When a via hole and wiring channel for burying Cu wiring is formed on an interlayer insulating film by a dry etching with a photo resist film as a mask, an antireflection film 26 on the interlayer insulating film which is made up of an SiOC film 25 is composed of an SiO film 26a, an SiON film 26b and an SiO film 26c, and the halation of a photo resist film 27 is inhibited. The preferred combination of the film thickness of the SiO film 26a and the film thickness of the SiON film 26b is that the film thickness of SiO film 26a is not more than 40 nm or at least 75 nm and the film thickness of the SiON film 26b is at least 40 nm, and the more preferred combination is that the film thickness of SiO film 26a is not more than 30 nm or at least 80 nm and the film thickness of the SiON film 26b is at least 50 nm. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a technology effective when applied to formation of Cu (copper) wiring using a damascene method.

  In the damascene method, after forming a fine wiring groove in an interlayer insulating film on a semiconductor substrate, a metal film is deposited on the interlayer insulating film including the inside of the wiring groove, and then chemical mechanical polishing (CMP). ) Method is used to remove the metal film outside the wiring trench, thereby forming a buried wiring inside the wiring trench.

  As the metal material for the embedded wiring, Cu (copper) that can ensure high reliability even if it is thinned is mainly used. In addition, when a buried wiring is formed in an interlayer insulating film using the damascene method, the interlayer insulating film is made of an insulating material having a low dielectric constant in order to reduce the capacitance generated between adjacent wirings. Yes.

  Among the damascene methods described above, in a method called dual-damascene method, a via hole for connecting a lower layer wiring is formed below a wiring groove formed in an interlayer insulating film, and metal is simultaneously formed in the wiring groove and the via hole. By embedding the film, the process of forming the buried wiring is simplified. This dual damascene method includes a via first method in which a via hole reaching the lower layer wiring is formed in the insulating film prior to the formation of the wiring groove, and a wiring groove is formed in the insulating film and then the lower wiring layer is formed in the wiring groove. There is a trench first method for forming a reaching via hole, and the via first method is mainly used in a process of forming a fine buried wiring.

  On the other hand, after forming a via hole in the interlayer insulating film in the lower layer in advance and embedding a metal plug therein, and then depositing an interlayer insulating film on the upper part to expose the metal plug, A method of forming a buried wiring inside the wiring trench is called a single-damascene method.

  By the way, when the width of the wiring groove and the diameter of the via hole are reduced with the miniaturization of the semiconductor element, it is caused by the halation of the photoresist film used when the wiring groove and the via hole are formed by etching the interlayer insulating film. Pattern defects are a problem. That is, when exposing the photoresist film spin-coated on the interlayer insulating film to transfer the pattern of wiring grooves and via holes, if the exposure light is reflected on the surface of the underlying wiring and the photoresist film causes halation, the wiring The pattern of the groove or via hole cannot be transferred with high accuracy.

  Therefore, in recent years, an antireflection film that absorbs exposure light is formed between the interlayer insulating film and the photoresist film to suppress the halation of the photoresist film due to the reflected light from the lower layer wiring. Yes.

  Patent Document 1 (Japanese Patent Laid-Open No. 2002-329779, [0037] to [0040], FIG. 3) discloses a technique of forming a buried Cu wiring in an interlayer insulating film using a dual damascene method. In this document, an interlayer insulating film is constituted by a laminated film of a low dielectric constant SiO (silicon oxide) film doped with fluorine and having a relative dielectric constant reduced to about 3.7 and a normal SiO film, and this interlayer insulating film The antireflection film made of a laminated film of a silicon oxynitride (SiON) film and a SiO film is formed between the photoresist film and the photoresist film formed thereon, thereby preventing halation of the photoresist film.

  Patent Document 2 (Japanese Patent Laid-Open No. 2004-253671, [0022], [0023], FIG. 4) discloses a low dielectric constant made of a carbon-doped SiO film (SiOC film) or methylsilsesquioxane (MSQ). A dual damascene process is disclosed in which an antireflection film made of a SiON film or a laminated film of a SiON film and a SiO film is formed on an interlayer insulating film.

  Patent Document 3 (Japanese Patent Laid-Open No. 2004-14828, [0027], [0028], FIG. 2) discloses that SiON or silicon nitride (SiN) is formed on an interlayer insulating film made of an SiOC film via a sacrificial film made of an SiO film. Discloses a dual damascene process for forming an anti-reflection film made of the like.

  Patent Document 4 (Japanese Patent Laid-Open No. 2003-332340, [0030], [0057] to [0061], FIG. 11) reflects on an interlayer insulating film including a SiOC film via a SiN film, a SiO film, and a SiON film. A dual damascene process for forming a barrier film is disclosed. Here, the SiN film functions as an adhesive layer that improves the adhesion between the interlayer insulating film and the SiO film. The SiO film has functions such as ensuring the mechanical strength of the interlayer insulating film, surface protection, and ensuring moisture resistance during the chemical mechanical polishing process. The SiON film has a function of preventing shoulder shaving from occurring in the underlying SiO film in an etching process other than the etching process for removing the SiON film.

  Patent Document 5 (Japanese Patent Application Laid-Open No. 2004-14841, [0071], [0072], FIG. 14) discloses an antireflection film made of SiN via a diffusion prevention film made of an SiO film on an interlayer insulating film made of an SiOC film. Discloses a dual damascene process.

  Patent Document 6 (Japanese Patent Application Laid-Open No. 2004-273383, [0037] to [0039], FIG. 3) discloses a film (SiO film) that suppresses permeation of nitrogen-based compound gas on an interlayer insulating film made of an SiOC film. Discloses a dual damascene process for forming an organic antireflection coating.

Patent Document 7 (Japanese Patent Laid-Open No. 2004-6633, [0047] to [0052], FIG. 2) and Patent Document 8 (Japanese Patent Laid-Open No. 2004-221439, [0042] to [0051]) are made of SiOC films. A dual damascene process for forming an antireflection film made of SiON on an interlayer insulating film is disclosed.
JP 2002-329779 A ([0037] to [0040], FIG. 3) Japanese Patent Laying-Open No. 2004-253671 ([0022], [0023], FIG. 4) JP 2004-14828 ([0027], [0028], FIG. 2) JP 2003-332340 A ([0030], [0057] to [0061], FIG. 11) JP 2004-14841 A ([0071], [0072], FIG. 14) Japanese Patent Laying-Open No. 2004-273483 ([0037] to [0039], FIG. 3) Japanese Patent Laying-Open No. 2004-6633 ([0047] to [0052], FIG. 2) JP 2004-221439 A ([0042] to [0051])

  The inventor forms an antireflection film composed of a laminated film of a SiON film (lower layer) and a SiO film (upper layer) on an interlayer insulating film composed of a SiOC film, and uses a light source having the same wavelength (248 nm) as that of a KrF excimer laser. The light reflectance of this antireflection film was measured.

  At that time, when the light reflectance was measured by variously changing the thickness of the SiON film and the thickness of the SiO film, it may exceed the light reflectance (5% or less) required for preventing halation. I found out. Similar results were obtained even when the light reflectance was measured by variously changing the composition ratio of O and N in the SiON film.

  Furthermore, when a SiON film was laminated on the SiOC film and the adhesive strength between the two was measured, it was found that sufficient adhesive strength could not be obtained, for example, there was a risk of peeling at the interface between the two during chemical mechanical polishing. .

  An object of the present invention is to provide a technique for improving the resolution of lithography in a dual damascene process by reducing the light reflectance of an antireflection film formed on a SiOC film.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

A method for manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps:
(A) forming an insulating film mainly comprising a SiOC film on the main surface of the semiconductor substrate;
(B) forming an antireflection film comprising a laminated film of a first SiO film, a SiON film, and a second SiO film on the insulating film;
(C) forming a first photoresist film on the antireflection film;
(D) forming a via hole in the insulating film by etching the antireflection film and the insulating film using the first photoresist film as a mask;
(E) a step of filling the via hole with a filling agent after removing the first photoresist film;
(F) after the step (e), forming a second photoresist film on the antireflection film;
(G) etching the antireflection film and the insulating film in a region including the region where the via hole is formed using the second photoresist film as a mask, and stopping the etching in the middle of the insulating film; A step of forming a wiring trench in the insulating film,
(H) a step of embedding a metal film in the wiring trench and the via hole after removing the second photoresist film and the filling agent;
(I) A step of forming a wiring made of the metal film inside the wiring groove and the via hole by removing the metal film outside the wiring groove by a chemical mechanical polishing method.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Formation of multilayer Cu wiring by the dual damascene method can be performed with high yield. In addition, it is possible to simplify the formation process of the multilayer Cu wiring by the dual damascene method.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  This embodiment is applied to a semiconductor integrated circuit device having a multilayer Cu wiring. In this semiconductor integrated circuit device, the first layer Cu wiring is formed by a single damascene method, and the second and subsequent Cu wirings are formed by a dual damascene method. Hereinafter, the manufacturing method will be described in the order of steps with reference to FIGS.

  First, as shown in FIG. 1, an n-channel MISFET (Qn) and a p-channel MISFET (Qp) are formed on the main surface of a semiconductor substrate (hereinafter simply referred to as a substrate) 1 made of, for example, single crystal silicon. In the figure, reference numeral 2 denotes an element isolation groove, reference numeral 4 denotes a p-type well, and reference numeral 5 denotes an n-type well.

  The element isolation trench 2 is a well-known STI (Shallow Trench Isolation) in which a SiO (silicon oxide) film 3 is embedded in a trench formed by etching the substrate 1 and then the surface thereof is planarized by a chemical mechanical polishing method. ) Method. In the p-type well 4 and the n-type well 5, p-type impurities (for example, boron) and n-type impurities (for example, phosphorus) are ion-implanted into the substrate 1, and then the substrate 1 is heat-treated to remove these impurities into the substrate 1. Form by diffusing in.

  The n-channel type MISFET (Qn) includes a gate insulating film 6 made of a SiO film or a SiON (silicon oxynitride) film formed on the surface of the p-type well 4, and a polycrystalline silicon film formed on the gate insulating film 6. A pair of n-type semiconductor regions (sources) formed in the p-type well 4 on both sides of the gate electrode 7 and the side wall spacer 8 formed on the side wall of the gate electrode 7. , Drain) 11 and the like. The p-channel MISFET (Qp) includes a gate insulating film 6, a gate electrode 7, a sidewall spacer 8, and a pair of p-type semiconductor regions (source and drain) 12 formed in the n-type well 5 on both sides of the gate electrode 7. Consists of.

  In the polycrystalline silicon film constituting the gate electrode 7 of the n-channel MISFET (Qn), an n-type impurity (phosphorus) is introduced into the polycrystalline silicon film constituting the gate electrode 7 of the n-channel MISFET (Qn). Is doped with p-type impurities (boron). Further, the respective surfaces of the gate electrode 7 and the n-type semiconductor region (source, drain) 11 of the n-channel type MISFET (Qn), and the gate electrode 7 and the p-type semiconductor region (source, drain) of the p-channel type MISFET (Qp). ) 12 is formed with a Co (cobalt) silicide film 9 for the purpose of reducing the resistance of the gate electrode 7 and the source and drain.

  Next, as shown in FIG. 2, after an etching stopper film 13 and an insulating film 14 are deposited on each of the n-channel MISFET (Qn) and the p-channel MISFET (Qp), a chemical mechanical polishing method is performed. By using this, the surface of the insulating film 14 is planarized. The etching stopper film 13 is composed of, for example, a silicon nitride film deposited by the CVD method, and the insulating film 14 is composed of, for example, an SiO film deposited by the CVD method.

  Next, the upper insulating film 14 of the n-type semiconductor region (source, drain) 11 of the n-channel type MISFET (Qn) and the p-type semiconductor region (source, drain) 12 of the p-channel type MISFET (Qp) is etched. Subsequently, the underlying etching stopper film 13 is etched to form a contact hole 15.

  Next, a metal plug 16 is formed inside the contact hole 15. In order to form the metal plug 16, first, a TiN (titanium nitride) film and a W (tungsten) film are deposited on the insulating film 14 including the inside of the contact hole 15 by sputtering. The TiN film functions as a barrier metal film, and can be composed of a laminated film of a TiN film and a Ti (titanium) film. Next, the TiN film and the W film on the insulating film 14 are removed by a chemical mechanical polishing method. The metal plug 16 formed inside the contact hole 15 includes an n-type semiconductor region (source, drain) 11 of the n-channel type MISFET (Qn) and a p-type semiconductor region (source, drain) 12 of the p-channel type MISFET (Qp). Are electrically connected to each other.

  Next, as shown in FIG. 3, after a SiCN film 17 is deposited on the insulating film 14, a SiOC film 18 is deposited on the SiCN film 17 as an interlayer insulating film. The SiCN film 17 functions as an etching stopper film when a wiring groove is formed in the SiOC film 18 in a later process. Although an SiN (silicon nitride) film can be used as the etching stopper film, here, the SiCN film 17 having a dielectric constant lower than that of the SiN film is used. The SiCN film 17 is deposited by the plasma CVD method, and the film thickness is about 50 nm. The SiOC film 18 on the SiCN film 17 is deposited by the plasma CVD method, and the film thickness is about 200 nm. The relative dielectric constant of the SiOC film 18 is about 2.9.

  Next, as shown in FIG. 4, an antireflection film 19 is formed on the SiOC film 18. The antireflection film 19 is composed of a three-layer film of an SiO film 19a, an SiON film 19b, and an SiO film 19c, and is continuously formed in a chamber of a plasma CVD apparatus. An example of the conditions for forming the antireflection film 19 is as follows.

First, the substrate 1 is carried into the chamber of the plasma CVD apparatus and its temperature is set to 400 ° C. Next, SiH ₄ (monosilane) (550 sccm) as a source gas and N ₂ O (nitrous oxide) (10000 sccm) as a carrier gas are introduced into the chamber, and a SiO film 19a having a thickness of 30 nm is deposited. (RF power = 525 W). The SiO film 19a is deposited with RF power = 1240W by introducing TEOS (tetraethoxysilane) (5250 sccm) and oxygen (4200 sccm) as source gases and He (helium) (4000 sccm) as a carrier gas into the chamber. May be.

Next, after evacuating the chamber, SiH ₄ (300 sccm) and N ₂ O (635 sccm) as source gases and He (9000 sccm) as a carrier gas are introduced into the chamber, and SiON having a film thickness of 50 nm. A film 19b is deposited (RF power = 200 W). Subsequently, after evacuating the chamber, SiH ₄ (35 sccm), N ₂ O (10000 sccm) and He (9000 sccm) are introduced into the chamber, and a 5 nm-thickness SiO film 19c is deposited (RF power = 180 W). ).

  Here, the reason why the lowermost layer film of the antireflection film 19 is composed of the SiO film 19a will be described with reference to FIG. FIG. 5 is a graph showing the interfacial adhesive strength between the upper and lower layers in a case where two types of insulating films having different compositions are laminated, in terms of critical peeling load (unit: mN).

  As shown in the figure, it can be seen that the interface adhesive force between the upper and lower layers when the SiON film is deposited on the SiOC film is relatively weak. On the other hand, when the SiO film is deposited on the upper part of the SiOC film and when the SiON film is deposited on the upper part of the SiO film, the interface adhesion between the upper and lower layers is extremely strong.

  Therefore, the lowermost layer film of the antireflection film 19 formed on the upper part of the SiOC film 18 is composed of the SiO film 19a, and the SiON film 19b is deposited on the upper film, thereby the SiOC film 18 and the like in the case of chemical mechanical polishing. Separation from the antireflection film 19 can be reliably prevented. On the other hand, the SiO film 19c deposited on the SiON film 19b functions as a sacrificial film for preventing oxidation of the SiON film 19b during plasma ashing.

  If the adhesion between the SiOC film 18 and the antireflection film 19 is not affected by the adhesion between the SiOC film and the SiON film, the lowermost SiO film 19a is omitted, and the SiON film 19b and the SiO film 19c The antireflection film 19 may be formed of a two-layer film. However, generally, the SiO film has a higher light refractive index than the SiOC film, and the SiON film has a higher light refractive index than the SiO film. Therefore, when the antireflection film 19 is composed of the above three layers, the effect of the reflected light interfering and weakening at the interface between the films becomes large, so the antireflection film 19 is composed of two layers. As compared with the case, the halation suppression effect is also increased.

  Next, as shown in FIG. 6, after forming a photoresist film 21 on the antireflection film 19, the antireflection film 19 and the SiOC film 18 are dry-etched using the photoresist film 21 as a mask. A wiring groove 20 is formed. At this time, the SiCN film 17 under the SiOC film 18 functions as an etching stopper film.

  Next, the photoresist film 21 is removed by plasma ashing, and then the polymer on the surface of the substrate 1 generated at the time of ashing is removed by wet cleaning, and then the SiCN film 17 at the bottom of the wiring trench 20 as shown in FIG. The surface of the metal plug 16 is exposed by dry etching. At this time, the antireflection film 19 formed on the upper part of the SiOC film 18 is also etched, and the film thickness is reduced.

  Next, as shown in FIG. 8, a barrier metal film 22a made of a TiN film having a thickness of about 50 nm or a laminated film of a TiN film and a Ti film is formed on the antireflection film 19 including the inside of the wiring trench 20 by a sputtering method. Subsequently, a thick (about 800 nm to 1600 nm) Cu film 22b that completely fills the inside of the wiring trench 20 is deposited by sputtering or electrolytic plating. The barrier metal film functions as a barrier film that prevents the Cu film from diffusing into the surrounding insulating film. As the barrier metal film, a TiN film, a metal nitride film such as a WN (tungsten nitride) film or a TaN (tantalum nitride) film, or an alloy film obtained by adding Si to these, or a Ta film, Ti film, W film, Various conductive films that do not easily react with Cu, such as a refractory metal film such as a TiW film or a laminated film of these refractory metal films, can be used. When the Cu film 22b is deposited by electrolytic plating, a Cu seed layer (not shown) is deposited on the barrier metal film 22a by sputtering, and the Cu film 22b is deposited on the surface of the seed layer.

  Next, as shown in FIG. 9, the Cu film 22b and the barrier metal film 22a outside the wiring groove 20 are removed by a chemical mechanical polishing method, so that the first layer of Cu wiring is formed inside the wiring groove 20. 22 is formed. At this time, the antireflection film 19 formed on the SiOC film 18 is also removed at the same time.

  Next, as shown in FIG. 10, a SiCN film 24 is deposited on top of the SiOC film 18 on which the Cu wiring 22 is formed, and then a SiOC film 25 is deposited on the SiCN film 24 as an interlayer insulating film, An antireflection film 26 is deposited on the film 25.

  The SiCN film 24 functions as an etching stopper film when a via hole is formed in the SiOC film 25 in a later process. It also functions as a barrier film that prevents Cu from diffusing from the surface of the Cu wiring 22 into the interlayer insulating film. The SiCN film 24 is deposited by the plasma CVD method, and the film thickness is about 50 nm. The SiOC film 25 on the SiCN film 24 is deposited by the plasma CVD method, and the film thickness is about 770 nm. The relative dielectric constant of the SiOC film 25 is about 2.9.

  The antireflection film 26 on the SiOC film 25 is composed of a three-layer film of an SiO film 26a, an SiON film 26b, and an SiO film 26c, like the antireflection film 19 used in the step of forming the wiring trench 20, and is a plasma CVD apparatus. The film is continuously formed in the chamber. When the photoresist film formed on the antireflection film 26 is exposed in the next step, the antireflection film 26 causes the exposure light reflected by the surface of the lower Cu wiring 22 to enter the photoresist film and cause halation. It has a function to prevent this.

  FIG. 11 is a graph showing the results of measuring the light reflectance (%) of the antireflection film 26 using a KrF excimer laser (wavelength = 248 nm) as an exposure light source. Here, the horizontal axis indicates the thickness of the SiO film 26a, and the vertical axis indicates the total thickness of the SiON film 26b and the SiO film 26c (the thickness of the SiO film 26c is fixed to 5 nm). In the regions (A to E) in the figure, the light reflectance is A = 0 to 2%, B = 2 to 4%, C = 4 to 6%, D = 6 to 8%, E = 8 to 10 The area which becomes% is shown.

  According to the above measurement results, when the light reflectance required for preventing halation is 5% or less, the preferable combination of the film thickness of the SiO film 26a and the film thickness of the SiON film 26b is the film of the SiO film 26a. The thickness is 40 nm or less or 75 nm or more, and the thickness of the SiON film 26b is 40 nm or more. A more preferable combination is that the thickness of the SiO film 26a is 30 nm or less or 80 nm or more, and the thickness of the SiON film 26b is 50 nm or more. is there.

  Next, as shown in FIG. 12, a photoresist film 27 having an opening for forming a via hole is formed on the antireflection film 26. The via hole pattern is transferred from the photomask to the photoresist film 27 using a KrF excimer laser as an exposure light source. Here, the exposure light is reflected on the surface of the Cu wiring 22 by setting the film thicknesses of the SiO film 26a, the SiON film 26b, and the SiO film 26c constituting the antireflection film 26 within the above-described preferable combination range. It is possible to suppress halation of the photoresist film 27 due to the above, and to transfer the via hole pattern to the photoresist film 27 with high accuracy.

  Next, as shown in FIG. 13, via holes 28 are formed by dry etching the antireflection film 26 and the SiOC film 25 using the photoresist film 27 as a mask. At this time, the SiCN film 24 under the SiOC film 25 functions as an etching stopper film.

  Next, the photoresist film 27 is removed by plasma ashing, and then the polymer on the surface of the substrate 1 generated at the time of ashing is removed by wet cleaning. Then, as shown in FIG. Fill. The filling agent 29 is formed to prevent the diameter of the via hole 28 from expanding during etching when forming the wiring trench in the next step, and to protect the bottom of the via hole 28. As the embedding agent 29, a photoresist agent that absorbs exposure light is used. Also, a coating type insulating film having a low exposure light reflectance, such as a spin-on-glass film, can be used. In order to fill the via hole 28 with the filling agent 29, a photoresist film is spin-coated on the antireflection film 26 including the inside of the via hole 28 and cured, and then the photoresist film outside the via hole 28 is removed by etching back. To do.

  Next, as shown in FIG. 15, after forming the second antireflection film 30 on the antireflection film 26, a photoresist film 31 having an opening in the wiring groove formation region is formed on the antireflection film 30. . A wiring groove pattern is transferred from the photomask to the photoresist film 31 using a KrF excimer laser as an exposure light source. The antireflection film 30 uses a known antireflection agent called BARC (Bottom Anti Reflective Coating), or a coating-type insulating film having low exposure light reflectance. Here, since the antireflection films 30 and 26 are formed under the photoresist film 31, halation during exposure is suppressed, and the pattern of the wiring groove can be accurately transferred to the photoresist film 31. Further, since the antireflection film 30 is formed below the photoresist film 31, the lower layer of the photoresist film 31 can be planarized. In addition, when the halation at the time of exposure is sufficiently suppressed only by the antireflection film 26, the second antireflection film 30 may be omitted.

  Next, as shown in FIG. 16, the antireflection film 30 and the antireflection film 26 are sequentially dry-etched using the photoresist film 31 as a mask, and then the SiOC film 25 is dry-etched halfway to form a wiring trench. 32 is formed. At this time, since there is no etching stopper film in the middle of the SiOC film 25, the etching for forming the wiring groove 32 is performed by controlling the etching time of the SiOC film 25.

  In this embodiment, in order to reduce the capacitance between wirings, the interlayer insulating film is composed of the SiOC film 25 having a relative dielectric constant of about 2.9. However, no etching stopper film is formed in the middle of the SiOC film 25. As a result, an increase in the effective dielectric constant of the interlayer insulating film can be suppressed, and the capacitance between wirings can be reduced. Since the depth of the wiring trench 32 is considerably shallower than the depth of the via hole 28, the depth of the wiring trench 32 can be easily controlled without forming an etching stopper film in the middle of the SiOC film 25.

  Next, as shown in FIG. 17, the photoresist film 31 and the antireflection film 30 thereunder are removed by plasma ashing. At this time, the filling agent 29 filled in the via hole 28 is also removed.

  Next, after the polymer on the surface of the substrate 1 generated during ashing is removed by wet cleaning, the SiCN film 24 at the bottom of the via hole 28 is dry-etched to expose the surface of the Cu wiring 22 as shown in FIG.

  Next, as shown in FIG. 19, a barrier metal film 33a made of a thin TiN film of about 50 nm is deposited on the antireflection film 26 including the inside of the wiring trench 32 and the via hole 28 by a sputtering method. Subsequently, a thick Cu film 33b that completely fills the inside of each of the wiring trench 32 and the via hole 28 is deposited on the barrier metal film 33a by a sputtering method or an electrolytic plating method.

  Next, as shown in FIG. 20, the Cu film 33b and the barrier metal film 33a outside the wiring groove 32 are removed by a chemical mechanical polishing method, so that the second inside the wiring groove 32 and the via hole 28. A Cu wiring 33 of the layer is formed. At this time, the antireflection film 26 formed on the SiOC film 25 is also removed at the same time.

  Although illustration is omitted, after that, by repeating the steps described with reference to FIGS. 10 to 20, the third and subsequent Cu wirings are sequentially formed in the upper layer of the second-layer Cu wiring 33.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is useful when applied to a semiconductor integrated circuit device in which a multilayer Cu wiring is formed using a dual damascene method.

It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 1. FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 2. FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 3. It is the graph which showed the interface adhesive force of the upper and lower layers at the time of laminating | stacking two types of insulating films from which a composition differs in a critical peeling load. FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 4. FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 7. FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 8. FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 9; It is a graph which shows the result of having measured the light reflectivity of the antireflection film. FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 10; FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 12; FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 13; FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 15; FIG. 17 is a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 16; FIG. 18 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 17; FIG. 19 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 18; FIG. 20 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the semiconductor integrated circuit device following FIG. 19;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation groove 3 SiO film 4 P-type well 5 N-type well 6 Gate insulating film 7 Gate electrode 8 Side wall spacer 9 Co silicide film 11 N-type semiconductor region (source, drain)
12 p-type semiconductor region (source, drain)
13 Etching stopper film 14 Insulating film 15 Contact hole 16 Metal plug 17 SiCN film 18 SiOC film 19 Antireflection film 19a SiO film 19b SiON film 19c SiO film 20 Wiring groove 21 Photoresist film 22 Cu wiring 22a Barrier metal film 22b Cu film 24 SiCN film 25 SiOC film 26 Antireflection film 26a SiO film 26b SiON film 26c SiO film 27 Photoresist film 28 Via hole 29 Filler 30 Antireflection film 31 Photoresist film 32 Wiring groove 33 Cu wiring 33a Barrier metal film 33b Cu film Qn n Channel type MISFET
Qp p-channel MISFET

Claims (12)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming an insulating film mainly comprising a SiOC film on the main surface of the semiconductor substrate;
(B) forming an antireflection film comprising a laminated film of a first SiO film, a SiON film, and a second SiO film on the insulating film;
(C) forming a first photoresist film on the antireflection film;
(D) forming a via hole in the insulating film by etching the antireflection film and the insulating film using the first photoresist film as a mask;
(E) a step of filling the via hole with a filling agent after removing the first photoresist film;
(F) after the step (e), forming a second photoresist film on the antireflection film;
(G) etching the antireflection film and the insulating film in a region including the region where the via hole is formed using the second photoresist film as a mask, and stopping the etching in the middle of the insulating film; A step of forming a wiring trench in the insulating film,
(H) a step of embedding a metal film in the wiring trench and the via hole after removing the second photoresist film and the filling agent;
(I) A step of forming a wiring made of the metal film inside the wiring groove and the via hole by removing the metal film outside the wiring groove by a chemical mechanical polishing method.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising a step of forming a metal wiring under the insulating film prior to the step (a).   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the metal film is mainly made of copper.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein in the step (g), the etching is stopped in the middle of the insulating film by controlling an etching time.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the film thickness of the first SiO film is 40 nm or less or 75 nm or more, and the film thickness of the SiON film is 40 nm or more.   6. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein the film thickness of the first SiO film is 30 nm or less or 80 nm or more, and the film thickness of the SiON film is 50 nm or more.   2. The pattern of the via hole is transferred to the first photoresist film, and the pattern of the wiring groove is transferred to the second photoresist film using a KrF excimer laser as an exposure light source. A method of manufacturing a semiconductor integrated circuit device. (A) forming a first insulating film mainly comprising a SiOC film on the main surface of the semiconductor substrate;
(B) forming an antireflection film comprising a laminated film of a second insulating film, a third insulating film, and a fourth insulating film on the first insulating film;
(C) forming a first photoresist film on the antireflection film;
(D) forming a via hole in the first insulating film by etching the antireflection film and the first insulating film using the first photoresist film as a mask;
(E) after removing the first photoresist film, filling the via hole with a filling agent;
(F) after the step (e), forming a second photoresist film on the antireflection film;
(G) Using the second photoresist film as a mask, etching the antireflection film and the first insulating film in a region including the region where the via hole is formed, and etching the intermediate portion of the first insulating film Forming a wiring trench in the first insulating film by stopping
(H) after removing the second photoresist film and the burying agent, burying a metal film inside the wiring trench and the via hole;
(I) forming a wiring made of the metal film inside the wiring groove and the via hole by removing the metal film outside the wiring groove by a chemical mechanical polishing method. A device manufacturing method comprising:
The second and fourth insulating films have a higher light refractive index than the first insulating film, and the third insulating film has a higher light refractive index than the second and fourth insulating films. A method for manufacturing a semiconductor integrated circuit device.   9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein the second and fourth insulating films are SiO films, and the third insulating film is a SiON film.   9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, further comprising a step of forming a metal wiring under the first insulating film prior to the step (a).   9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein the metal film is mainly made of copper.   9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein in the step (g), the etching is stopped in the middle of the first insulating film by controlling an etching time.

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