JP2007115406A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce test time when defect check of a bit line or a sense amplifier is performed in a wafer test of a NAND flash memory, and furthermore extremely reduce the test time through parallel processing of a plurality of chips. <P>SOLUTION: In a wafer test of a NAND flash memory, when defect check of a bit line or a sense amplifier of a cell array in a memory chip is performed, output of an expectation register 42 holding expectation data being externally input is compared with output of latch circuits 41a, 41b, ..., 41n holding data read from the memory cell by a comparison circuit 43, and a result on whether they agree or not to each other is output. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a test facilitating circuit used for facilitating a test in a wafer state at the time of manufacturing, for example, detecting a defect in a bit line or a bit line potential sense amplifier. Used for non-volatile memory.

  As one of semiconductor memory devices, an EEPROM that can be electrically rewritten is known. In particular, a NAND cell type EEPROM in which a plurality of memory cells are connected in series to form a NAND cell is attracting attention as being capable of high integration. In addition, NAND cell groups that share the same word line and selection gate line are handled as one cell block. Usually, operations such as reading and writing are performed by selecting one of a plurality of blocks and selecting this block. Against. Further, the NAND cell type EEPROM is often configured as a flash memory (NAND Flash) that can be erased in batches in units of a predetermined block.

  In a NAND flash memory wafer test, one of the test items using a memory tester is a bit line defect check for detecting the presence or absence of a bit line defect. This test item cannot be omitted in the test because the detected defective bit line is replaced with a circuit called column redundancy.

  Bit line defect check items include open check (Open CHECK), short check (Short CHECK), and short check between adjacent sense amplifiers (S / A).

  For example, when performing an open check, if there is no open failure of the bit line, all sense latch circuits hold "L" data, and if there is an open failure, the sense latch circuit corresponding to the defective bit line is set to "H". Data is retained.

  If a defective bit line is detected and replaced with column redundancy, a check for each column is required. At this time, all the columns (for example, 2048 columns) of the memory cell array must be checked in order.

  Conventionally, when checking a bit line defect, a method of reading data from a sense latch circuit to a memory tester and making a determination is employed. Along with this, on the memory tester side, parallel processing cannot be performed for a plurality of chips on the wafer, leading to an increase in test time. Furthermore, since at least three items must be checked as described above regarding the bit line or sense amplifier defect check, the test time is greatly affected.

  As described above, when checking the bit line defect in the wafer test of the conventional NAND flash memory, the method of reading the data of the sense latch circuit to the memory tester and determining it is adopted, and the memory tester side uses a plurality of chips on the wafer. However, there is a problem that the parallel processing cannot be performed and the test time is increased.

  The present invention has been made to solve the above-described problems, and when performing a defect check of a bit line or a sense amplifier during a wafer test of a semiconductor memory, data read from the memory cell is not read to an external memory tester. It is an object of the present invention to provide a semiconductor integrated circuit that can detect a defect, can perform processing on a plurality of chips in parallel, and can significantly reduce a test time.

  A semiconductor integrated circuit of the present invention includes a memory cell array having a plurality of columns, a redundancy address register for storing an address corresponding to a defective column of the memory cell array, a read circuit for reading data in the memory cell array, A data holding circuit for latching data read by the reading circuit, an expected value register for holding expected value data inputted from the outside for one address, an output of the data holding circuit, and an output of the expected value register Comparing and outputting a match / mismatch result, and if the comparison results in the comparison circuit match, the address is incremented and the comparison circuit compares the latch data and expected value data for the next one address. Make a comparison, and if they do not match, the column is determined to be defective and is determined to be defective. It means for setting the address of the column redundancy address register, and wherein the means for replacing a defective column address the set in redundancy address register to the redundancy circuit.

  According to the semiconductor integrated circuit of the present invention, when performing a defect check of a bit line or a sense amplifier in a wafer test, it is possible to detect a defect without reading data to the outside (memory tester), thereby shortening the test time. The test time can be greatly shortened by parallel processing of a plurality of chips.

  Further, since expected value data can be freely input from the outside according to the test, there is an advantage that the degree of freedom of the test becomes very high.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment>
FIG. 1 is a block diagram showing an overall schematic configuration of a NAND flash memory according to the first embodiment of the present invention.

  A bit line control circuit 11 is provided for the memory cell array 10 to perform data read, data write, rewrite, write verify read, and erase verify read.

  The bit line control circuit 11 is mainly composed of a CMOS flip-flop, and includes a latch circuit serving as a sense amplifier for sense-amplifying the potential of the bit line and a data latch circuit for latching data for writing. Then, a sense operation for verify read after writing, a latch of rewrite data, and data transfer such as write data / read data to / from the data input / output control circuit 12 are performed.

  The data input / output control circuit 12 controls input / output of external input or internal output (write data, read data, etc.). The data input / output buffer (I / O buffer) 16 and the bit line The control circuit 11 is connected.

  The connection of the data input / output control circuit 12 is controlled by the output of a column decoder 13 that receives an address signal from an address buffer (address latch) 14 that receives an address input.

  A row decoder 15 is provided for controlling the control gate and the selection gate for the memory cell array 10, and a well for controlling the potential of the p-type well (or p-type substrate) in which the memory cell array 10 is formed. A potential control circuit 17 is provided. In addition, a source line control circuit 18 is provided to control the source line voltage Cell-Source in the cell array.

  A word line control circuit 19 for controlling the potential of the word line (control gate line) in the selected block and a row decoder power supply control circuit 30 for controlling the potential of the row decoder power supply are provided.

  Also, the high voltage for programming, intermediate voltage, high voltage for erasing, high voltage for reading, etc. are generated, and the p-type well (or p-type substrate) during the erasing operation or the word line / bit line during the writing operation A high voltage / intermediate voltage generation circuit 31 for supplying to a row decoder power supply or the like is provided.

  Further, a command latch 32 for latching command input from the outside, and a control circuit (command for outputting a control signal for controlling operations such as reading, writing, and erasing of the memory in accordance with the command latched by the command latch 32 Decoder) 33 is provided.

  FIG. 2 shows an equivalent circuit diagram of one NAND cell of the memory cell array 10 in FIG.

  The NAND cell 20 is connected in series so that a plurality of memory cells (in this example, eight memory cells M1 to M8) share a source and a drain, and the drain side and the source side are further connected to each other. Select gate transistors S1 and S2 are provided, respectively. Each of the memory cells M1 to M8 has a MOSFET structure in which a floating gate is formed on a semiconductor substrate via a gate insulating film, and a control gate is stacked thereon via an interlayer insulating film, and select gate transistors S1, S2 also has a MOSFET structure. A bit line is disposed on the substrate on which the element is formed via the CVD oxide film, and this bit line is in contact with one end of the selection gate transistor S1.

  In the memory cell array 10 in FIG. 1, NAND cells 20 as described above are arranged in a matrix. In this case, the selection gate transistor S1 on the drain side of the NAND cell is commonly connected to the bit line, and the selection gate transistor S2 on the source side is connected to the common source line (source line voltage Cell-Source).

  The control gates of the memory cells M1 to M8 are arranged in the row direction of the memory cell array as control gate lines (word lines) CG1, CG2,... CG8, and the gate electrodes of the selection gate transistors S1, S2 are the selection gate line SG1. , SG2 are arranged in the row direction of the memory cell array.

  FIG. 3 shows a part of an equivalent circuit of the memory cell array in FIG.

  A NAND cell group sharing the same word line or select gate line is called a cell block. For example, a region surrounded by a broken line in FIG. 4 is defined as one cell block. Normally, operations such as reading and writing are performed on this selected block by selecting one of the plurality of blocks.

  FIG. 4 is a block diagram schematically showing a connection relationship between a part of the existing circuit and the newly added test facilitating circuit in the NAND flash memory of FIG.

  In FIG. 4, the sense amplifier group 40, the address latch circuit 14, and the redundancy address register 45 are existing ones, and an expected value register 42 and a data comparison circuit 43 for holding expected value data input according to a test from the outside are provided. Newly added.

  The sense amplifier group 40 includes, for example, 8-bit sense amplifier / latch circuits 41a, 41b,..., 41n corresponding to each column, and data (read data or write data) is input for each externally input address. Data) can be retained.

  Here, the sense amplifier group 40 is commonly used in all the blocks (erase units), and shows a configuration assuming a case where a bit line failure check is performed on, for example, 2048 columns. Bit line defect check items include open check (Open CHECK), short check (Short CHECK), and short check between adjacent sense amplifiers (S / A).

  The expected value register 42 includes eight registers REG for one column. In the NAND flash memory of this example, the sense amplifier group 40 and the expected value register 42 can handle a plurality of bits at the same time.

  FIG. 5 schematically shows the connection relationship between some NAND cells 20 and the sense amplifier 21 in one cell block in the NAND flash memory in FIG.

  Reference numeral 27 denotes two adjacent bit lines in the odd-numbered column and the even-numbered column, each of which is connected to the NAND cell 20, and holds the write data or the read data so as to be shared by the two NAND cells 20. A sense amplifier / latch circuit 21 is connected.

  The nMOS transistor 22 is connected between the input node of the sense amplifier 21 and a predetermined power supply node VDD, and precharges the bit line 27 by being switch-controlled at a predetermined timing.

  The nMOS transistors 23 and 25 selectively connect the odd-numbered bit lines 27 to the sense amplifier 21 by being switch-controlled at a predetermined timing.

  The nMOS transistors 24 and 26 are controlled so as to selectively connect the bit lines 27 in even columns to the sense amplifier 21.

  A large number of sense amplifiers 21 and NAND cells 20 having the above-described connection relation are formed. In the NAND flash memory of this example, for example, eight sets of the sense amplifier 21 and the NAND cell 20 are read and written as one set. As a unit of load, that is, one column has a configuration of 8 bits.

  FIG. 6 shows a case where the bit line 27, the nMOS transistor (22, 23, 24, 25, 26) group and the sense amplifier (S / A) 21 in FIG. The situation is shown schematically.

  The nMOS transistor 22 and the nMOS transistor 23 or 24 on the bit line side to be subjected to open check are turned on, and the bit line 27 is charged. Thereafter, the charge path is turned off, the nMOS transistor 25 or 26 is turned on, and the bit line charge is discharged. Thereafter, the state of the bit line potential is taken into the latch circuit of S / A21.

  At this time, if there is no open failure of the bit line 27, all the S / A21 latch circuits hold "L" data, and the S / A21 latch circuit corresponding to the bit line with the open failure has "H" data. "Data is retained.

  At this time, if “L” data is held in advance in all the registers REG of the expected value register 42 in FIG. 4, the result of the open check is output by the comparison in the comparison circuit 43.

  FIG. 7 shows a test flow when performing the open check of the bit line as described above with reference to FIG. If a defective bit line is detected and replaced with column redundancy, an open check for each column is required.

  First, the expected value of the test result is input to the expected value register 42, and open check reading is performed. Here, the open check read indicates that after the bit line is charged, the discharge result is taken into the latch circuit of the sense amplifier.

  Since the open check must be performed for all columns, first set the column address to the test start address (usually address 0).

  After that, the data in the latch circuit of the sense amplifier is compared with the data held in the expected value register 42 for each column. If they match, the address is incremented to move to the next column. (FAIL) is determined and replaced with a redundancy circuit. Here, the address of the defective column is set in the redundancy address register 45. At this time, if all the redundancy circuits are used for defect remedy, this memory chip is determined as FAIL and the process ends. If there is no column that has not been replaced by the redundancy circuit even if the column address has advanced to the final address, a pass (PASS) is made.

  As described above, in the NAND flash memory of this example, when checking a bit line or sense amplifier for defects in a wafer test, the output of the latch circuit of the sense amplifier holding the read data and the external input By comparing the output of the expected value register 42 holding the expected value data, a defect can be detected without reading the data to the outside (memory tester).

  In this case, since all processing can be performed inside the chip, it is possible not only to shorten the time for reading data to the memory tester as in the prior art, but also to greatly reduce the test time by parallel processing of a plurality of chips. Further, since the expected value register 42 can set data freely according to the test, the degree of freedom of the test is expanded.

<Second Embodiment>
FIG. 8 is a block diagram schematically showing a connection relationship between a part of existing circuits and a newly added test facilitating circuit in the NAND flash memory according to the second embodiment of the present invention.

  The NAND flash memory according to the second embodiment is different from the NAND flash memory according to the first embodiment described above in that it further includes a control circuit 70, and the others are the same. The same parts as those in FIG. 4 are denoted by the same reference numerals.

  The control circuit 70 is connected between the expected value register 42 and the comparison circuit 43, and cascades an inverter circuit 71 and a first clocked inverter circuit 72 that is driven and controlled by complementary clock signals A, / A. A connected positive phase circuit and a second clock connected in parallel to the positive phase circuit and driven in a complementary manner to the first clocked inverter circuit 72 by complementary clock signals A, / A. And an inverter circuit consisting of an inverter circuit 73.

  According to this control circuit 70, it is possible to invert part or all of the output of the expected value register 42 by driving and controlling the positive phase circuit or the inverting circuit as necessary.

  FIG. 9 is a diagram showing an example of the arrangement of sense amplifiers (indicating the I / O numbers of the corresponding columns) in the NAND flash memory of FIG.

  As described above, when the sense amplifier group corresponding to the even-numbered column of the 2048 columns and the sense amplifier group corresponding to the odd-numbered column are arranged adjacent to each other as shown in FIG. As shown in the figure, it is necessary to set (load) the write data so that the held data of “1” or “0” of each sense amplifier has a different checkerboard pattern in the adjacent sense amplifiers.

  When performing a short check between adjacent sense amplifiers, if the column address is an odd number, the complementary clock signals A and / A are set to "L" / "H" to drive the inversion circuit of the control circuit 70. The output of the value register 42 is inverted and supplied to the comparison circuit 43.

  On the other hand, when the column address is an even number, the output of the expected value register 42 is obtained by driving the positive phase circuit of the control circuit 70 by setting the complementary clock signals A and / A to "H" / "L". Is supplied to the comparison circuit 43 in the positive phase.

  Therefore, as shown in FIG. 9, the check data between the adjacent sense amplifiers can be checked between the adjacent sense amplifiers by comparing the check data stored in the checkered pattern loaded in the sense amplifier and the expected value data.

<Third Embodiment>
FIG. 10 is a block diagram showing an overall schematic configuration of a NAND flash memory according to the third embodiment of the present invention.

  Compared with the NAND flash memory of the first embodiment described above, the NAND flash memory of FIG. 10 inputs the expected value register 42 in accordance with an external clock (clock) that controls the operation of reading data from the sense amplifier. Since the values are different and the others are the same, the same parts as those in FIG.

  FIG. 11 is a circuit diagram showing an example of one register 90 extracted from the expected value register 42 in FIG.

  The register 90 is composed of a D flip-flop, and operates so as to capture external input data in synchronization with an external clock.

  Test pattern for bit line defect check in wafer test for NAND flash memory is not only when the expected value is all "L" or all "H" but also a specific test pattern is input according to the address There are also cases where it is necessary to do so. In this case, as shown in FIG. 10, the value input to the expected value register 42 is changed according to the external clock, and the data read sequentially from the sense amplifiers 41a, 41b,..., 41n are synchronized with the external clock. Then, it can be compared with arbitrary expected value data for all columns.

  As a result, even when arbitrary data is written, comparison can be performed by inputting the same data again, so that it is possible to cope with all cases of defect checks on the bit lines and sense amplifiers.

<Modification of Third Embodiment>
In the third embodiment described above, the expected value register 42 is omitted, the expected value data input to the comparison circuit 43 is changed according to the external clock, and the data read in order from the sense amplifiers 41a, 41b,. If it is made to synchronize with, it can compare with arbitrary expected value data with respect to all the columns.

  According to such a modification, the expected value register 42 can be omitted, so that the circuit configuration can be simplified as compared with the third embodiment.

  The present invention is not limited to the NAND cell type memory described above, but can be applied to a semiconductor integrated circuit equipped with a NOR cell type memory, a DINOR cell type memory, an AND cell type memory, or the like.

1 is a block diagram showing an overall schematic configuration of a NAND flash memory according to a first embodiment of the present invention. FIG. 2 is an equivalent circuit diagram showing one NAND cell portion of the memory cell array in FIG. 1. FIG. 2 is an equivalent circuit diagram showing a part of the memory cell array in FIG. 1. FIG. 2 is a block diagram schematically showing a connection relationship between a part of an existing circuit and a newly added test ease circuit in the NAND flash memory of FIG. 1. The figure which shows typically the connection relation of a part of NAND cell and a part of sense amplifier in one cell block in the NAND type flash memory in FIG. FIG. 6 is a diagram schematically showing a state in which the bit line, nMOS transistor group, and sense amplifier in FIG. 5 are taken out and a bit line open check is performed. The figure which shows the test flow at the time of performing the bit line open check shown in FIG. FIG. 5 is a block diagram schematically showing a connection relationship between a part of existing circuits and a newly added test facilitating circuit in a NAND flash memory according to a second embodiment of the present invention. FIG. 9 is a diagram illustrating an arrangement example of sense amplifiers in the NAND flash memory of FIG. 8. FIG. 9 is a block diagram schematically showing a connection relationship between a part of existing circuits and a newly added test facilitating circuit in a NAND flash memory according to a third embodiment of the present invention. FIG. 11 is a circuit diagram illustrating an example of one of the expected value registers in FIG. 10 taken out.

Explanation of symbols

40 ... sense amplifier group, 42 ... expected value register, 43 ... data comparison circuit, 45 ... redundancy address register.

Claims (6)

A memory cell array having a plurality of columns;
A redundancy address register for storing an address corresponding to a defective column of the memory cell array;
A read circuit for reading data in the memory cell array;
A data holding circuit for latching data read by the read circuit;
An expected value register holding expected value data input from the outside for one address;
A comparison circuit that compares the output of the data holding circuit with the output of the expected value register and outputs a match / mismatch result;
If the comparison results in the comparison circuit match, the address is incremented and the comparison circuit compares the latch data for the next one address with the expected value data. If they do not match, the column is determined to be defective. And means for setting the address of the column determined to be defective in the redundancy address register,
Means for replacing a defective column of an address set in the redundancy address register with a redundancy circuit. A memory cell array having a plurality of columns;
A redundancy address register for storing an address corresponding to a defective column of the memory cell array;
A read circuit for reading out data in the memory cell array for each column according to an address;
A data holding circuit for latching data for one column read by the read circuit;
An expected value register holding expected value data for one column input from the outside;
A comparison circuit that compares the output of the data holding circuit with the output of the expected value register and outputs a match / mismatch result;
If the comparison results in the comparison circuit match, the address is incremented to read the next one column of data in the memory cell array into the read circuit, and the comparison circuit expects the next one column of latch data. Means for performing comparison with the value data, if the data does not match, the column is determined to be defective, and the address of the column determined to be defective is set in the redundancy address register;
Means for replacing a defective column of an address set in the redundancy address register with a redundancy circuit.   3. The semiconductor integrated circuit according to claim 1, wherein a plurality of the data holding circuits are provided and hold data for each address inputted from the outside.   4. The semiconductor integrated circuit according to claim 3, further comprising a control circuit capable of inverting a part or all of the output of the expected value register. The expected value register can capture expected value data input from outside at any time by an external clock,
5. The semiconductor integrated circuit according to claim 1, wherein the data holding circuit is capable of sequentially outputting the held data in synchronization with the external clock. 6.   6. The semiconductor integrated circuit according to claim 1, wherein NAND cells are arranged in a matrix in the memory cell array.

Images