JP2007110265A - Decoding apparatus and decoding method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a decoding apparatus with a reduced circuit scale using a low density parity check code suitable for correcting an error caused in a transmission path for high speed transmission of data and to provide a decoding method. <P>SOLUTION: A check matrix is configured as a set of a plurality of partial matrices the number in the column direction of which is an integer twice the number of column weights and the number in the row direction of which is an integer equal to the number of row weights, wherein the column weight is the number of elements in one column whose value is "1", and the row weight is the number of elements in one row whose value is "1", the row weight of the partial matrices is configured to be all "1", and the sum of the column weight of the (2r-1)th partial matrix and the 2r-th partial matrix (wherein r is a column weight number) which are consecutive in the column direction of the check matrix is configured to be all "1". First and second storage means respectively store row processing arithmetic data and column processing arithmetic data by each same row weight number and each same column weight number as to the elements whose value is "1" in the check matrix. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a decoding apparatus and a decoding method, and more particularly, to a decoding apparatus and a decoding method suitable for correcting errors that occur in a transmission line that performs high-speed transmission of low-density parity check code data.

  The demand for communication fields such as mobile communication typified by mobile phones and wireless LANs has been advanced, and development and research for that purpose have been rapidly advanced. In particular, in these fields, higher data transfer rates are required. Since transmission lines that perform high-speed data transmission are prone to errors, development and research of error correction techniques that perform error detection and correction using a low-density parity check code and the like are being actively conducted.

  In general, in such a communication system, information data to be transmitted is encoded by a generator matrix and further transmitted after modulation. The received codeword is demodulated and then decoded by a check matrix to be restored to information data.

  The low density parity check (LDPC) code used here refers to a linear code defined by a check matrix having very few “1” elements. In addition, although the LDPC code is not limited to binary, in the following description, a binary LDPC code is used for simplification.

  The decoding characteristics obtained by the combination of the LDPC code and the sum-product decoding method are comparable to the performance of the turbo code, and rather better when the code length is long. That is, when the code length is long, performance very close to the Shannon limit, which is the limit of the frequency utilization efficiency (bit / second / Hz), can be obtained. This “Shannon limit” is determined by the frequency band of the transmission line and Eb / No (the power density per bit to noise power density ratio is expressed in dB). Other advantages of the LDPC code include flexibility to configure various code lengths and coding rates, good block error rate characteristics, and low error floor phenomenon.

By the way, for decoding using the parity check matrix, a decoding device including an arithmetic circuit, a memory circuit, etc. is used (for example, Patent Document 1). As system requirements become higher, the memory circuit scale for temporarily storing operation data increases. In order to reduce the circuit scale, a RAM (Random Access Memory) is more suitable as a memory circuit than a register.
JP 2004-364233 A

  However, when RAM is used, data rearrangement is required when accessing the check matrix. In order to perform data rearrangement, since a multi-input selection circuit is required, the circuit scale is not sufficiently reduced as it is, and the size of the decoding device is increased, the processing speed is decreased, and the power consumption is increased. There is room for improvement.

  The present invention has been made on the basis of recognition of such a problem, and an object of the present invention is to achieve a low-density circuit with a reduced circuit scale suitable for correcting an error occurring in a transmission line for performing high-speed data transmission. An object of the present invention is to provide a parity check code decoding apparatus and decoding method.

According to the present invention, a row processing arithmetic circuit that performs a row processing operation using a check matrix that performs error correction of a received word;
A column processing arithmetic circuit for executing column processing arithmetic using the check matrix for performing error correction of a received word; first storage means for storing row processing arithmetic data by the row processing arithmetic circuit; and the column processing arithmetic circuit. A second storage means for storing column processing calculation data, wherein the parity check matrix is divided by a multiple of a column weight in the column direction and a set of a plurality of submatrices divided by the number of row weights in the row direction The row weights of the sub-matrices are all set to 1, and the column weight of the (2r-1) -th sub-matrix and the 2r-th sub-matrix (provided that r is a column weight number) and the total column weights are all set to 1, and the first storage means sets the element of “1” of the parity check matrix for each of the same row weight number and the same column weight number. Storing the row processing operation data; The second storage means stores the column processing calculation data for each of the same row weight number and the same column weight number for the element “1” of the parity check matrix, and the row processing calculation circuit includes the second storage means. The column processing operation data read from the column processing data is used for parallel processing of column processing twice the column weight, and the operation data is written to the first storage unit for each row weight number and column weight number. The column processing arithmetic circuit performs the parallel processing of the column processing calculation for the number of row weights using the row processing calculation data read from the first storage means, and calculates the calculation data for each column weight number and row weight number. A low density parity check code decoding apparatus is provided, wherein the low density parity check code is written to each of the second storage means.
According to this decoding apparatus, the parity check matrix is divided into a multiple of column weights in the column direction and configured as a set of a plurality of submatrices divided in the row direction by the number of row weights. The weights are all 1, and the sum of the column weights of the (2r-1) th submatrix and the column weights of the 2rth submatrix that are continuous in the column direction is all 1.
The row processing operation circuit and the column processing operation circuit execute a row processing operation and a column processing operation that perform error correction of the received word using this check matrix, respectively, and the results are used as row processing operation data and column processing operation data. The first storage means and the second storage means are written for each row weight number and column weight number. In the first storage means and the second storage means, the row processing calculation data and the column processing calculation data are stored for each of the same row weight number and the same column weight number for the element “1” of the parity check matrix. Yes.
Here, the row processing arithmetic circuit reads the column processing arithmetic data from the second storage means, and performs parallel processing of the row processing arithmetic twice the column weight. At this time, since the column processing calculation data is written in the second storage means for each row weight number and column weight number by the column processing calculation circuit, the second processing means does not rearrange the data in the row processing calculation circuit. Column processing operation data necessary for row processing can be read out from the.
In addition, the column processing arithmetic circuit reads out the row processing arithmetic data from the first storage means and performs the parallel processing of the column processing arithmetic of the row weight number. At this time, the row processing arithmetic data is also processed by the row processing arithmetic circuit. Since each column weight number is written in the first storage means, the row processing calculation data necessary for the column processing can be read from the first storage means without rearranging the data.
As described above, since the row processing operation and the column processing operation can be performed in parallel without rearranging the data, the conventionally required selection circuit can be omitted, and the circuit scale can be reduced.

Further, according to the present invention, a plurality of parts formed by dividing the row by the number of row weights in the row direction and dividing the row by the number of row weights in the row direction as a check matrix for error correction of received words A set of matrices, wherein the row weights of the sub-matrices are all set to 1, and the column weight of the (2r-1) th sub-matrix and the 2r-th sub-matrix that are continuous in the column direction of the parity check matrix (Where r is the column weight number) and the total of the column weights is set to 1, and a set of a plurality of sub-matrices is used, and the operation data initialized by inputting the received word data is the first A first step of writing to the storage means for each row weight number and column weight number, and reading the column processing operation data stored in the second storage means for the element “1” of the parity check matrix; By parallel processing of twice the column weight A second step of performing a processing operation and writing the operation data to the first storage unit for each row weight number and column weight number, and storing the element of “1” in the parity check matrix in the first storage unit The row processing calculation data read out, column processing calculation is performed by parallel processing of the number of row weights, and the calculation data is written in the second storage means for each row weight number and column weight number. A third step of calculating a temporary estimated word using calculation data, a fourth step of repeating the second step and the third step a predetermined number of times in this order;
A low-density parity check code decoding method is provided.
According to this decoding method, the parity check matrix is divided as a multiple of the column weights in the column direction and is configured as a set of a plurality of submatrices divided by the number of row weights in the row direction. The weights are all 1, and the sum of the column weights of the (2r-1) th submatrix and the column weights of the 2rth submatrix that are continuous in the column direction is all 1.
First, in the first step, the received word data is written to the second storage means as initialized column processing calculation data. At this time, the initialized column processing calculation data is stored in the second storage unit for each identical row weight number and identical column weight number. Thereby, in the next second step, the column processing calculation data is read from the second storage means without rearranging the data, and the row processing of twice the column weight number is performed for the element “1” of the check matrix. Operations can be processed in parallel.
Then, the parallel processing result of the second step is stored in the first storage unit for each of the same row weight number and the same column weight number as row processing calculation data. As a result, in the next third step, the row processing calculation data is read from the first storage means without rearranging the data, and the column processing calculation of the row weight number is performed in parallel on the element “1” of the check matrix. It can be processed. In addition, the temporary estimated word can be calculated using the row processing calculation data read from the first storage means.
Then, the parallel processing result in the third step is stored in the second storage means for each of the same row weight number and the same column weight number as column processing calculation data. Thereby, after that, even if the parallel processing of the row processing operation and the column processing operation is repeatedly executed a predetermined number of times (fourth step), the data need not be rearranged.
In this way, in the parallel processing of the row arithmetic processing and the column arithmetic processing, it is not necessary to rearrange the data, so that the conventionally required selection circuit can be omitted, and the circuit scale can be reduced.

In addition, according to the present invention, a row processing arithmetic circuit that performs a row processing operation using a check matrix that performs error correction on a received word, and a column processing operation that uses the check matrix that performs error correction on a received word. Column processing arithmetic circuit, first storage means for storing row processing arithmetic data by the row processing arithmetic circuit, second storage means for storing column processing arithmetic data by the column processing arithmetic circuit, and the first storage means A selection circuit that selects and outputs one of the two data stored in the check matrix, and the parity check matrix is divided by a multiple of the column weight in the column direction and the number of row weights in the row direction. The column weights of the (2r-1) th submatrix and the 2rth submatrix that are configured as a set of a plurality of divided submatrices and continuous in the column direction of the parity check matrix (where r is all column weight numbers) The total column weights 1 and the sum of the row weights of two sub-matrices continuous in the row direction among the plurality of sub-matrices is all 2, and the first storage means includes the parity check matrix The row processing calculation data is stored for each of the same row weight number and the same column weight number for the element of “1”, and the second storage means stores the same row weight number for the element of “1” of the parity check matrix. The column processing calculation data is stored for each column weight number, and the row processing calculation circuit uses the column processing calculation data read from the second storage means to perform a row processing calculation of twice the column weight. Parallel processing is performed, and operation data is written to the first storage unit for each row weight number and column weight number, and the column processing operation circuit selects the row processing operation data selected and output by the selection circuit. Use line weight There is provided a low-density parity check code decoding apparatus, wherein the number of column processing operations are processed in parallel, and the operation data is written in the second storage means for each column weight number and row weight number. .
2. The decoding apparatus according to claim 1, wherein the sum of the row weights of two sub-matrices in which the parity check matrix is continuous in the row direction is all 2, and has a higher degree of freedom than the parity check matrix in the decoding apparatus according to claim 1. Making the design easier.
By using the check matrix having such a configuration, in order to perform the column processing calculation of the row weight number in parallel in the column processing calculation circuit, the row processing necessary for the column processing calculation from the first storage means is performed by the selection circuit. The arithmetic data is selected, that is, the data must be rearranged. However, in order to perform the row processing operation of twice the column weight in parallel in the row processing arithmetic circuit, the data as in the decoding device according to claim 1 is used. There is no need to rearrange.
As a result, the selection circuit only needs to be provided for column processing operation, and the number of selection circuits required than before can be reduced, and the circuit scale can be reduced.

Further, according to the present invention, a plurality of parts formed by dividing the row by the number of row weights in the row direction and dividing the row by the number of row weights in the row direction as a check matrix for error correction of received words A set of matrices, the column weights of the (2r-1) th submatrix and the 2rth submatrix (where r is a range of all column weight numbers) consecutive in the column direction of the parity check matrix Of the plurality of sub-matrices configured such that the sum of the row weights of two sub-matrices consecutive in the row direction is all 2 among the plurality of sub-matrices. Using sets,
A first step of writing operation data initialized by inputting received word data into the second storage means for each row weight number and column weight number, and for the element “1” of the parity check matrix The column processing calculation data stored in the second storage means is read out, row processing calculation is performed by parallel processing of twice the column weight, and the calculation data is respectively stored in the first storage means for each row weight number and column weight number. For the second step of writing to the element and the “1” element of the parity check matrix, one of the two row processing calculation data stored in the first storage means is selected and read, and the number of row weights Column processing calculation is performed by parallel processing, and calculation data is written to the second storage unit for each row weight number and column weight number, and a temporary estimated word is calculated using the row processing calculation data. 3 and step, low density parity check decoding process of a code characterized by comprising a fourth step of repeating a predetermined number of times and said third step and said second step in this order is provided.
5. In this decoding method, the sum of row weights of two sub-matrices in which the parity check matrix is continuous in the row direction is all 2, and the degree of freedom is higher than that of the parity check matrix in the decoding method according to claim 4. Making the design easier.
By using the check matrix having such a configuration, in order to perform the column processing calculation of the row weight number in the third step in parallel, the row processing calculation data necessary for the column processing calculation is selected from the first storage means. That is, data rearrangement is required. However, in order to perform parallel processing of row processing twice the column weight in the row processing operation of the second step, data rearrangement is not required as in the fourth aspect. is there.
As a result, the selection circuit need only be provided for column processing operations, and the number of selection circuits required can be reduced as compared with the conventional case, and the circuit scale can be reduced.

  According to the present invention, there is provided a low-density parity check code decoding apparatus and decoding method with a reduced circuit scale, suitable for correcting errors occurring in a transmission path for high-speed data transmission.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram of a low density parity check (LDPC) code decoding apparatus 24 according to a first specific example of the present invention. The received word data passes through the serial-parallel conversion circuit 52 and the input buffer 54, and is input to the column processing arithmetic circuit 44 and the temporary estimated word arithmetic circuit 50 controlled by the received word valid signal input to the control unit 40.

  The column processing calculation data calculated by the column processing calculation circuit 44 is written in the second storage means 46 by parallel processing (however, the first time is an initialization step). The row processing arithmetic circuit 42 reads the data in the second storage means 46 by parallel processing and performs row processing arithmetic. The row processing calculation data is written to the first storage means 48 by parallel processing.

  After the row processing operation and the column processing operation are repeated a predetermined number of times, the temporary estimation word calculation circuit 50 calculates the temporary estimation word and decodes it via the output buffer 56 and the parallel-serial conversion circuit 58. Retrieved as word data.

  FIG. 2 is a block diagram showing a receiver in which the decoding device 24 of this specific example illustrated in FIG. 1 is incorporated. This receiver is used, for example, for mobile wireless devices such as mobile phones and PDAs (Personal Digital Data Assistants). The signal received by the antenna 20 is demodulated by the demodulation circuit 22 and decoded by the decoding device 24 according to this specific example.

  Further, the receiver includes a video / audio signal processing circuit 28 that processes data such as a decoded video signal and audio signal, and a CPU (Central Processing Unit) 26 that controls the decoding device 24 and the video / audio signal processing circuit 28. , A speaker 34 for generating a signal-processed audio signal to the outside, a monitor 32 for displaying the signal-processed video signal, and the like.

  Next, the parity check matrix used for decoding the LDPC code according to this example will be described in detail. FIG. 3 shows a basic configuration of the parity check matrix 10 represented by H used in this specific example. The parity check matrix 10 includes M rows × N columns. Further, the row is divided into Pm pieces, and the column is divided into Pn pieces. As a result, the parity check matrix 10 is configured with (M / Pm) rows × (N / Pn) columns, and is handled as Pm × Pn sub-matrices 12 represented by Hsub [i] [j]. Can do. Here, since Pm is an integer obtained by doubling the column weight, it is an even value. Also, Pn is the same integer as the row weight.

  Further, in this specific example, the (2r−1) th and odd 2rth (where r = 1, 2,..., Pm / 2) submatrix Hsub [ 2r-1] [c] and Hsub [2r] [c] (where c = 1, 2,..., Pn), the sum of column weights is 1. On the other hand, the row weight in each submatrix is set to 1. The row weight represents the number of “1” elements in one row. Similarly, the column weight represents the number of “1” elements in one column.

  FIG. 4 is a diagram illustrating an example of the submatrix 12 more specifically. Each element of the two sub-matrices 12 represented by Hsub [2r-1] [c] and Hsub [2r] [c] that are continuous along the column direction is illustrated. Hereinafter, “continuous along the column direction” is expressed as “continuous vertically”. Each row weight is set to 1, and the number of columns is set to N / Pn. Also, the column weight is 1 in any column of the two sub-matrices, and the sum of the column weights of the two vertically continuous sub-matrices is 1.

Next, a Tanner graph necessary for understanding an arithmetic expression for performing error detection and error correction using such a check matrix 10 will be described.
FIG. 5 is a Tanner graph in a parity check matrix of M rows × N columns, and is composed of N bit nodes (represented by ◯ marks) and M check nodes (represented by □ marks). In the parity check matrix, the nodes corresponding to the row and column of the element “1” are connected by a line. The decoding of the LDPC code is performed by repeatedly exchanging a log likelihood ratio (LLR) which is a message between a bit node and a check node in such a Tanner graph.

Next, calculation steps performed using such a Tanner graph will be described. An element in the parity check matrix 10 is represented as Hmn, a set N (m) of column numbers having an element “1” in the m-th row, and a set M of row numbers having an element “1” in the n-th column ( n) is defined as follows.

N (m) = {n: Hmn = 1}
M (n) = {m: Hmn = 1}

Further, a message sent from the bit node to the check node is defined as Zmn, and a message sent from the check node to the bit node is defined as Lmn. Further, a message from the received word is defined as yn.

  First, FIG. 6 is a Tanner graph showing exchange between nodes in the row processing calculation. The message Lmn1 passed from the check node m to the bit node N (m) = n1 is a bit node connected to the check node m other than the bit node n1 to which the message is passed -It is calculated from the messages (Zmn2, Zmn3, ...) from the nodes. An example of the arithmetic expression at this time is shown below.

ｔａｎｈ関数を用いた演算式は、ｓｇｎ関数のｐｒｏｄｕｃｔとｍｉｎ関数との積として近似することができる。

An arithmetic expression using the tanh function can be approximated as a product of the product of the sgn function and the min function.

  Here, the sgn function is expressed by the following equation (2). The arithmetic expression is not limited to the expression (1), and may be, for example, Gallager's f function.

  FIG. 7 is a Tanner graph showing exchanges between nodes in the column processing operation. The message Zm1n passed from the bit node n to the check node m1 is a message from a check node other than the check node m1 to which the message is passed among the check nodes linked to the bit node n. (Lm2n, Lm3n,...) An arithmetic expression at this time is shown below.

  Zmn is represented by the sum of the sum of Lm′n and the received word yn. The LDPC code decoding process is also referred to as a “sum-product decoding method” because the above process is repeated. In this case, the time complexity is linear time with respect to the code length, and since this decoding algorithm is essentially a parallel algorithm, it is suitable for a parallel and distributed hardware implementation.

Next, the flow of decoding processing will be described.
FIG. 8 is a flowchart showing the decoding method according to this example. First, a code word is received (S100). Next, a counter T for counting the number of iterations is initialized to T = 1, and all elements with Hmn = 1 are initialized to Zmn = yn using the received word yn (S102). More specifically, all input data from the first storage means 48 to the column processing arithmetic circuit 44 is set to “0”. In this way, the output from the column processing arithmetic circuit 44 is only the received word yn, and the data in the second storage means 46 can be initialized to the received word.

  Next, the column processing calculation data is read from the second storage means 46, the row processing calculation is performed in parallel with a multiple of the column weight, and the bit ··· from the check node corresponding to the element “1” in the check matrix 10 The operation data passed to the node is stored in the first memory element group constituting the first storage means 48 for each row weight number and column weight number. This row processing operation is executed for all m and n using equation (1) (S104). In the following, “row processing” includes reading column processing operation data, row processing operation, and writing to the first storage means. The “row weight number” is a number assigned from 1 to the element “1” in the same row of the parity check matrix in ascending order of the column number of the element. Similarly, the “column weight number” is a number assigned from 1 to the element “1” in the same column of the parity check matrix in ascending order of the row number of the element.

  Next, the row processing operation data is read from the first storage means 48, the column processing operation is performed in parallel with the number of row weights, and from the bit node to the check node corresponding to the element “1” in the check matrix. The passed calculation data is stored in the second memory element group constituting the second storage means 46 for each row weight number and column weight number. This column processing operation is executed for all m and n using equation (3). Further, the calculation of the temporary estimated word cn is executed for all m and n using the equation (4) (S106). In the following, “column processing” includes reading of row processing operation data, column processing operation, and writing to the second storage means.

次に、反復回数判定を行う（Ｓ１０８）。ここでカウンタＴ＜ｉｔであれば、カウンタＴをインクレメントして、行処理演算を行うステップＳ１０４へ戻る。この繰り返しサイクルは、Ｔ＝ｉｔとなるまで継続される。ここで、例えば，ｉｔ＝５０とすることができるがこれに限定される必要はなく、収束が早ければｉｔはより小であっても良い。Ｔ＝ｉｔで復号処理は終了する（Ｓ１１０）。

Next, the number of iterations is determined (S108). Here, if the counter T <it, the counter T is incremented and the process returns to step S104 where the row processing calculation is performed. This repeated cycle continues until T = it. Here, for example, it can be set to 50, but it is not necessary to be limited to this, and it may be smaller if convergence is quick. The decoding process ends when T = it (S110).

Finally, the temporary estimated word cn subjected to error correction is obtained.
Here, it returns to the decoding apparatus 24 illustrated in FIG. 1 again, and it demonstrates supplementarily regarding the component. The received word data is first input to the S / P circuit 52 that performs serial-parallel conversion. The input buffer 54 includes a memory that stores received words. The input buffer 54 is configured to be able to simultaneously output a plurality of data necessary for the column processing operation from one received word so that parallel processing can be performed in the column processing operation. Specifically, the data is rearranged when writing to the input buffer.

The output buffer 56 is configured by a memory that stores temporary estimated word calculation data. This temporary estimated word is input to the P / S circuit 58 that performs parallel-serial conversion. The control unit 40 controls operations of the input buffer 54, the first storage unit 48, the second storage unit 46, the row processing arithmetic circuit 42, the column processing arithmetic circuit 44, the output buffer 56, and the like.
Note that the total number of bits of data required for the row processing operation is
Quantization bit number x row weight x Pm (twice the column weight)
It is expressed as

The total number of bits of data read from the first storage means 48 required for the column processing calculation is
Quantization bit number x column weight x Pn (row weight)
It is expressed as

Furthermore, the total number of bits of read data from the first storage means 48 required for the temporary estimated word calculation is
Quantization bit number x column weight x Pn (row weight)
It is expressed as

Further, the total number of bits of read data from the input buffer 54 is
Quantization bit number x Pn (row weight)
It is expressed as

  Next, data transfer executed between the row processing arithmetic circuit 42, the first storage means 48, the column processing arithmetic circuit 44, and the second storage means 46 will be described in more detail. Here, as a memory element group constituting the first storage unit 48 and the second storage unit 46, for example, a dual port RAM can be used.

  FIG. 9 is a diagram showing an example of the configuration of stored data when the dual port RAM 60 which is a dual port memory is used as a memory element group of the storage means. The configuration of this stored data is (2r-1) th and 2rth (where r = 1, 2,...) Along the column of the partial matrix 12 constituting the parity check matrix 10 illustrated in FIG. , Pm / 2) to correspond to a set of matrices. That is, each of the two sub-matrices combined can have a row weight of 1 and a column weight of 1.

  As a result, each dual port RAM 60 can store the calculation result corresponding to the element “1” of the submatrix having the row weight 1 and the column weight 1. Therefore, the first storage means 48 and the second storage means 46 are composed of Pn × Pm / 2 dual port RAMs 60. In FIG. 9, Pn is matched with the row weight, and Pm / 2 is matched with the column weight. In this specification, the position is represented by the expression RAM [j] [k], k is a “row weight number”, and j is a “column weight number”. Although not shown, each port of the dual port RAM 60 is used to access each element of the submatrix 12 illustrated in FIG. Further, the calculation data can be stored in the dual port RAM 60 in the order of row numbers.

  Next, the case where the row weight of the parity check matrix H is 7 (meaning Pn = 7) and the column weight is 3 (means Pm = 6) will be described more specifically. Here, the flow of the decoding method is assumed to follow the flowchart illustrated in FIG.

  FIG. 10 is a block diagram showing the connection between the storage means and the row processing arithmetic circuit 42 in the row processing arithmetic step (S104). In the row processing calculation, first, necessary data is read from the second storage means 46. In this case, data corresponding to the element “1” in the same row of the parity check matrix is required. In this specific example, since the row weight is 7, 7 pieces of data (corresponding to the number of bit nodes) are required per row. FIG. 6 illustrates seven bit nodes. In addition, since 6 parallel processing, which is twice the column weight 3, is performed in the row processing, 7 × 6 (rows) = 42 pieces of data are required.

  The data for one row is stored in the corresponding dual port RAM 47 of the second memory element group in the order of the row weight number (k). Since this data is stored in the order of row numbers, seven data can be read out in parallel by one access by giving the same address indicating the row number to all seven dual port RAMs. Further, since the second storage means 46 is also a dual port RAM, two rows of data can be read simultaneously.

  Furthermore, by arranging this dual port RAM configuration in the same number as three column weights, 7 × 6 (rows) = 42 data can be read simultaneously. Thus, the read column processing data is input to the row processing arithmetic circuit 42 for each row. In this case, the row processing arithmetic circuit 42 is also arranged in six parallels, so that the row processing arithmetic for six rows can be processed in parallel.

  The operation data in the row processing operation circuit 42 is written to the dual port RAM 49 constituting the first storage means 48. 42 pieces of calculation data can be written in one access by 6 parallel processing.

  FIG. 11 is a block diagram showing the connection between the storage means and the column processing arithmetic circuit in the column processing arithmetic step (S106). In the column processing calculation, first, necessary data is read from the first storage unit 48. In this case, data corresponding to the element “1” in the same column of the parity check matrix is necessary. In this specific example, since the column weight is 3, three data (corresponding to the number of check nodes) are required per column. FIG. 7 illustrates three check nodes. In addition, since 7 parallel processes are performed in the column processing, 3 × 7 (columns) = 21 data are required.

  The data for one column is stored in the corresponding dual port RAM 49 of the first memory element group in the order of the column weight number (j). As this data, three pieces of data can be read out by one access. In addition, by arranging the dual port RAM configuration in the same number as the row weight, seven sets of 3 × 7 (columns) = 21 data can be read simultaneously. Here, since the dual port RAM 49 constituting the first storage means 48 stores data in the order of row numbers, it is necessary to designate an address corresponding to the row number of the data as the read address of the data. This read address is designated by the control unit 40.

  FIG. 12 is a diagram for explaining this address designation. The column number conversion memory 64 is used to convert the column number into an address corresponding to the row number. The column number of the column processing calculation target is given to the memory address. The number of columns subject to column processing calculation is 7, but conversion is realized by setting memory contents in advance so that addresses corresponding to the 21 row numbers are output from one column number. .

  The data read from the first storage means 48 is input to the column processing arithmetic circuit 44 for each column. The column processing arithmetic circuit 44 can perform seven parallel processing. In addition, the temporary estimated word calculation circuit 50 can perform 7 parallel processing.

  Next, the output data from the column processing arithmetic circuit 44 is written into the dual port RAM 47 constituting the second storage means 46. Since 21 pieces of data are written evenly, all data can be written in one access.

Next, the advantages of the first specific example will be made clearer by comparison with the comparative example.
FIG. 13 is a block diagram showing an LDPC code decoding apparatus according to a comparative example. In addition, the same number is attached | subjected to the component similar to a 1st example, and detailed description is abbreviate | omitted. In this comparative example, the parity check processing time is shortened by dividing the parity check matrix in the row direction and the column direction and performing parallel processing. In order to reduce the circuit scale, a RAM is used for the first storage means 48 and the second storage means 46, and a plurality of RAMs are used for parallel processing. Further, in the parity check matrix, “1” is randomly arranged as illustrated in FIG. In this comparative example, the check matrix has a row weight of 4 and a column weight of 3.

First, the row processing calculation of the comparative example will be described.
FIG. 15 is a diagram illustrating an example of a parity check matrix.
FIG. 16 is a block diagram showing a memory connection at the time of row processing calculation. The second storage means 46 and the first storage means 48 store the data in every 100 columns in the order of the column numbers. The element “1” in the first row in the check matrix is in the fourth, 201th, and 480th columns. , 998, the data for the element is scattered in the RAM constituting the storage means. As a result, the selection circuit 66 for selecting only the data necessary for the row processing operation from the output of each RAM is required. Further, when writing the operation data into each RAM, a selection circuit 66 for selecting and passing the corresponding data to a plurality of RAMs corresponding to the four “1” elements in the row is required.

Next, the column processing operation of the comparative example will be described.
FIG. 17 is a diagram illustrating an example of a parity check matrix.
FIG. 18 is a block diagram showing memory connections at the time of column processing calculation. The second storage means 46 and the first storage means 48 store data for every 100 rows in the order of row numbers.

  If the “1” element of the parity check matrix is randomly arranged and the “1” element in the first column is in the second, 152th, and 450th rows, the data for that element is stored in each RAM. Scattered. As a result, a selection circuit 66 that selects only data necessary for column processing operation from the output of each RAM is required. Further, when writing the operation data into each RAM, a selection circuit 66 for selecting and passing the corresponding data to a plurality of RAMs corresponding to the three “1” elements in the column is required.

  As described above, in the comparative example, when the check matrix is “1” randomly arranged, the selection circuit 66 is necessary on the input and output sides of the first storage unit 48 and the second storage unit 46. It is. This selection circuit 66 is required for the number of parallel processes. When the number of parallel processes is increased in order to shorten the arithmetic processing time, the number of selection circuits 66 is increased accordingly. The selection circuit 66 has a large circuit scale, leading to an increase in the size of the device and an increase in power consumption.

  On the other hand, in the first specific example, the parity check matrix is divided into (number of row weights × twice column weights) sub-matrices, and “1” is distributed to a plurality of RAMs. Thus, the row processing operation and the column processing operation can be performed in parallel without rearranging the storage data of the first storage unit 48 and the second storage unit 46, and data can be read and written by using the dual port RAM 60. Time can also be reduced. As a result, the data corresponding to the row weight number (k) and the column weight number (j) can be stored in the (port weight × column weight) number of dual port RAMs 60, so that the selection circuit 66 is unnecessary. Yes, the circuit scale can be reduced by 7 to 20%. As a result, it is possible to realize a decoding device capable of shortening the calculation processing time, miniaturizing, and reducing power consumption.

Next, a low-density parity check code decoding apparatus and decoding method according to the second specific example of the present invention will be described.
FIG. 19 is an example of a parity check matrix in the second specific example. In each submatrix, elements of “1” are arranged at random, but the row weight is 0, 1, or 2, and the column weight is 0 or 1.

  Here, the sum of the column weights in the matrix that is a combination of the (2r-1) th and 2rth (r = 1, 2,..., Pm / 2) sub-matrices that are vertically continuous is set to 1. . Further, all the row weights of the matrix obtained by combining two paired partial matrices along the row direction are set to 2. Hereinafter, “continuous along the row direction” will be referred to as “continuous sideways”.

  In the example of FIG. 19, Hsub [2r−1] [2] and Hsub [2r] [2] whose column block number = 2 are arranged vertically and continuously, and Hsub [2r whose column block = 3. -1] [3] and Hsub [2r] [3] are arranged vertically continuously.

  On the other hand, Hsub [2r-1] [2] belonging to the column block = 2 and Hsub [2r-1] [3] belonging to the column block = 3 constitute a horizontally continuous pair submatrix. Hsub [2r] [2] belonging to the column block = 2 and Hsub [2r] [3] belonging to the column block = 3 form a horizontally continuous pair submatrix. The position of this pair submatrix is not particularly limited. For example, combinations of column block numbers such as Nos. 1 and 2, Nos. 2 and 3, Nos. 3 and 4, Nos. 4 and 5, etc. can be arbitrarily selected.

Next, the flow of processing in the second specific example will be described in more detail.
In FIG. 20, each submatrix 12 has 2 rows × 4 columns, and two sets of paired submatrixes 13 that are laterally continuous by partial matrices belonging to column block number = 2 and column block number = 3 are provided vertically. It is an example of a check matrix. In this case, the row weights are all set to 2 in the two pair matrices 13. In the submatrices other than the two pair submatrices 13, the row weights are all set to 1. The two pairs of sub-matrixes 13 are positioned in the (2r-1) th and 2r-th (where r is one of natural numbers from 1 to Pm / 2) sub-matrices in the vertical direction.

  Also in the second specific example, the row processing calculation is the same as in the first specific example, so only the column processing calculation will be described. In the parity check matrix illustrated in FIG. 20, the row weight number of the element “1” that is the column processing calculation target for the first column and the second column of each submatrix matches the column block number. The same column processing operation can be performed.

  Further, in the column processing calculation of the third column of each submatrix, the row weight number of the element “1” that is the column processing calculation target with the column block number of 1 and the column block number of 4 or more is equal to the column block number. Therefore, the same column processing operation as that in the first specific example can be performed.

Next, column block number = 2 and column block number = 3, which are different from the first specific example, will be described below.
FIG. 21 is a block diagram showing memory connections in column processing operations. A corresponding block diagram of the first specific example is illustrated in FIG. 11, and FIG. 20 represents only a part different from the first specific example.

  The element “1” of the column processing calculation target in the third column in the column block number = 3, that is, the eleventh column in the parity check matrix 10 is located in the fourth row, the sixth row, and the ninth row, respectively. These are expressed as {element (4, 11), element (6, 11), element (9, 11)}. Further, the row weight number and the column weight number of the element are expressed as {weight (k = row weight number, j = column weight number)}.

  This is the weight (k = 2, j = 1) of the element (4, 11), and the weight number is different from the column block number. In this case, the data is stored in RAM-A [1] [2] (k = 2, j = 1) constituted by the dual port RAM in FIG. Reading of the data is performed using the port 2 of the RAM-A [1] [2]. The read data is transferred to the column processing arithmetic circuit 44 (# 3) by controlling the selection circuit 66 by the selection instruction circuit 72 (# 3).

  On the other hand, the row weight number of the element (6, 11) and the element (9, 11) is 3, which matches the column block number = 3. In this case, the data is read from the RAM-A [2] [3] and RAM-A [3] [3], respectively, and the selection instruction circuit 72 (# 3) controls the selection circuit 66 to perform column processing calculation. It is passed to the circuit 44 (# 3). As described above, all three pieces of data necessary for the column processing calculation are simultaneously read from the corresponding dual port RAM.

  Subsequently, the column processing calculation data is the dual port RAM 49 from the column processing calculation circuit 44 (# 3), RAM-B [1] [2], RAM-B [2] [3], RAM-B [3] [ 3]. At this time, port 2 is used for writing to RAM-B [1] [2], and port 1 is used for the other cases. In this way, all data can be written to the dual port RAM 49 simultaneously.

  Next, the column processing calculation for the third column in column block number = 2 will be described. In this case, all the row weight numbers of the element “1” to be subjected to the column processing calculation are 2, which matches the column block number. Accordingly, data is simultaneously read from port 1 of RAM-A [1] [2], RAM-A [2] [2], RAM-A [3] [2], and selected by the selection instruction circuit 70 (# 2). By controlling the circuit 66, the data necessary for the column processing operation of the third column of the column block number = 2 is passed to the column processing arithmetic circuit 44 (# 2).

  Column processing operation data is written to each memory using port 1 of RAM-B [1] [2], RAM-B [2] [2], RAM-B [3] [2]. The selection instruction circuits 70 (# 2) and 72 (# 3) can be realized using a memory. The column number of the column processing calculation target is given to the memory address, and the selection instruction signal corresponding to the check matrix is stored in advance from the data bus.

  Next, the column processing operation for the fourth column of each submatrix will be described. Since the row weight number of the element “1” to be subjected to the column processing calculation in the column block number = 1 and the column block number = 4 or more matches the column block number, it can be the same as in the first specific example. The column processing operation of column block number = 2 and column block number = 3 will be described using the memory connection in FIG.

The element of “1” in the fourth column in the column block number = 2, that is, the column operation target in the eighth column of the parity check matrix 10 is located in the second row, the seventh row, and the ninth row. These are expressed as {element (2, 8), element (7, 8), element (9, 8)}. Further, the weight (k = 3, j = 1) of the element (2, 8) is different from the column block number = 2. In this case, the data is stored in RAM-A [1] [3] (k = 3, j = 1).
The data is read out using port 2 of RAM-A [1] [3]. Subsequently, the data is transferred to the column processing arithmetic circuit 44 by the selection circuit 66 controlled by the selection instruction circuit 72 (# 3).

  On the other hand, the row weight number of element (7, 8) and element (9, 8) is 2, which matches the column block number. Therefore, the data is read from RAM-A [2] [2] and RAM-A [3] [2], selected by the selection circuit 66, and passed to the column processing arithmetic circuit 44. For this purpose, all three pieces of data necessary for the column processing calculation are simultaneously read from the RAM-A. The column processing operation data is written into RAM-B [1] [3], RAM-B [2] [2], RAM-B [3] [2]. At this time, RAM-B [1] [3] ], Port 2 is used for writing, and port 1 is used otherwise.

  The row weights of the “1” elements to be subjected to the column processing calculation in the fourth column of the column block number = 3 are all 3, which matches the column block number. Therefore, data is simultaneously read from port 1 of RAM-A [1] [3], RAM-A [2] [3], and RAM-A [3] [3]. Controlled to select output. As a result, data necessary for the column processing calculation of the fourth column with column block number = 3 is passed to the column processing arithmetic circuit 44 (# 3). Column processing operation data is written into each memory using port 1 of RAM-B [1] [3], RAM-B [2] [3], RAM-B [3] [3]. In this way, all data can be written to the dual port RAM 49 simultaneously.

  In the second specific example, a selection instruction circuit and a minimum selection circuit are required. However, since the number of selection circuits is extremely small compared to the comparative example illustrated in FIG. 13, an increase in circuit scale can be minimized.

  The advantage of the second specific example is that the design of the check matrix 10 is easier than that of the first specific example. One method of constructing a parity check matrix for decoding an LDPC code is a construction method using Gallager that performs column replacement using random numbers. In the second specific example, the horizontal pair submatrix 13 can provide a degree of freedom due to the check matrix configuration, so that the design becomes easier.

  Further, similarly to the first specific example, also in the second specific example, the parity check matrix is divided into partial matrices, and “1” is distributed. Further, the dual port RAM 60 is used to reduce data read / write time. As a result, data corresponding to the row weight number (k) and the column weight number (j) can be stored in the dual port RAM 60 of row weight × column weight number, so that the number of selection circuits can be reduced. As a result, it is possible to realize a decoding device capable of shortening the calculation processing time, miniaturizing, and reducing power consumption.

  By using the LDPC code decoding apparatus and decoding method as described in the first specific example and the second specific example, it is possible to detect and correct errors occurring in a high-speed data transmission path. As a result, a high-speed transmission line with a low block error rate and a small error floor can be realized.

  The embodiments of the present invention have been described above with reference to the drawings. However, the present invention is not limited to these specific examples. For example, those skilled in the art have made various design changes with respect to storage means, memory elements, arithmetic circuits, S / P circuits, P / S circuits, buffer circuits, etc. constituting the LDPC decoding device, and decoding methods. However, as long as it has the gist of the present invention, it is included in the scope of the present invention.

It is a block diagram of the decoding apparatus of the low density parity check (LDPC) code concerning the 1st example of this invention. It is a block diagram showing the receiver incorporating the decoding apparatus concerning a 1st specific example. It is a figure showing the parity check matrix of the LDPC code in a 1st specific example. It is a figure showing an example of the check matrix of the LDPC code in the 1st example. It is a figure showing a Tanner graph. It is a Tanner graph for demonstrating line processing calculation processing. It is a Tanner graph for demonstrating a column process calculation process. It is a flowchart explaining the decoding method of the low density parity check code concerning this example. It is a figure showing the structure of the dual port RAM in a 1st example. It is a block diagram showing the connection of the dual port RAM and row processing arithmetic circuit in the decoding apparatus concerning the 1st specific example. It is a block diagram showing the connection of dual port RAM and a column processing arithmetic circuit in the decoding apparatus concerning a 1st specific example. It is a figure showing a column number conversion memory. It is a block diagram showing the decoding apparatus of the LDPC code concerning a comparative example. It is an example of the check matrix in a comparative example. It is an example of the check matrix for demonstrating the row processing calculation in a comparative example. It is a block diagram showing the memory connection at the time of the row processing calculation in a comparative example. It is an example of the check matrix for demonstrating the column processing calculation in a comparative example. It is a block diagram showing the memory connection at the time of the column processing calculation in a comparative example. It is a check matrix in the second specific example. It is a more detailed example of the check matrix in the second specific example. It is a block diagram showing the memory connection at the time of the column processing calculation in the second specific example.

Explanation of symbols

10 Check Matrix 12 Submatrix 13 Lateral Pair Submatrix 20 Antenna 22 Demodulator 24 Decoder 26 CPU
28 Video / Audio Signal Processing Circuit 32 Monitor 34 Speaker 40 Control Unit 42 Row Processing Operation Circuit 44 Column Processing Operation Circuit 46 Second Storage Unit 47 Dual Port RAM
48 First storage means 49 Dual port RAM
50 Temporary Estimated Word Calculation Circuit 52 S / P Circuit 54 Input Buffer 56 Output Buffer 58 P / S Circuit 60 RAM
64 column number conversion memory 66 selection circuit 70 selection instruction circuit 72 selection instruction circuit

Claims (10)

A row processing arithmetic circuit that performs a row processing operation using a check matrix that performs error correction of a received word;
A column processing arithmetic circuit that performs column processing arithmetic using the parity check matrix that performs error correction of a received word;
First storage means for storing row processing calculation data by the row processing calculation circuit;
Second storage means for storing column processing calculation data by the column processing calculation circuit;
With
The check matrix is configured as a set of a plurality of sub-matrices divided in the column direction by a multiple of the column weight and divided in the row direction by the number of row weights,
The row weights of the sub-matrixes are all configured to be 1,
The sum of the column weights of the (2r-1) th submatrix that is continuous in the column direction of the parity check matrix and the column weights of the 2rth submatrix (where r is a column weight number) are all 1. ,
The first storage means stores the row processing calculation data for each of the same row weight number and the same column weight number for the element “1” of the parity check matrix,
The second storage means stores the column processing calculation data for each of the same row weight number and the same column weight number for the element “1” of the parity check matrix,
The row processing arithmetic circuit performs a parallel processing of a row processing operation of twice the column weight using the column processing arithmetic data read from the second storage means, and calculates the arithmetic data for each row weight number and column weight number. Write to each of the first storage means,
The column processing arithmetic circuit performs parallel processing on the number of row weights of column processing arithmetic using the row processing arithmetic data read from the first storage means, and calculates the arithmetic data for each column weight number and row weight number. A low-density parity check code decoding apparatus, wherein the low-density parity check code is written in each of the second storage means.   The first storage means writes row processing operation data corresponding to all “1” elements of two rows in the parity check matrix to two combinations of column weight numbers and row weight numbers at the same time. 2. The decoding apparatus according to claim 1, comprising a plurality of dual port RAMs having two possible ports.   The second storage means reads column processing operation data corresponding to all “1” elements of two rows in the parity check matrix in correspondence with combinations of column weight numbers and row weight numbers, and simultaneously reads out two rows. 3. The decoding apparatus according to claim 1, further comprising a plurality of dual port RAMs having two possible ports. As a check matrix for error correction of received words, it is a set of a plurality of sub-matrices formed by dividing the column direction by a multiple of the column weight and dividing the row by the number of row weights in the row direction, The row weights of the submatrices are all set to 1, and the column weight of the (2r-1) th submatrix and the 2rth submatrix (where r is a column weight number) that are continuous in the column direction of the parity check matrix. ) Using a set of sub-matrices constructed such that the sum of column weights is all 1,
A first step of writing each of the row weight number and the column weight number in the column processing calculation data second storage means initialized by inputting the received word data;
For the element “1” of the parity check matrix, column processing calculation data stored in the second storage means is read out, row processing calculation is performed by parallel processing of twice the column weight, and the calculation data is stored in the first memory. A second step of writing to the means for each row weight number and column weight number;
For the element “1” of the parity check matrix, the row processing calculation data stored in the first storage means is read, column processing calculation is performed by parallel processing of the number of row weights, and the calculation data is converted into the second data. A third step of writing to the storage means for each row weight number and each column weight number, and calculating a temporary estimated word using the row processing calculation data;
A fourth step in which the second step and the third step are repeated a predetermined number of times in this order;
A method for decoding a low-density parity check code. A row processing arithmetic circuit that performs a row processing operation using a check matrix that performs error correction of a received word;
A column processing arithmetic circuit that performs column processing arithmetic using the parity check matrix that performs error correction of a received word;
First storage means for storing row processing calculation data by the row processing calculation circuit;
Second storage means for storing column processing calculation data by the column processing calculation circuit;
A selection circuit that selects and outputs one of the two data stored in the first storage means;
With
The check matrix is configured as a set of a plurality of sub-matrices divided in the column direction by a multiple of the column weight and divided in the row direction by the number of row weights,
The sum of the column weights of the (2r-1) th submatrix and the 2rth submatrix (where r is the range of all column weight numbers) that is continuous in the column direction of the parity check matrix is all 1. Configured as
Among the plurality of sub-matrices, the sum of row weights of two sub-matrices continuous in the row direction is configured to be 2,
The first storage means stores the row processing calculation data for each of the same row weight number and the same column weight number for the element “1” of the parity check matrix,
The second storage means stores the column processing calculation data for each of the same row weight number and the same column weight number for the element “1” of the parity check matrix,
The row processing arithmetic circuit performs a parallel processing of a row processing operation of twice the column weight using the column processing arithmetic data read from the second storage means, and calculates the arithmetic data for each row weight number and column weight number. Write to each of the first storage means,
The column processing arithmetic circuit performs parallel processing of column processing operations for the number of row weights using the row processing arithmetic data selected and output by the selection circuit, and calculates the arithmetic data for each column weight number and row weight number. A low-density parity check code decoding apparatus, wherein the low-density parity check code is written in each of the second storage means.   The first storage means includes a plurality of dual-port RAMs having two ports capable of simultaneously writing two rows of row processing operation data corresponding to all “1” elements of two rows of the parity check matrix. The decoding device according to claim 5.   The second storage means includes a plurality of dual port RAMs having two ports capable of simultaneously reading two rows of column processing operation data corresponding to all “1” elements of two rows of the parity check matrix. The decoding device according to claim 5 or 6.   The second storage means includes a dual port RAM capable of simultaneously writing column processing operation data corresponding to all “1” elements of two columns in two sub-matrices continuous in the row direction. The decoding device according to any one of claims 5 to 7.   The first storage means has a dual port RAM capable of simultaneously reading out row processing operation data corresponding to all “1” elements in two columns in two sub-matrices continuous in the row direction. The decoding device according to any one of claims 5 to 8. As a check matrix for error correction of received words, it is a set of a plurality of sub-matrices formed by dividing the column direction by a multiple of the column weight and dividing the row by the number of row weights in the row direction, The sum of the column weights of the (2r-1) th submatrix that continues in the column direction of the check matrix and the column weights of the 2rth submatrix (where r is the range of all column weight numbers) is all 1. Using a set of a plurality of sub-matrices configured such that the total of the row weights of two sub-matrices continuous in the row direction among the plurality of sub-matrices is all 2,
A first step of writing operation data initialized by inputting received word data to the second storage means for each row weight number and column weight number;
For the element “1” of the parity check matrix, column processing calculation data stored in the second storage means is read out, row processing calculation is performed by parallel processing of twice the column weight, and the calculation data is stored in the first memory. A second step of writing to the means for each row weight number and column weight number;
For one “1” element of the parity check matrix, one of the two row processing calculation data stored in the first storage means is selected and read out, and column processing calculation is performed by parallel processing of the number of row weights. And writing calculation data to the second storage means for each row weight number and column weight number, and calculating a temporary estimated word using the row processing calculation data;
A fourth step in which the second step and the third step are repeated a predetermined number of times in this order;
A method for decoding a low-density parity check code.

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