JP2007108838A - Compile method and compile device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To parallelize a loop so as to perform parallel execution when the effects of parallel execution is expected, and to perform successive execution when the effects of parallel execution is not expected when the loop length of the parallelized loop is unclear. <P>SOLUTION: This compile device generates an object code 107 executable on a shared memory type computer with a thread as the unit of parallel processing by input of a source program 101 and using an inter-thread synchronous overhead information file 108 and the number of machine cycles acquisition library 106, and is constituted of a syntax analysis part 103, a parallelization part 104 and a code generation part 105. The parallelization part 104 executes the first repetition of a loop which can be parallelized, and acquires the number of machine cycles whose loop repetition is one time, and generates an object code to determine a threshold as loop length from which the acquisition of the effects of parallel execution is expected. Thus, it is possible to perform highly efficient parallel execution by a static determination system in a development time shorter than that in an execution information sampling system. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a compiling method and compiling device, and more particularly to a compiling method and compiling device for parallelizing a source program described in a programming language.

  A compiling device that parallelizes a source program for a shared memory computer is a machine language that can process a source program written in a programming language or the like (hereinafter simply referred to as a source program) by a plurality of threads. It is generated in a program (hereinafter referred to as object code). Since parallel processing generates parallel overhead associated with parallel processing such as synchronization processing among multiple threads, for example, loop parallelization hides the parallelization overhead unless the loop length exceeds a certain length Cannot be obtained and the effect of parallelization cannot be obtained.

  For parallelization of loops according to the prior art, a method of generating object code for selecting parallel execution or sequential execution at the time of execution when the loop length of the parallelized loop is not known at the time of execution is used. Then, as a method for generating object code, a loop length value (hereinafter referred to as a threshold) that can be expected to obtain the effect of parallel execution statically determined by the compiling device is compared with an actual loop length at the time of execution. Thus, there are a method of generating an object code (hereinafter referred to as a static determination method) and a method of determining a threshold value at the time of recompilation based on program execution information (hereinafter referred to as an execution information collection method).

In addition, as an example of a method different from the static determination method and the execution information collection method, a technique related to a calculation method (hereinafter referred to as a dynamic determination method) that collects execution information at the time of execution and optimizes the program at the time of execution is, for example, It is described in Patent Document 1 and the like.
JP 2004-355144 A

  The static determination method described above has a problem that it is difficult to determine a highly accurate threshold value because the influence of the cache memory at the time of execution is not taken into consideration. In addition, the execution information collection method can determine a highly accurate threshold because the program is executed once in order to collect execution information. However, since recompilation is required, this is an overhead in program development. It has the problem of becoming.

  In addition, the above-described dynamic determination method has a problem that the user needs to explicitly describe the area to be optimized and the parameter to be optimized in the source program that is input. Has a point. Moreover, this dynamic determination method is to generate a program to be dynamically optimized, and is not related to parallel compilation that generates object code that dynamically separates between parallel execution and sequential execution.

  The object of the present invention is to solve the above-mentioned problems of the prior art, the problem that it is difficult to determine a high-accuracy threshold in the static decision method, and the need to recompile in the execution information collection method Solve the problem and let parallel execution occur when parallel loops whose loop length is unknown can be expected to obtain the effect of parallel execution, and execute sequentially when the effect of parallel execution cannot be expected It is another object of the present invention to provide a compiling method and compiling device for parallelizing a source program capable of parallelizing a loop.

  According to the present invention, in the compiling method for generating an object code used in a shared memory type computer, the first loop repetition is executed for a parallel loop whose loop length is unknown at the time of compiling. The number of machine cycles required for one iteration of the loop is acquired, and a loop length value that can obtain the effect of parallel execution is calculated based on the acquired number of machine cycles. This is achieved by separating execution.

  The object is a compiling device that generates an object code used in a shared memory type computer, and includes a syntax analysis unit, a parallelization unit, and a code generation unit, and the parallelization unit includes the shared memory. By executing the object code used in the type computer, the required number of machine cycles for one iteration of the loop is acquired, and parallel processing based on the acquired number of machine cycles and the synchronization processing overhead information of the computer to be read at the time of compilation The loop length that can obtain the effect of execution is obtained, and the obtained loop length that can obtain the effect of parallelization is compared with the actual loop length of the loop, so that the parallel execution or the sequential execution is separated. This is accomplished by generating an intermediate language.

  According to the present invention, when the loop length is short with respect to the parallelized loop and the effect of parallelization cannot be expected, the object code to be sequentially executed can be generated more accurately than the static determination method.

  Hereinafter, embodiments of a compiling method and compiling apparatus for parallelizing source programs according to the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a compiling device according to an embodiment of the present invention, and FIG. 5 is a block diagram showing a configuration of a shared memory type computer. 1 and 5, 101 is a source file, 102 is a parallel compilation device, 103 is a syntax analysis unit, 104 is a parallelization unit, 105 is a code generation unit, 106 is a machine cycle number acquisition library, 107 is an object code, Reference numeral 108 denotes an interthread synchronization overhead information file, 111 a CPU, 112 a memory, 113 a hard disk device, 501 a shared memory computer, 502 a processor, 503 a cache memory, and 504 a main memory.

  The parallelized program according to the embodiment of the present invention is executed on, for example, a shared memory type computer 501 as shown in FIG. The shared memory type computer 501 is configured by connecting a plurality of processors 502 each having a cache memory 503 and a main memory 505 shared by the plurality of processors 502 via a communication path such as a bus. Yes.

  As shown in FIG. 1A, the parallel compiling apparatus 102 according to the embodiment of the present invention receives the source program 101 described in a programming language such as FORTRAN as an input, and synchronizes overhead information files 108 between threads and the machine. An object code 107 that can be executed on a shared memory type computer is generated by using a cycle number acquisition library 106 as a unit of parallel processing, and includes a syntax analysis unit 103, a parallelization unit 104, and a code generation unit 105. Consists of

  The parallelizing compiling device 102 configured as described above is constructed on the shared memory computer 501 shown in FIG. 5, and one of the processors 502 is configured to execute parallel processing of the source program. Alternatively, it may be built in another independent computer. FIG. 1B shows a configuration example of a computer when a parallel compiling device is built in a computer. As is well known, this computer includes a CPU 111, a memory 112, a hard disk device 113, and not shown. What is necessary is just to be provided with the input / output device. In the parallel compiling device 102, each functional unit constituting the device is configured by software, stored in the hard disk device 113, called into the memory 112, and executed by the CPU under the OS. Can be realized. Further, the source file 101 for storing information required by the parallelizing compiling device 102, the machine cycle number acquisition library 106, and the inter-thread synchronization overhead information file 108 need only be stored in the hard disk device 113, and can be generated. The object code 107 may be stored in the hard disk device 113.

  The syntax analysis unit 103 constituting the parallel compilation apparatus receives the source program in the source file 101 as an input, and generates an intermediate language from the source program. The parallelization unit 104 receives the intermediate language generated by the syntax analysis unit 103 and the synchronization overhead information in the target machine from the inter-thread synchronization overhead information file 108, and acquires the number of machine cycles for the parallel loop whose loop length is unknown. The hardware counter routine of the library 106 is used to obtain the required number of machine cycles for the first iteration of the loop, a threshold is determined based on the number of machine cycles, and the parallel execution is performed by comparing the threshold with the loop length. Generates an intermediate language for determining whether to execute. In addition, the code generation unit 105 receives the intermediate language output from the parallelization unit 104 as an input, performs optimization, register allocation, etc. on the intermediate language, and then links the machine cycle number acquisition library 106 Then, the object code 107 which is a machine language executable by the computer is generated.

  FIG. 2 is a flowchart for explaining a processing operation in which the parallelizing unit 104 generates an intermediate language for determining whether the execution is parallel execution or sequential execution. In the processing shown in the flowchart shown here, the parallel processing unit 104 executes the first loop iteration processing for the parallel loop whose loop length is unknown using the hardware counter routine of the machine cycle number acquisition library 106. In this process, the required number of machine cycles is acquired, a threshold is determined based on the number of machine cycles, and an intermediate language is generated for comparing between the threshold and the loop length to distinguish between parallel execution and sequential execution. Therefore, in this processing, the parallelizing unit 104 uses only the necessary name (code) in the machine cycle number acquisition library 106 and does not use the entity, and the entity of the machine cycle number acquisition library 106 is Used when creating an object.

(1) When the process is started, the parallelizing unit 104 first determines whether the loop length of the parallelized loop is unknown, and if not, does nothing and ends the process here (station) 201, 202, 208).

(2) If it is determined in step 202 that the loop length of the parallelized loop is unknown, a check code with a loop length of 0 times is inserted before the parallel loop (step 203).

(3) Next, peeling is performed to take out the first iteration of the parallel loop, and a statement (code) for calling a hardware counter routine from the machine cycle number acquisition library 106 is inserted before and after the peeled loop body (step 204). ).

(4) Next, the inter-thread synchronization overhead information file 108 is read, and a code for determining a threshold value from the machine cycle number of the peeled main body obtained from the thread fork overhead, inter-thread barrier overhead, and hardware counter routine is read. Insert (steps 205 and 206).

  FIG. 6 is a diagram for explaining an example of the contents of the inter-thread synchronization overhead information file 108 read in the process of step 205 described above. The contents of the inter-thread synchronization overhead information file 108 are, for example, as shown as 601 in FIG. 6. In the example shown in FIG. 6, the thread fork overhead of the target shared memory type computer is 1000 cycles, and the inter-thread barrier It is shown that the overhead is 2000 cycles and the number of processors is 16.

(5) After that, the determined threshold value is compared with the loop length, and if established, a code is branched to the parallel loop, and if not established, a code to branch to the sequential loop is generated, and the processing here is terminated (step) 207, 208).

  The processing described above is configured by a program and can be executed by a CPU provided in a computer. These programs can be provided by being stored in a recording medium such as an FD, a CDROM, or a DVD. Can be provided by digital information.

  FIG. 3 is a diagram for explaining an example of a source program. FIG. 4 is a diagram for explaining an example of an intermediate language for explaining a parallelized loop generated from the source program shown in FIG. Will continue to be described as being compiled in parallel according to an embodiment of the present invention.

  In the example 301 of the source program shown in FIG. 3, A (I) = A (I) + B (I), S = C (I), D (I) = E (I) for all of I = 1 to N. Each operation of + F (I) is executed. The intermediate language generated by the parallelization unit 104 by the processing in the flow described with reference to FIG. 2 from such a source program is an intermediate language as indicated by 401 in FIG.

  It is checked whether the loop length N is 0 or more by the check code inserted in step 203 in FIG. 2 (line 402). If it is 0 or less, nothing is done, and if it is 0 or more, the first loop iteration is performed. A hardware counter routine for acquiring the machine cycle number before and after the peeled loop is called to start counting (line 403), and after the hardware counter is completed, the machine cycle number is acquired (line 404). The expression described between the line 403 and the line 404 is an expression for executing I = 1 in the example 301 of the source program shown in FIG. A threshold is determined from the number of machine cycles acquired as a result of executing this expression (line 405), the determined threshold is compared with the loop length N (line 406), and if the expression shown in line 406 is satisfied, Parallel execution is performed, and if it does not hold, branching is performed so that sequential execution is performed.

  In the case of parallel execution, code (line 407) for determining the start position% L and end position% U of each thread of each thread parallelized by dividing the loop length is described, and the start of each thread of the parallelized loop The position% L and the end position% U are specified, and the source program is executed in parallel by a plurality of processors. The instruction to execute this parallel execution is an expression shown in four lines including do% I =% L and% U.

  On the other hand, in the case of sequential execution, I = 2 to N except for I = 1 in the source program example 301 shown in FIG. 3 are sequentially executed by one processor. The instruction to perform this sequential execution is an expression shown in four lines including doI = 2 and N.

  As can be seen from the example of the intermediate language shown in FIG. 4, when this intermediate language is generated into object code and executed by the processor, the first one of the loops is actually executed, and the execution result is executed in parallel. Or sequential execution is determined.

  FIG. 7 is a diagram showing an example of an arithmetic expression 701 for performing threshold calculation in the process of step 206 in the flow of FIG. 2, and FIG. 8 is a diagram showing an example of the number of machine cycles acquired by the hardware counter at the time of execution. In FIG. 7, the threshold value to be obtained is L, the machine cycle number of the peeled loop to be acquired is M, the thread fork overhead is O1, the inter-thread synchronization overhead is O2, and the number of execution threads is NPE.

Since the expected number of sequential execution machine cycles is L × M and the expected number of parallel execution machine cycles is L × M ÷ NPE + (O1 + O2), the lowest threshold value where the expected number of parallel execution machine cycles is lower than the expected number of sequential execution machine cycles is As shown in equation 701 in FIG.
L = ((O1 + O2) × NPE) ÷ (M × (NPE-1))
It becomes.

  For example, when the inter-thread synchronization overhead information 601 shown in FIG. 6 is read in the processing of step 205 in the flow of FIG. 2, since O1 = 1000, O2 = 2000, and NPE = 16 are set, L = 3200 ÷ M is the actual processing of the threshold calculation in the row 405 in FIG. 4, and when the number of machine cycles acquired in the row 404 in FIG. 4 is 801 in FIG. If M = 10 is set, L = 320, and if no data is stored in the cache memory, M = 200 is set and L = 16.

  In the case of the example as described above, the static determination method described in the section of the prior art can obtain an effect because the threshold when the data is loaded or not loaded in the cache memory cannot be considered. In some cases, unexpected parallel execution may be performed, and in the execution information collection method, recompilation and re-execution are necessary. However, in the embodiment of the present invention, this can be prevented.

  The embodiment of the present invention described above is an example in which the FORTRAN language is used as the source program. However, the present invention can be applied to a case where an arbitrary programming language such as C language is used as the source program. Can be applied.

It is a block diagram which shows the structure of the compilation apparatus by one Embodiment of this invention. It is a flowchart explaining the processing operation | movement which produces | generates the intermediate language which isolates whether the parallelization part 104 performs parallel execution or sequential execution. It is a figure explaining the example of a source program. It is a figure explaining the example of the intermediate language explaining the loop after the parallelization produced | generated from the source program shown in FIG. It is a block diagram which shows the structure of a shared memory type computer. It is a figure explaining the example of the content of the thread | sled synchronization overhead information file read by the process of step 205 of FIG. It is a figure which shows the example of the computing equation which performs the threshold value calculation by the process of step 206 in the flow of FIG. It is a figure which shows the example of the number of machine cycles acquired by a hardware counter at the time of execution.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Source file 102 Parallelization compiling apparatus 103 Syntax analysis part 104 Parallelization part 105 Code generation part 106 Machine cycle number acquisition library 107 Object code 108 Interthread synchronization overhead information file 111 CPU
112 memory 113 hard disk device 501 shared memory type computer 502 processor 503 cache memory 504 main memory

Claims (4)

  In a compiling method for generating object code used in a shared memory type computer, a loop that requires only one loop iteration is executed for a parallel loop whose loop length is unknown at the time of compilation. It is characterized by acquiring the number of cycles, calculating the loop length value that can obtain the effect of parallel execution based on the acquired number of machine cycles, and separating the parallel execution or sequential execution based on this value Compilation method.   In the compiling method for generating an object code used in a shared memory type computer, the required machine cycle number of one iteration of a loop is obtained by executing the object code used in the shared memory type computer, and the obtained machine A loop length capable of obtaining the effect of parallel execution based on the number of cycles and the synchronization processing overhead information of the computer to be read at the time of compilation is obtained, and the loop length and loop capable of obtaining the obtained effect of parallelization are obtained. A parallel loop method characterized by comparing the actual loop length of and determining whether to execute in parallel or sequentially.   In a compiling device that generates an object code used in a shared memory type computer, it is composed of a syntax analysis unit, a parallelization unit, and a code generation unit, and the parallelization unit is used in the shared memory type computer. By executing the object code, the number of required machine cycles for one iteration of the loop is acquired, and the parallel execution effect is obtained based on the acquired number of machine cycles and the synchronization processing overhead information of the computer to be read at the time of compilation. A loop length that can be obtained, and a comparison between the obtained loop length capable of obtaining the effect of parallelization and the actual loop length of the loop, and generating an intermediate language that separates between parallel execution and sequential execution A loop parallelization device characterized by the above.   In a compiler program executable by a computer that generates object code used in a shared memory type computer, the number of required machine cycles for one iteration of the loop is obtained by executing the object code used in the shared memory type computer. Obtaining a loop length capable of obtaining the effect of parallel execution based on the acquired number of machine cycles and the synchronization processing overhead information of the computer to be read at the time of compilation, and obtaining the obtained effect of parallelization A compiler program comprising a step of comparing a loop length capable of being executed and an actual loop length of the loop to determine whether the execution is parallel execution or sequential execution.

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