JP2007107101A - Plating apparatus and plating method for substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus and a method for plating a substrate, capable of continuously introducing and treating semiconductor wafers one by one in the plating apparatus without putting them in cassettes, reducing particle contamination or oxide film formation as much as possible, decreasing the number of processes and decreasing a floor space of the apparatus. <P>SOLUTION: The apparatus 10 for plating the substrate forms a plated layer on the substrate for embedding a wiring part made of wiring gutters and wiring holes, wherein the wiring part is formed on a surface of the substrate, and a barrier layer is formed on the surface of the substrate containing the wiring part. The apparatus is equipped with a first plating bath 13 for forming the plated layer on the barrier layer containing the wiring part surface through electroless plating and a second plating bath 13 for forming the plated layer for wiring on top of the plated layer through electrolytic plating. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a substrate plating apparatus for plating a substrate, and particularly suitable as a plating apparatus for forming a wiring layer in a wiring portion comprising fine grooves and / or fine holes formed on a substrate surface such as a semiconductor wafer. The present invention relates to a substrate plating apparatus and a substrate plating method.

  Conventionally, aluminum is often used as a circuit wiring material for semiconductor devices. In many cases, wiring of semiconductor devices is performed by etching back aluminum sputtering. On the other hand, wiring formation with other metal materials such as copper may be difficult with the above-described method. Therefore, a method is adopted in which a wiring groove or hole is formed in advance in the substrate, a metal material is embedded in the groove or hole, and then the surface is subjected to chemical mechanical polishing (CMP).

  However, as the degree of integration of semiconductor devices increases, the miniaturization of wiring advances and the width of wiring further decreases, and as step coverage increases, conventional fine grooves and fine holes (fine contact holes) formed by sputtering have been used. There is a limit to embedding metal in the wiring portions made of the above, and there is a problem that holes are easily formed in these wiring portions.

  For example, due to high integration of semiconductor devices, wiring grooves and wiring holes having a width of 0.18 μm or 0.13 μm are required. It is difficult to embed a metal material into the wiring grooves and wiring holes thus miniaturized by sputtering. Therefore, instead of embedding a metal material by sputtering, a Cu plating layer is formed by electrolytic plating or electroless plating on the surface of the semiconductor wafer including the wiring portion including such fine grooves and fine holes, and then Cu plating of the wiring portion is performed. There is a demand for development of a technique for performing the process of removing the Cu plating layer on the surface of the semiconductor wafer with a single apparatus while leaving the layer.

  In the case where the seed layer is formed by electroless Cu plating or electrolytic Cu plating having a different liquid composition, which is a pre-process of the plating process, the semiconductor wafer after the plating process and the cleaning process is dried, put in a wafer cassette, and the wafer. Although the cassettes are moved between the apparatuses, the drying process and the like can be omitted by introducing the cleaning liquid onto the semiconductor wafer, that is, in the wet state, into the Cu plating apparatus rather than this method. For this purpose, the problem of contamination of the semiconductor wafer is reduced if the semiconductor wafers are continuously introduced into the Cu plating apparatus one by one without being put in the cassette.

  Furthermore, during the waiting time until each semiconductor wafer is introduced into the Cu plating apparatus and plated, if it is temporarily stored in pure water or dilute sulfuric acid to prevent particle contamination and oxide film formation, plating is possible. It is not necessary to set a non-energization time for removing the surface oxide film after immersing the semiconductor wafer in the liquid.

  Further, when the semiconductor device is miniaturized and the thickness of the sheet layer in the hole is reduced, the etching for the purpose of removing the surface oxide film must be as small as possible. That is, the oxide film formation before the plating process must be prevented as much as possible.

  In addition, if a CMP apparatus, which is a subsequent process in which the semiconductor wafers after plating processing are continuously discharged one by one from the Cu plating apparatus, is placed close to the apparatus, the Cu plating apparatus and the CMP apparatus are separated from each other. However, since the unload stage and, in some cases, the drying step can be omitted, the installation area of the apparatus can be reduced.

  The present invention has been made in view of the above points, and can introduce and process semiconductor wafers one by one in a plating apparatus one by one without putting them in a cassette, and reduce particle contamination and oxide film formation as much as possible. An object of the present invention is to provide a substrate plating apparatus and a substrate plating method that can reduce the number of steps and reduce the installation area of the apparatus.

  In order to solve the above-mentioned problem, the invention according to claim 1 embeds the wiring part in a substrate in which a wiring part including a wiring groove and a wiring hole is formed on the surface, and a barrier layer is formed on the surface including the wiring part. A substrate plating method for forming a plating layer, wherein a plating layer is formed by electroless plating on a barrier layer including the surface of the wiring portion, and a wiring plating layer is formed on the plating layer by electrolytic plating. It is characterized by.

  According to a second aspect of the present invention, there is provided a substrate in which a wiring portion comprising wiring grooves and wiring holes is formed on the surface, and a plating layer for embedding the wiring portion is formed on a substrate in which a barrier layer is formed on the surface including the wiring portion. A first plating means for forming a plating layer by electroless plating on the barrier layer including the surface of the wiring portion, and forming a wiring plating layer by electrolytic plating on the plating layer. A second plating means is provided.

  According to invention of Claim 1, the board | substrate plating method which can form the plating layer for wiring easily on the barrier layer containing the wiring part surface can be provided.

  According to the invention described in claim 2, it is possible to provide a substrate plating apparatus that can easily form a wiring plating layer on the barrier layer including the surface of the wiring portion.

  Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, the substrate plating apparatus will be described by taking a semiconductor wafer wiring plating apparatus as an example. FIG. 1 is a diagram showing a planar configuration of a substrate plating apparatus according to claim 1. As shown in the figure, the plating apparatus 10 is provided with a transfer robot 12, a Cu plating tank 13, 13, and a cleaning tank 14 that reciprocate on the rail 11 as indicated by an arrow A.

  Semiconductor wafers to be plated are introduced into the plating apparatus 10 one by one from the inlet 15 by the transfer robot 12, subjected to Cu plating in the Cu plating tank 13, subsequently cleaned in the cleaning tank 14, and discharged from the outlet. 16 is discharged out of the plating apparatus 10.

In the plating apparatus having the above arrangement, the unprocessed semiconductor wafer introduced from the introduction port 15 by the transfer robot 12 is made of SiO ₂ on the conductive layer 106 on the semiconductor wafer W as shown in FIG. An insulating film 105 is formed, and a wiring portion including a wiring groove 101 and a wiring hole (contact hole) 102 is formed in the insulating film 105 by a lithography / etching technique.

  When such a semiconductor wafer is subjected to a Cu plating process in the Cu plating tank 13, a Cu plating layer is formed on the surface of the semiconductor wafer W including the wiring portion including the wiring grooves 101 and the wiring holes 102 as shown in FIG. 103 is formed. In FIG. 2, reference numeral 104 denotes a barrier layer made of TiN or the like.

  The plating process performed in the Cu plating tanks 13 and 13 may be electroless plating or electrolytic plating. For example, the former stage may be electroless plating and the latter stage may be electrolytic plating. The semiconductor wafer on which the Cu plating layer 103 is formed by the Cu plating process is cleaned with a cleaning liquid such as pure water in the cleaning tank 14, and the cleaning robot adheres to the outside of the plating apparatus 10 from the discharge port 16 by the transfer robot 12. Discharged.

  The semiconductor wafer discharged with the cleaning liquid attached from the discharge port 16 is transferred to the next step, for example, a CMP apparatus (not shown), and from the Cu plating layer 103 as shown in FIG. The Cu plating layer on the surface of the semiconductor wafer W is removed leaving the Cu plating layer formed in the wiring groove 101 and the wiring hole 102. Therefore, if the CMP apparatus is disposed adjacent to the discharge port 16, the semiconductor wafer drying process step after the plating process and the cleaning process becomes unnecessary.

  FIG. 3 is a diagram showing a planar configuration of the substrate plating apparatus. As shown in the figure, the plating apparatus 10 is provided with a substrate storage tank 17 containing a storage liquid. The unprocessed semiconductor wafers introduced into the plating apparatus 10 one by one from the introduction port 15 by the transfer robot 12 are stored in the substrate storage tank 17 during the waiting time until the Cu plating tanks 13 and 13 perform the Cu plating process. Immerse in and store.

  FIG. 4 is a diagram showing the configuration of the substrate storage tank 17. As shown in the figure, the substrate storage tank 17 includes a storage tank 17-1, and a bottom of the substrate storage tank 17-1 for mounting the wafer cassette 17-2 and a storage liquid supply nozzle 17-4 for supplying storage liquid. Further, a recovery tank 17-5 is provided at the upper end of the storage tank 17-1 for recovering the storage liquid overflowing from the upper end of the storage tank 17-1. Here, as the storage solution, a dilute sulfuric acid solution or an antioxidant solution for preventing the surface of the Cu plating layer 103 from being oxidized is used in addition to pure water. As a result, it is possible to prevent the formation of an oxide film or particle contamination that hinders the plating process on the surface of the semiconductor wafer during the waiting time of the plating process.

  In the plating apparatus 10 having the above-described configuration, there are three possible methods for processing unprocessed semiconductor wafers introduced into the plating apparatus 10 from the inlet 15 as follows.

  In the first processing method, the substrate is stored temporarily in the substrate storage tank 17, and after the storage, the Cu plating tanks 13 and 13 are subjected to Cu plating treatment, the cleaning tank 14 is cleaned, and the discharge port 16 is discharged.

  In the second processing method, the introduced unprocessed semiconductor wafer is subjected to Cu plating processing in the Cu plating tanks 13 and 13, cleaned in the cleaning tank 14, temporarily stored in the substrate storage tank 17, and discharged from the discharge port 16. .

  The third method is to temporarily store in the substrate storage tank 17, and after the storage, perform Cu plating in the Cu plating tanks 13 and 13, wash in the cleaning tank 14, temporarily store in the substrate storage tank 17, and discharge from the discharge port 16. To do.

  FIG. 5 is a diagram showing a planar configuration of the substrate plating apparatus. As shown in the drawing, a substrate underwater transporter 18 is disposed in the plating apparatus 10 so as to reach the vicinity of the Cu plating tank 13 from the introduction port 15. As shown in FIG. 6, the substrate underwater transporter 18 includes a water channel 18-1, pure water Q is supplied to the water channel 18-1 from a supply port 18-4, and the height of the water surface H is increased in the direction of arrow B. It flows while maintaining the thickness and is discharged from the drain port 18-5. Moreover, the roller conveyor 18-3 which comprises many conveyance rollers 18-2 is arrange | positioned at the bottom part of the waterway 18-1.

  When the unprocessed semiconductor wafer W introduced from the introduction port 15 is placed on the roller conveyor 18-3 at the carry-in end of the substrate underwater transport machine 18 having the above-described configuration, the semiconductor wafer W is purified by pure water Q as indicated by an arrow C. Is transferred through the pure water in the opposite direction to the flow (in the direction of arrow B). Then, it is transferred to the Cu plating tank 13 by the transfer robot 12, subjected to Cu plating treatment, cleaned in the cleaning tank 14, and then discharged from the discharge port 16 to the outside of the plating apparatus 10 by the transfer robot 12.

  FIG. 7 is a diagram showing another planar configuration of the substrate plating apparatus. As shown in the figure, a substrate underwater transporter 18 is disposed in the plating apparatus 10 so as to reach the discharge port 16 from the vicinity of the cleaning tank 14. The configuration of the substrate underwater transporter 18 is the same as that of the substrate underwater transporter 18 shown in FIG.

  Unprocessed semiconductor wafers W introduced into the plating apparatus 10 one by one by the transfer robot 12 from the introduction port 15 are subjected to Cu plating processing in the Cu plating tank 13, and are then transferred to the carry-in end of the substrate underwater transfer machine 18. When placed on the roller conveyor 18-3, the semiconductor wafer W passes through the pure water in the direction opposite to the flow of pure water Q (in the direction of arrow B) as shown by the arrow C to the vicinity of the discharge port 16. Be transported. The semiconductor wafer W transferred to the vicinity of the discharge port 16 is discharged in a state where pure water is attached, that is, in a wet state, by a transfer means arranged outside the plating apparatus 10.

  FIG. 8 is a diagram showing a planar configuration in which a plating device 20 for forming a seed layer is disposed adjacent to the inlet 15 and the outlet 16 side of the plating device 10 having the planar configuration shown in FIG. A plurality of semiconductor wafers are received from a carry-in entrance 21 of the seed layer forming plating apparatus 20 and a wafer cassette (not shown) is carried in, and a seed layer to be described in detail later is formed on the surface of each semiconductor wafer W. The

  Then, the semiconductor wafers W on which the seed layer is formed by the seed layer forming plating apparatus 20 are introduced one by one into the plating apparatus 10 through the introduction port 15 by the transfer robot 12 arranged in the plating apparatus 10, and Cu After being plated with Cu in the plating tanks 13 and 13, cleaned in the cleaning tank 14, transferred to the seed layer forming plating apparatus 20 by the transfer robot 12, and then transferred in the seed layer forming plating apparatus 20. A plurality of wafers are stored in a wafer cassette by a robot or the like, and the wafer cassette is unloaded from the carry-out port 22 to the outside.

As shown in FIG. 2A, an insulating film 105 made of SiO ₂ is formed on the conductive layer 106 on the semiconductor wafer W on the unprocessed semiconductor wafer W on which the wiring plating layer is to be formed. A wiring portion composed of the wiring groove 101 and the wiring hole 102 is formed, and a barrier layer 104 made of TiN, TaN or the like is further formed on the surface thereof. Since this barrier layer 104 is not a conductor, a Cu plating layer cannot be formed directly on the surface by electrolytic plating. Even if the Cu plating layer is formed by electroless plating, it is necessary to form a seed layer on the surface of the barrier layer 104 for starting the growth of metal (Cu in this case).

  In the seed layer forming plating apparatus 20, as shown in FIG. 9, a Cu thin film is formed on the surface of the barrier layer 104 as a seed layer 107 by electroless plating. In order to form a Cu thin film by electroless plating, a palladium treatment is used to form a large number of palladium nuclei for metal growth on the surface of the barrier layer 104, and a metal (here, Cu) is grown around the nuclei. Do.

  As described above, the arrangement of the plating device 20 for forming the seed layer is not limited to the plating device shown in FIG. 1, and is adjacent to the introduction port 15 and the discharge port 16 side of the plating device 10 shown in FIG. It is also possible to arrange them, and it is also possible to arrange them adjacent to the introduction port 15 side of the plating apparatus 10 shown in FIGS.

  FIG. 10 shows a configuration in which a seed layer forming plating device 20, a CMP chamber 30, cleaning modules 40, 41, and 42, and an unload chamber 46 are arranged adjacent to the planar plating device 10 shown in FIG. A CMP apparatus 31 is disposed in the CMP chamber 30, and cleaning units (or cleaning / drying units) 43, 44, and 45 are disposed in the cleaning modules 40, 41, and 42, respectively.

In the apparatus shown in FIG. 10, the seed layer forming plating apparatus 20 forms a seed layer 107 on the surface of the barrier layer 104 of the semiconductor wafer W as shown in FIG. The semiconductor wafers W on which the seed layer 107 is formed are introduced one by one by the transfer robot 12 of the plating apparatus 10 and subjected to Cu plating treatment in the Cu plating tanks 13 and 13, as shown in FIG. 9B. 2 is formed, cleaned in the cleaning tank 14, and transferred to the CMP apparatus 31 in the CMP chamber 30 with the cleaning liquid attached thereto. As shown in FIG. The Cu plating layer on the surface of the semiconductor wafer W is removed while leaving the Cu plating layer formed in 101 and the wiring hole 102.

  The semiconductor wafer W from which the Cu plating layer has been removed leaving the Cu plating layer formed in the wiring groove 101 and the wiring hole 102 is sequentially cleaned by the cleaning machines 43 and 44 of the cleaning modules 40 and 41, and the cleaning machine of the cleaning module 42. A plurality of the semiconductor unload wafers W that have been washed and dried at 45 are accommodated in a wafer cassette disposed in the unload chamber 46, and each wafer cassette is unloaded from the carry-out port 47.

  In the above example, the seed layer forming plating apparatus 20, the CMP chamber 30, the cleaning modules 40, 41, and 42 and the unload chamber 46 are arranged in the plating apparatus 10 shown in FIG. 5. Of course, the plating apparatus 10 shown in FIG. 7 may be disposed adjacent to the plating apparatus 20 for forming the seed layer, the CMP chamber 30, the cleaning modules 40, 41, and 42, and the unload chamber 46.

  The semiconductor wafers W to be plated as described above are introduced into the plating apparatus 10 one by one, cleaned in the Cu plating tank 13 and the cleaning tank 14, and then discharged to the outside of the plating apparatus 10 one by one. Since the plating apparatus 10 is configured, the semiconductor wafers W can be successively introduced into the Cu plating apparatus one by one without being put in the cassette and processed, and particle contamination and oxide film formation can be reduced as much as possible. Even when moving the semiconductor wafer, it is possible to omit the steps such as the drying process by arranging it adjacent to the plating apparatus 10 and to reduce the installation area as a whole by reducing the scale of equipment and the semiconductor wafer wiring plating. The device can be easily constructed.

  In the above example, the substrate plating apparatus is described by taking the semiconductor wafer wiring plating apparatus as an example. However, the substrate is not limited to the semiconductor wafer, and the portion to be plated is limited to the wiring portion formed on the substrate surface. Is not to be done. Moreover, although Cu plating was demonstrated to the example in the said example, it is not limited to Cu plating.

It is a figure which shows the plane structure of the board | substrate plating apparatus of this invention. It is semiconductor wafer sectional drawing which shows an example of the process of plating with the board | substrate plating apparatus of this invention. It is a figure which shows the plane structure of the board | substrate plating apparatus of this invention. It is a figure which shows the structure of the board | substrate storage tank used for the board | substrate plating apparatus of this invention. It is a figure which shows the plane structure of the board | substrate plating apparatus of this invention. It is a figure which shows the structure of the board | substrate underwater conveyance machine used for the board | substrate plating apparatus of this invention. It is a figure which shows the plane structure of the board | substrate plating apparatus of this invention. It is a figure which shows the plane structure which has arrange | positioned the plating apparatus for seed layer formation adjacent to the board | substrate plating apparatus of this invention. It is semiconductor wafer sectional drawing which shows an example of the process of plating with the substrate plating apparatus of this invention, and the plating apparatus for seed layer formation. It is a figure which shows the plane structure which has arrange | positioned the plating apparatus for seed layer formation, CMP chamber, the washing | cleaning module, and the unload chamber adjacent to the substrate plating apparatus of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Plating apparatus 11 Rail 12 Transport robot 13 Cu plating tank 14 Washing tank 15 Inlet 16 Discharge port 17 Substrate storage tank 18 Substrate underwater transport machine 20 Seed layer forming plating apparatus 21 Carrying in port 22 Carrying out port 30 CMP chamber 31 CMP apparatus 40 Cleaning module 41 Cleaning module 42 Cleaning module 43 Cleaning machine 44 Cleaning machine 45 Cleaning machine 46 Unload chamber 47 Unloading port

Claims (2)

A substrate plating method for forming a wiring layer comprising a wiring groove and a wiring hole on a surface, and forming a plating layer for embedding the wiring portion on a substrate on which a barrier layer is formed on a surface including the wiring portion,
A substrate plating method, wherein a plating layer is formed by electroless plating on a barrier layer including the surface of the wiring portion, and a wiring plating layer is formed on the plating layer by electrolytic plating. A substrate plating apparatus for forming a wiring portion comprising a wiring groove and a wiring hole on a surface, and forming a plating layer for embedding the wiring portion on a substrate on which a barrier layer is formed on a surface including the wiring portion,
First plating means for forming a plating layer by electroless plating on the barrier layer including the surface of the wiring portion, and second plating means for forming a plating layer for wiring by electrolytic plating on the plating layer are provided. A substrate plating apparatus characterized by that.

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