JP2007102596A - Central processing unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a central processing unit including a branch prediction means capable of removing a loss related to branch processing with a smaller circuit scale and without using a delay slot. <P>SOLUTION: A program load processing part 22 predicts, based on a branch result signal 35 showing occurrence of branch in an execution processing part 25, whether program data to be decoded includes branch or not, preliminarily acquires, when predicted to include the branch, program data of the branch destination address from a program storage area 21, transfers it with the program data to be decoded to a transfer processing part 23, and transfers first transfer data without branch and second transfer data with branch to a decoding processing part 24. The decoding processing part 24 selects and outputs one of decode data of the first and second transfer data according to the occurrence of branch. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a central processing unit, and more particularly, to a central processing unit including a program branch prediction unit.

  The processing load on a central processing unit (hereinafter referred to as CPU) used in personal computers (hereinafter referred to as personal computers) and electronic devices is increasing year by year, and improvement in processing capacity is desired. Therefore, conventionally, a CPU executes a multi-stage pipeline process (see, for example, Non-Patent Document 1). In pipeline processing, the CPU can directly reduce the processing time related to program branching, which directly leads to improvement in processing capability.

  FIG. 15 is a block diagram showing an example of a CPU that executes the conventional pipeline processing. In the figure, the CPU is loaded into a program storage area (memory) 1 for storing a program, a program load processing section (pre-fetch) 2 for loading a program from the program storage area 1, and a program load processing section 2. The transfer processing unit (Fetch stage) 3 for transferring the program, the decoding processing unit (Decode stage) 4 for decoding the program transferred from the transfer processing unit 3, and the decoded data sent from the decoding processing unit 4 are executed. An execution processing unit (Execute stage) 5 and an execution result storage processing unit (Writeback stage) for writing an execution result sent from the execution processing unit 5 execute pipeline processing of a plurality of stages.

  In the conventional CPU, as shown in the timing chart of FIG. 16, in the first execution unit (cycle) 1T, the transfer processing unit 3 reads the program (instruction) read from the program storage area 1 by the program load processing unit 2. The process F [0] to be transferred to the decoding processor 4 is performed, and in the next execution unit 2T, the transfer processor 3 performs the process F [1} to transfer the second program to the decoder 4 at the same time. The processing unit 4 performs processing D [0] for decoding the first transferred program and outputting the decoded data.

  In the next execution unit 3T, the execution processing unit 5 to which the decoded data is input performs the process E [0] for executing the decoded data, and at the same time, the transfer processing unit 3 transfers the third program to the decoding processing unit 4. The process F [2} is performed, and the process D [1] is performed in which the decryption processing unit 4 decrypts the transferred second program and outputs decrypted data. In the next execution unit 4T, the execution result storage processing unit 6 writes the execution result executed by the execution processing unit 5, and the execution processing unit 5 to which the second decoded data is input Processing E [1] for executing the decoded data is performed, and processing D [2] for decoding the third program transferred by the decoding processing unit 4 and outputting the decoded data is performed.

  At this time, the execution result storage processing unit 6 determines whether or not there is a branch that is a process for changing the execution order of the program to be executed next by the execution processing unit 5. The program transfer to the unit 3 and the program transfer from the transfer processing unit 3 to the decoding processing unit 4 are not performed. Thereafter, the execution result storage processing unit 6 performs the process W [1] for writing the execution result of the second program executed by the execution processing unit 5 in the execution unit 5T, and then at the next execution unit 6T stage. The process W [2] for writing the execution result of the third program executed by the execution processing unit 5 is performed, it is determined whether or not a branch has occurred, and a branch result signal 7 indicating the determination result is sent to the program load processing unit Send to 2.

  When the input branch result signal 7 indicates that no branch has occurred, the program load processing unit 2 reads the fourth program from the program storage area 1 in the next execution unit 7T, and the transfer processing unit 3 decodes it. When processing F [3] to be transferred to the unit 4 is performed and the input branch result signal 7 indicates that a branch has occurred, the seventh execution program at the branch destination is read from the program storage area 1 in the next execution unit 7T. Then, the transfer processing unit 3 performs processing F [6] in which the transfer processing unit 3 transfers it to the decoding processing unit 4. Thereafter, the same operation is repeated.

  Therefore, the branch of the program in the conventional CPU is determined by the execution result storage processing unit 6 of FIG. 15 to determine that there is a branch, and the program load processing unit 2 uses the result to determine the branch destination program in the program storage area 1. The branch processing is performed by further reading, and a delay slot is inserted into the branch of the program until the branch can be determined as shown in FIG. Therefore, in the case of FIG. 16, in the conventional CPU, every time a branch process occurs, a delay of 3 CPU cycles as shown in 4T to 6T occurs. As the amount of programs increases, the number of branches increases, and the CPU operation becomes enormous. The problem was that a long run time loss occurred.

  Therefore, conventionally, in order to reduce the overhead of the above branch processing, a CPU (for example, see Patent Document 1) having a function of predicting a branch destination from the branch occurrence frequency, for branch prediction A CPU having a plurality of pipeline processes (see, for example, Patent Document 2) has been proposed.

  FIG. 17 is a block diagram showing an example of a conventional CPU described in Patent Document 1 described above. In the figure, the same components as those in FIG. 15 are denoted by the same reference numerals, and the description thereof is omitted. In the conventional CPU shown in FIG. 17, the program load processing unit 8 registers the branch destination address corresponding to the address of the branch instruction, the number of accesses, and the branch prediction result in the buffer 9 as a table, so that a branch occurrence pattern is obtained. This improves the accuracy of branch prediction.

  FIG. 18 shows a block diagram of an example of a conventional CPU described in Patent Document 2 above. In the figure, the same components as those in FIG. 15 are denoted by the same reference numerals, and the description thereof is omitted. The conventional CPU shown in FIG. 18 is a type that uses a delay slot without performing branch prediction, but before introducing the data acquired from the program storage area 1 into the pipeline, whether or not it is a branch determination instruction in advance. Is determined by the program load processing unit 10, a non-branch instruction without a branch determination instruction is stored in the buffer 11a, a branch instruction with a branch determination instruction is stored in the buffer 11b, and a non-branch instruction from the buffer 11a is transferred. The pipeline processing is performed by the unit 3a, the decoding processing unit 4a, and the execution processing unit 5a, and the branch instruction from the buffer 11b is pipelined by the transfer processing unit 3b, the decoding processing unit 4b, and the execution processing unit 5b. Is processed by the execution result storage processing unit 12.

Tetsuya Fujihiro, “What the CPU is doing, the world of wonder hidden in silicon chips”, Subaru Corporation, published September 2002 Japanese Patent No. 2567978 JP 2004-192021 A

  However, the conventional CPU shown in FIG. 17 has a problem that the prediction accuracy of the branch destination from the address cannot be increased unless the number of accesses to the address causing the branch is large, and all the branch patterns. Therefore, the circuit size cannot be predicted, and there is a possibility that the circuit may be enlarged depending on the contents of the program.

  Further, the conventional CPU shown in FIG. 18 has a configuration in which the processing stages other than the final processing stage form two pipeline processing stages, so that the normal pipeline circuit scale is simply nearly double. Increasing is a challenge.

  The present invention has been made in view of the above points, and provides a central processing unit having a branch prediction unit capable of removing a loss associated with branch processing without using a delay slot with a smaller circuit scale. Objective.

To achieve the above object, the present invention transfers a program storage area for storing program data, a program load processing section for loading program data from the program storage area, and program data transferred from the program load processing section A transfer processing unit, a decoding processing unit that decodes the program data transferred from the transfer processing unit, and a process for executing the decoded data sent from the decoding processing unit and changing the execution order of the program data. An execution processing unit that generates a branch result signal indicating whether or not a certain branch has been performed and outputs the branch result signal to the program load processing unit, and an execution result storage processing unit that writes the execution result sent from the execution processing unit, A central processing unit that executes multi-stage pipeline processing,
The program load processing unit determines whether or not there is a branch in the program data to be decoded based on the branch result signal based on the branch result signal and the storage unit that stores the program data to be decoded from the program storage area. When it is determined that the program data of the branch destination address is acquired from the program storage area in advance and stored in the storage unit, the program data stored from the storage unit is output to the transfer processing unit, and the branch result A control signal for instructing a storage location in the transfer processing unit of the output program data based on the signal and a control signal for instructing selection of the decoded data output from the decoding processing unit, and
The transfer processing unit stores the program data transferred from the program load processing unit in different locations depending on whether the program data is the data of the branch destination address based on the control signal indicating the storage location. Transfer data storage means to perform, and among the program data stored in the transfer data storage means, the first program data to be decoded when there is no branch and the second program data to be decoded when there is a branch Transfer data selecting means for selecting program data and outputting the first and second transfer data, respectively,
The decoding processing unit includes decoding / storing means for separately decoding the first and second transfer data input from the transfer processing unit to generate and store the first and second decoded data, and program load Decoding data selection means for selecting one of the first and second decoding data from the decoding / storing means and outputting to the execution processing section in accordance with a control signal for instructing selection of decoding data from the processing section. Features.

  In this invention, based on a branch result signal indicating whether or not a branch has occurred in the execution processing unit, the program load processing unit determines whether or not there is a branch in the program data to be decoded. When it is determined, the program data of the branch destination address is obtained in advance from the program storage area, set together with the program data to be decoded to the transfer processing unit and temporarily stored, and then the first transfer when no branch occurs Since the data and the second transfer data when the branch occurs are set in the decoding processing unit and are decoded respectively, one of the decoded data is selected depending on whether the branch has occurred or not. Even if the pipeline processing system is not provided, the number of cycles required from the branch occurrence determination to the branch destination process can be reduced to zero.

  According to the present invention, the number of cycles required from the branch occurrence determination to the transition to the branch destination process can be shortened to zero without providing two pipeline processing systems. In addition, the overhead for the branch processing time can be eliminated without using the delay slot.

  Next, the best mode for carrying out the present invention will be described with reference to the drawings. First, the relationship between the variables h, i, j, k, m, n, p, and q used in this specification will be described. Variables h, m, p, and q indicate program addresses in the fetch, decode 1 (decode1), execute (execute), and writeback (writeback) stages, respectively. Since there are two decoding (Decode) stages, they are distinguished as decoding 1 (Decode 1) and decoding 2 (Decode 2). n indicates the address of the program in the Decode2 stage. i indicates a branch prediction destination address. j indicates the address next to the branch prediction destination address i before 1T execution time. k predicts that the branch prediction destination address i before 1T execution time branches, and indicates the prediction destination address of i.

  FIG. 1 is a block diagram at the time of pipeline processing of an embodiment of a central processing unit according to the present invention. As shown in the figure, the central processing unit (CPU) of the present embodiment includes a program storage area (memory) 21 for storing programs and a program load processing unit (pre-) for loading programs from the program storage area 21. fetch) 22, a transfer processing unit (Fetch stage) 23 for transferring the program loaded in the program load processing unit 22, a decoding processing unit (Decode stage) 24 for decoding the program transferred from the transfer processing unit 23, An execution processing unit (Execute stage) 25 for executing the decoded data sent from the decoding processing unit 24, and an execution result storage processing unit (Writeback stage) 26 for writing the execution result sent from the execution processing unit 25. Execute multi-stage pipeline processing.

  In this embodiment, the program load processing unit 22, the transfer processing unit 23, and the decoding processing unit 24 are connected to a signal line for transmitting a signal transfer data update instruction signal 31 that is an output from the program load processing unit 22, and a transfer data selection signal. 32, a signal line for transmitting a decoding instruction signal 33, a signal line for transmitting a decoded data selection signal 34, and a signal for transmitting a branch result signal 35 that is an output from the execution processing unit 25. The line is connected to the program load processing unit 22.

  As shown in FIG. 2A, the program storage area 21 stores program data used in the central processing unit of the present embodiment corresponding to the address. As shown in FIG. 2B, each piece of program data includes an operation code having a fixed bit width x, an operand A (bit width y) and an operand B (bit width z) having a variable bit width. If the program data bit width of the central processing unit to be used is 32 bits, the bit width addition value (x + y + z) of each of the above operation code, operand A, and operand B is “32” at the maximum.

  FIG. 2C shows the inside of the program data when the program data bit width of the central processing unit is 32 bits and the operation code has a branch instruction. As shown in FIG. 5C, the branch instruction has a fixed bit width x equivalent to the operation code. The bit width representing the branch destination address has a fixed width u in which the added value with the bit width of the operation code does not exceed “32”. In FIG. 2C, the remaining bit width v (= 32− (x + u)) is an N / A (not available) area.

  Next, the configuration of the program load processing unit 22 will be described. FIG. 3 shows a block diagram of an embodiment of the program load processing unit 22 of FIG. The program load processing unit 22 includes a program data storage unit 221 and a sequence processing unit 222 as shown in FIG. The program data storage unit 221 stores the program data 36 from the program storage area 21 of FIG. 1 and then outputs the program data 36 to the transfer processing unit 23 of FIG. Further, the sequence processing unit 222 receives the branch result signal 35 from the execution processing unit 25 of FIG. 1 as an input, outputs a transfer data update instruction signal 31 and a transfer data selection signal 32 to the transfer processing unit 23 of FIG. A decoded data selection signal 34 and a decoding instruction signal 33 are output to the processing unit 24, and a read signal 37 is output to the program storage area 21.

  Next, the operation of the program load processing unit 22 will be described. FIG. 4 is a flowchart for explaining the schematic operation of the program load processing unit 22. The program load processing unit 22 stores the program data from the program storage area 21 in the program data storage unit 221, and when the sequence processing unit 222 starts to operate based on the program data (step S1), at the start (CPU 1T in execution unit: T is the unit time (operation clock frequency)) After performing the initial processing 1 described later (step S2), it is determined whether or not the next CPU step has been shifted (step S3) If so, it is determined whether the initial process 2 has been completed (step S4).

  If the initial process 2 has not yet been completed, the initial process 2 described later is performed in the next cycle (2T) (step S5). If the initial process 2 has been completed, it is determined whether the initial process 3 has been completed. (Step S6). When the initial process 3 has not been performed yet, the initial process 3 to be described later is performed in the next cycle (3T) (step S7). If the initial process 3 is also completed, the subsequent cycle (3T) and thereafter Branch prediction, which will be described later, is performed in each cycle (step S8).

  FIG. 5 shows a flowchart for explaining the detailed operation of the initial process 1 in step S2 of FIG. In the initial process 1, the program start address (here, assumed to be 0x0) is added to the fetch stage F_N [h] at the address h required when the content to be processed 1T before is not branched (FIG. 13, FIG. 14) (step S11), m = 0 is set in the decode stage D_1 [m] at the address m (step S12), and p = 0 is set in the execute stage E [p] at the address p. After that (step S13), the transfer data update instruction signal 32 and the transfer data selection signal 33 are output to the transfer processing unit 23 (step S14), and the process is terminated (step S15).

  FIG. 6 shows a flowchart for explaining the detailed operation of the initial process 2 in step S5 of FIG. In the initial process 2, when the process is started, the address next to the start address (here, 0x1 is assumed) is set in F_N [h] (step S21), and m = 1 is set in D_1 [m] ( Step S22) The branch predicted value (address) y from F_N [0] is set to the fetch stage F_B [i] at the address i required when the content scheduled to be processed 1T before is no branch (i = y) (step S23), and it is determined whether a branch prediction value exists (step S24). Note that F_N [] contains address data added to the address scheduled to be processed 1T before, and F_B [] has a branch destination address when the address scheduled to be processed 1T branches. Contains data.

  If there is a branch prediction value, the data at address i is set in F_B [j] in transfer processing unit 23 (step S25), and then address i is set in decode stage D_2 [n] at address n (n = i) (step S26). When there is no branch prediction value, the processing of steps S25 and S26 is jumped and nothing is set. Subsequently, the transfer data update instruction signal 32 and the transfer data selection signal 33 are output to the transfer processing unit 23, and the decoding instruction signal 33 and the decoded data selection signal 34 are output to the decoding processing unit 24 (step S27). Processing 2 ends (step S28).

  FIG. 7 shows a flowchart for explaining the detailed operation of the initial process 3 in step S7 of FIG. Initial processing 3 sets the address i (j = i + 1) to the fetch stage F_BN [j] at the address j required when the content scheduled to be processed 1T before the start of processing is branched, and 1T before The branch predicted value v from F_B [i] is set (k = v) to the fetch stage F_BB [k] at the address k required when the content to be processed has a branch, and F_B [i] is set to F_N [ h] branch prediction value u is set (i = u) (step S31), and it is determined whether branch prediction address j exists (step S32). If it exists, j_address is assigned to F_BN [j]. Data is set (step S33), and if it does not exist, it is determined whether the branch prediction address k exists (step S34).

  Note that F_BN [] contains address data added to the address scheduled to be processed 1T before, and F_BB [] has a branch destination address when the address scheduled to be processed 1T branches. Contains data.

  If the branch prediction address k exists, the address data of k is set in F_BB [k] (step S35). If not, it is determined whether the branch prediction address i exists (step S36). If the address i exists, the address data of i is set in F_B [i] (step S37), and if the branch prediction address i does not exist, the process proceeds to step S38.

  Accordingly, in the above steps S32 to S37, it is determined whether or not the branch prediction addresses j, k, i exist. If they exist, the address data is set in the transfer processing unit 23. Also do not set. Subsequently, the data at address h + 1 is set in F_N [h], the transfer data update instruction signal 32 and the transfer data selection signal 33 are output to the transfer processing unit 23, and the decoding instruction signal 33 and the decoded data are output to the decoding processing unit 24. The selection signal 34 is output. After the process of step S38, the initial process 3 is terminated (step S39).

  FIG. 8 is a flowchart for explaining the detailed operation of the branch prediction process in step S8 of FIG. When the program load processing unit 22 starts the branch prediction process, it receives the branch result signal 35 from the execution processing unit 25 in FIG. 1 to determine whether or not a branch has occurred (step S41), and the branch has occurred. Regardless of the case, the predetermined data is stored in each stage in preparation for the next branch prediction (steps S42 and S43). Here, the predetermined data includes data stored in F_N [h + 1] corresponding to an address obtained by incrementing the address “h” processed immediately before F_N [], and F_N [] to F_B []. When the address “h” used in h] has a branch process, the data stored in F_B [y] corresponding to the branch destination address “y” and the F_B [ i] The address stored in F_BN [i + 1] corresponding to the address obtained by incrementing the address “i” by one and the address “i” processed immediately before F_BB [] have branch processing. , Data stored in F_BB [k] corresponding to the branch destination address “k”.

  If a branch has occurred, the data of the decoding stage D_2 [m] is set as the decoded data output to E [p] of the execution processing unit 25, and the address j is set to the decoding stage D_1 [m] (m = j), the address k is set to D_2 [n] (n = k), the data of the address j + 1 is set to F_N [h], and the branch destination address from F_BN [j] is previously set to F_B [i]. The predicted value a is set (i = a), the address k + 1 is set to F_BN [j] (j = k + 1), and the predicted value b predetermined as the branch destination address from F_BB [k] is set to F_BB [k]. Is set (k = b) (step S42).

  When the branch has not occurred, the data of the decoding stage D_1 [m] is set as the decoded data output to E [p] of the execution processing unit 25, and the address h is set to the decoding stage D_1 [m] ( m = h), an address i is set in D_2 [n] (n = i), and a predicted value b set in advance as a branch destination address from F_B [i] is set in F_BB [k] (k = b) F_BN [j] is set to address i + 1 (j = i + 1), F_B [i] is set to a predetermined predicted value a as a branch destination address from F_N [h] (i = a), and F_N [j] The data at address h + 1 is transferred to h] (step S43).

  If there is a branch, the process proceeds to step S42. If there is no branch, and the process of step S43 is completed, it is confirmed whether or not there is a branch prediction address j, i, k set. When the sequence processing unit 222 in FIG. 3 determines that the branch prediction address exists, the program load processing unit 22 acquires the program data at the branch destination address in the program data shown in FIG. 3, when data is stored in the program data storage unit 221 and then transferred to the transfer processing unit 23, any one of the four transfer data storage units 231 to 234 in the transfer processing unit 23, which will be described later, according to the flowchart of FIG. 8. Set crab and store.

  On the other hand, if there is no branch prediction address, the program data acquisition operation is not performed. For this reason, program data is not stored in any of the transfer data storage units 231 to 234 that are scheduled to be stored when a branch prediction address exists.

  That is, the sequence processing unit 222 first determines whether or not the branch prediction address j exists (step S44), and if it exists, transfers the j address data to the transfer processing unit 23 in F_BN [j] (step S44). S45) If not, it is determined whether the branch prediction address i exists (step S46).

  If the branch prediction address i exists, the address data of i is transferred to F_B [i] to the transfer processing unit 23 (step S47). If not, it is determined whether the branch prediction address k exists. (Step S48). If the branch prediction address k exists, the address data of k is transferred to F_BB [k] to the transfer processing unit 23 (step S49), but if it does not exist, the transfer data update instruction signal 32 and the transfer are transferred to the transfer processing unit 23. After outputting the data selection signal 33 and outputting the decoding instruction signal 33 and the decoded data selection signal 34 to the decoding processor 24 (step S50), the branch prediction process is terminated (step S51).

  Next, the configuration and operation of the transfer processing unit 23 in FIG. 1 will be described. FIG. 9 shows a block diagram of an embodiment of the transfer processing unit 23 of FIG. In FIG. 9, the transfer processing unit 23 includes four transfer data storage units 231 to 234 to which transfer data 38 and a transfer data update instruction signal 31 are input from the program load processing unit 22, and transfer data storage units 231 to 234, respectively. Output transfer data is selected based on a transfer data selection signal 32 from the program load processing unit 22 and a transfer data selection unit 235 that outputs two types of transfer data 1 and 2 in parallel. The transfer data storage units 231 to 234 store the input transfer data only when the transfer data update instruction signal 31 is active.

  Next, the operation of the transfer processing unit 23 will be described together with a detailed operation explanation flowchart shown in FIG. When starting the processing, the transfer processing unit 23 first determines whether or not the transfer data update instruction signal 31 is generated in step S41 (step S53), and if so, according to the transfer data update instruction signal 31. The transfer data 38 from the program load processing unit 22 is stored in the transfer data storage units 231 to 234 (step S54). If no transfer data 38 is generated, the transfer data 38 is not stored in the transfer data storage units 231 to 234.

  Subsequently, the transfer data selection unit 235 determines whether or not the transfer data selection signal 32 is generated (step S55). If it is generated, the transfer data selection unit 235 stores the transfer data selection signal 32 in the transfer data storage units 231 to 234 according to the transfer data selection signal 32. Two types of transfer data 39 and 40 are selected from the transferred data and output in parallel.

  The transfer data storage units 231, 232, 233, and 234 store the transfer data 38 processed in the stages F_N [], F_B [], F_BN [], and F_BB [], respectively. That is, the transfer data storage unit 231 stores the transfer data 38 when there is no branch from the address executed 1T before stage F_N [h], and the transfer data storage unit 232 executes 1T before stage F_B [i]. The branch predicted transfer data 38 from the address to be stored is stored. The transfer data storage unit 233 stores the transfer data at the branch prediction address +1 before 1T in the stage F_BN [j], and the transfer data storage unit 234 stores the transfer data from the branch prediction address 1T before in the stage F_BB [k]. The branch predicted transfer data 38 is stored.

  If no branch has occurred, the transfer data selection unit 235 selects the transfer data to be processed at the stages F_N [] and F_B [] stored in the transfer data storage units 231 and 232 according to the transfer data selection signal 32. If the branch is generated, the transfer data processed in the stages F_BN [] and F_BB [] stored in the transfer data storage units 233 and 234 are selected and output in parallel. .

  Next, the configuration and operation of the decoding processing unit 24 in FIG. 1 will be described. FIG. 11 shows a block diagram of an embodiment of the decoding processor 24 of FIG. As shown in FIG. 11, the decoding processing unit 24 includes decoding units 241 and 242, decoded data storage units 243 and 244, and a decoded data selection unit 245. The decryption unit 241 receives the first transfer data 39 from the transfer processing unit 23 and is supplied with the decryption instruction signal 33 from the program load processing unit 22. The decryption unit 242 receives the second transfer from the transfer processing unit 23. Data 40 is input, and a decoding instruction signal 33 is supplied from the program load processing unit 22, and the transfer data 39 and 40 are decoded according to the decoding instruction signal 33, respectively.

  The decoded data storage units 243 and 244 store the decoded data output from the decoding units 241 and 242 independently of each other. The decoded data selection unit 245 selects and reads the decoded data stored in one of the decoded data storage units 243 and 244 in accordance with the decoded data selection signal 34 supplied from the program load processing unit 22, and executes the execution processing unit 25. Is output as decoded data 41.

  Next, the operation of the decoding processing unit 24 will be described together with the detailed operation explanation flowchart shown in FIG. When starting the process, the decoding processing unit 24 first determines whether the decoding instruction signal 33 is generated (input) or not (step S61). If it is generated, the transfer processing unit 24 according to the decoding instruction signal 33 The transfer data 39 and 40 from 23 are decoded by the decoding units 241 and 242, respectively, and the obtained decoded data are supplied to the decoded data storage units 243 and 244 for storage (step S62).

  When the decoding instruction signal 33 has not been generated, the decoding process is not performed. Subsequently, the decoded data selection unit 245 determines whether or not the decoded data selection signal 45 is generated (input) (step S63). If it is generated, the decoded data is stored according to the decoded data selection signal 45. One of the decoded data stored in the units 243 and 244 is selected and output as the decoded data 41 to the execution processing unit 25 (step S64), and the decoding process is terminated (step S65). When it is determined that the decoded data selection signal 45 is not generated (not input), the decoded data selection unit 245 ends the decoding process without performing the selection operation of the decoded data (step S65).

  The decoding process performed using the decoding unit 241, the decoded data storage unit 243, and the decoded data selection unit 245 is stage D_1 [], and the decoding unit 242, the decoded data storage unit 244, and the decoded data selection unit 245 are used. The decoding process performed in this way is stage D_2 []. When the branch has not occurred, the decoded data selection unit 245 selects the decoded data stored in the decoded data storage unit 243 (selects the decoded data by the stage D_1 []), and the branch has occurred. In this case, the decoded data stored in the decoded data storage unit 244 is selected (decoded data by stage D_2 [] is selected.

  Next, the operation when there is no branch processing of the central processing unit of the embodiment of FIG. 1 described above will be described with reference to FIG. In FIG. 13, the thick frame indicates the stage actually operating in the transfer processing unit 23 (the same applies to FIG. 14 described later).

  First, in the first cycle 1T (hereinafter, 1T), the program load processing unit 22 executes the initial process 1 of step S2 in FIG. 4, and the saved content of each transfer data is h = 0 (F_N [h]). Since the program start address is 0x0), F_N [0]. F_B [i], F_BN [j], and F_BB [k] are not defined. That is, stage F_N [0] in which the program data of the program start address is stored in the transfer data storage unit 231 in the transfer processing unit 23 of FIG. 9 is executed, but the data is stored in the transfer data storage units 232 to 234. Not.

  In addition, since pipeline processing in 1T performs start address processing in each stage, D_1 [m], E [p], and W [q] are D_1 [0], E [0], and W [0], respectively. Is set. D_2 [n] is not defined.

  In 2T of the next cycle, the program load processing unit 22 performs the initial process 2 of step S5 in FIG. 4, and the storage content of each transfer data is F_N [h], the execution address in 1T (previous cycle) is Since it is a start address, it is set as h ++ and set as an execution address when there is no branch. In F_B [i], it is not possible to determine whether or not to enter branch processing while F_N [0] is being decoded in 1T. Extract the branch destination from the register set in. If the predicted branch destination address is y, it is determined whether or not the branch destination address y exists. If it exists, the data at the branch destination address destination is set in F_B [i] and stored.

  That is, the decoding processing unit 24 decodes the data processed at the stage F_N [0] by the transfer processing unit 23 (stage D_1 (m = h)). Meanwhile, at the same time, the transfer processing unit 23 executes stage F_N [h = h + 1] for storing program data at an address obtained by incrementing the program start address by one in the transfer data storage unit 231 in the transfer processing unit 23 of FIG. At the same time, the stage F_B [i = y] for storing the program data of the predicted branch destination address y in the transfer data storage unit 232 is executed.

  In the next cycle 3T, the decoding processing unit 24 simultaneously decodes the data of the addresses h and i, that is, the data transferred from the transfer data storage units 231 and 232, and selects whether there is a branch or not. (Stage D_1 [m = h], D_2 [n = i]). In the execution processing unit 25, the decoded data of the start address transferred to the transfer processing unit 23 in 1T input from the decoding processing unit 24 is executed (stage E [p = h]).

  For F_N [h], a value h ++ obtained by advancing the address of F_N [h] by 2T is used. For F_BN [j], the address i ++ value when there is no branch at F_B [i = y] at 2T is used. F_BB [k] is predicted to have a branch at F_B [i = y] in 2T, the branch destination v is obtained, and the address k = v. For F_B [i], F_N [h] at 2T is expected to have branch processing, and the branch destination u is extracted and i = u.

  That is, the transfer processing unit 23 stores the program data of the value h ++ obtained by advancing the address of F_N [h] in 2T by one in the transfer data storage unit 231 in the transfer processing unit 23 of FIG. 9. F_N [h = h + 1 ], And the stage F_B [i = u] for storing the program data of the predicted branch destination address u in the transfer data storage unit 232 is executed, and there is no branch at F_B [i = y] in 2T. Stage F_BN [j = i + 1] for storing the program data of the address i ++ in the transfer data storage unit 233 and the stage F_BB [for storing the program data of the predicted branch destination address v in the transfer data storage unit 234 k = v].

  In the next cycle 4T, the execution result storage processing unit 26 performs a process of writing the execution result of the decoded data of the first program data sent from the execution processing unit 25 (stage W [q = h]), and the execution processing unit 25 executes the 3T decrypted data input from the decryption processing unit 24 (stage E [p = h]). In the decryption processing unit 24, data at addresses h and i, that is, transfer data storage units 231 and 232 are stored. The data transferred from is simultaneously decoded, so that it is possible to select whether there is a branch or not (stage D_1 [m = h], D_2 [n = i]). Further, processing for storing data at addresses h = h + 1, i = a, j = i + 1, k = b is executed in the transfer data storage units 231 to 234 (stages F_N [h = h + 1], F_B [ i = a], F_BN [j = i + 1], F_BB [k = b]). Thereafter, the same operation is performed.

  Next, the operation when there is a branch process of the central processing unit of the embodiment of FIG. 1 will be described with reference to FIG. In FIG. 14, 1T to 3T are the same as those in FIG. That is, in 4T, the start address data acquired in 1T is executed by the execution processing unit 25 in 3T, so that a branch has occurred.

  Then, since the data of D_2 [n] decoded in anticipation of branching at 3T is required to be executed by the execution processing unit 25 next, the result obtained by decoding the data acquired at the address n in E [p] Transfer D_2 [n]. The execution processing unit 25 outputs a branch result signal 35 that informs that a branch has occurred to the program load processing unit 22. In the branch process of the program load processing unit 25 that has determined that a branch has occurred, the address j + 1 of F_BN [j] in 3T is used as F_N [h]. This is because the branch destination is determined to be address j. In F_B [i], a branch destination address a that is predicted to have branch processing when F_B [j] is executed in 3T is acquired and i = a is set. In F_BN [j], k + 1 is assumed assuming that there is no branch process in F_BB [k] in 3T. In F_BB [k], a branch destination address b that is predicted to have branch processing in F_BB [k] in 3T is acquired, and k = b is set.

  When a branch occurs, the same procedure as the above 3T and 4T is repeated. As described above, according to the present embodiment, since the branch of the program to be processed is always predicted, the branch destination is determined based on the branch occurrence determination in the program load processing unit 22 in the conventional central processing unit shown in FIG. As can be seen from FIG. 14, the three cycles required until the transition to the process is shortened to 0 cycle, and branch processing can be performed without time overhead.

  It can be applied to all CPUs using a plurality of stages and pipeline configurations.

It is a block diagram at the time of pipeline processing of one embodiment of the central processing unit of the present invention. It is explanatory drawing of an example of the program data in the program storage area | region in FIG. FIG. 2 is a block diagram of an embodiment of a program load processing unit in FIG. 1. It is a flowchart for operation | movement description of the program load process part of FIG. 5 is a flowchart for explaining in detail the initial process 1 of FIG. 4. 5 is a flowchart for explaining in detail the initial process 2 of FIG. 4. 5 is a flowchart for explaining in detail the initial process 3 of FIG. 4. 5 is a flowchart for explaining details of branch prediction in FIG. 4. FIG. 2 is a block diagram of an embodiment of a transfer processing unit in FIG. 1. 10 is a flowchart for explaining the operation of the transfer processing unit in FIG. 9. It is a block diagram of one Embodiment of the decoding process part in FIG. It is a flowchart for operation | movement description of the decoding process part of FIG. It is a timing chart when there is no branch processing in one embodiment of the central processing unit of the present invention. It is a timing chart in case there exists a branch process in one embodiment of the central processing unit of the present invention. It is a block diagram of an example of the central processing unit which performs the conventional pipeline processing. It is a timing chart in case there exists a branch process of the conventional central processing unit. FIG. 11 is a block diagram of a central processing device disclosed in Patent Document 1 during pipeline processing. 10 is a block diagram of a central processing device of Patent Document 2 during pipeline processing. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 21 Program storage area 22 Program load process part 23 Transfer process part 24 Decoding process part 25 Execution process part 26 Execution result preservation | save process part 31 Transfer data update instruction signal 32 Transfer data selection signal 33 Decoding instruction signal 34 Decoding data selection signal 35 Branch result Signal 36 Program data 37 Read signal 38-40 Transfer data 41 Decoded data 221 Program data storage unit 222 Sequence processing unit 231-234 Transfer data storage unit 235 Transfer data selection unit 241, 242 Decoding unit 243, 244 Decoded data storage unit 245 Decoding Data selection part

Claims (1)

A program storage area for storing program data, a program load processing section for loading program data from the program storage area, a transfer processing section for transferring program data transferred from the program load processing section, and the transfer processing A decoding processing unit that decodes the program data transferred from the decoding unit, and a branch that is a process for changing the execution order of the program data while executing the decoding data sent from the decoding processing unit An execution processing unit that generates a branch result signal indicating whether or not the program has been executed and outputs the branch result signal to the program load processing unit, and an execution result storage processing unit that writes the execution result sent from the execution processing unit. A central processing unit for performing pipeline processing,
The program load processing unit
Storage means for storing the program data read from the program storage area and decrypted from now on;
Based on the branch result signal, it is determined whether or not the program data to be decoded has the branch, and when it is determined that the branch is present, the program data of the branch destination address is acquired from the program storage area in advance. And storing the stored program data to the transfer processing unit and instructing at least a storage location of the output program data in the transfer processing unit based on the branch result signal A signal and a means for outputting a control signal for instructing selection of decoded data output from the decoding processing unit,
The transfer processing unit
Transfer data storage means for storing the program data transferred from the program load processing unit in different locations depending on whether or not the program data is data of a branch destination address based on a control signal indicating the storage location When,
Of the program data stored in the transfer data storage means, the first program data to be decoded when there is no branch and the second program data to be decoded when there is a branch are selected. Transfer data selection means for outputting as first and second transfer data respectively,
The decryption processing unit
Decoding / storing means for separately generating the first and second decoded data by separately decoding the first and second transfer data input from the transfer processing unit;
In accordance with a control signal for instructing selection of the decoded data from the program load processing unit, one of the first and second decoded data from the decoding / storing unit is selected and output to the execution processing unit And a central processing unit.

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