JP2007102132A - Display element driving circuit and liquid crystal display device equipped therewith, and display element driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a display device with which a higher effect of reducing electric power consumption can be obtained by most appropriately performing a charge share by short-circuiting of source-bus lines before charging a pixel capacitor in a display device of a hold type. <P>SOLUTION: A control logic 42 compares a video signal in the latest scanning line stored in a line memory 421 with a video signal before one scanning line and selects the data signal line to be short-circuited. A short circuit 2 of a source driver 2 performs charge recovery between the source bus lines by short-circuiting the selected data signal lines. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display element driving circuit for driving an active matrix display element, a liquid crystal display device including the display element driving circuit, and a display element driving method.

  In a hold-type display device (for example, a liquid crystal display device), a driving method is adopted in which analog image signals are sequentially sampled and the sampled analog signals are held in pixel capacitors arranged in a matrix. At this time, the sampled analog signal is written into the pixel capacitance via the source bus line.

  Here, since parasitic capacitance occurs in the source bus line, every time data is written to the pixel capacitance, charging and discharging are repeated not only in the pixel capacitance but also in the source bus line. The charging / discharging power in the parasitic capacitance of the source bus line is an obstacle to low power consumption in the display device.

Patent Document 1 discloses a technique for reducing power consumption in charging / discharging in such a source bus line. That is, in the method of Patent Document 1, every time the polarity of the output terminal of the source driver is switched, the output terminals are short-circuited for a certain period to perform charge recovery (charge sharing), thereby reducing power consumption in the display device. Is disclosed.
JP 2004-279626 A (publication date October 7, 2004)

  In the method of Patent Document 1, the output terminals of the source driver are short-circuited, so that charge movement occurs between the source bus lines, and the potentials of the source bus lines are averaged. In addition, since the method of Patent Document 1 assumes dot inversion driving, the charge / discharge amount of the entire source bus line is reduced by averaging the potential of the source bus line every time the polarity is switched. Thus, an effect of reducing power consumption can be obtained.

  However, in the configuration of Patent Document 1, all the source bus lines are short-circuited at the same time. In this case, although a certain amount of power consumption reduction effect is recognized, an optimum power consumption reduction effect cannot be obtained. That is, when the direction of potential change in all the source bus lines is biased in the + direction or the-direction, if all the source bus lines are short-circuited at the same time, the biased charge prevents the charge sharing effect due to the short-circuiting of the lines. Acts on direction. Therefore, it cannot be said that the method of Patent Document 1 has a sufficient power consumption reduction effect.

  The present invention has been made in view of the above problems, and its object is to optimize charge sharing by short-circuiting a source bus line in a hold-type display device before charging a pixel capacitor. This is to realize a display device that can achieve a higher power consumption reduction effect.

  In order to solve the above problems, a display element driving circuit according to the present invention includes a plurality of scanning signal lines and a plurality of data signal lines provided to intersect each other, and the intersection of the scanning signal lines and the data signal lines. A display element driving circuit for driving a display element having a pixel connected to a part via a thin film transistor, wherein the video signal in the latest scanning line is compared with the video signal in the previous scanning line, and the data signal line Data to be short-circuited based on the comparison unit that calculates the potential level change direction and the potential level change amount, and the potential level change direction and potential level change amount for each data signal line calculated by the comparison unit. It has the selection part which selects a signal line, and the data signal line short circuit part which short-circuits the data signal lines selected by the said selection part, It is characterized by the above-mentioned.

  According to the above configuration, the comparison unit calculates the potential level change direction and the potential level change amount for each data signal line from the comparison result between the video signal in the latest scan line and the video signal in the previous scan line. . The selection unit selects a data signal line to be short-circuited based on the potential level change direction and the potential level change amount for each data signal line calculated by the comparison unit, and the data signal line short-circuit unit is The selected data signal lines are short-circuited. As a result, more effective charge recovery can be performed than when all data signal lines are short-circuited, and the effect of reducing power consumption can be improved.

  The display element driving circuit further includes a precharge unit that precharges the data signal line. In the comparison unit, it is determined that the direction of signal level change is the same in all the data signal lines. In this case, the selection unit may not select a data signal line to be short-circuited, and the precharge unit may precharge the data signal line.

  According to the above configuration, when the comparison unit determines that the direction of signal level change is the same in all the data signal lines, the power consumption is particularly reduced even if the data signal line is short-circuited. The effect is not obtained. Therefore, in such a case, the image signal in the display element can be improved by precharging the data signal line by the precharge unit. Further, when there is no signal that changes in the reverse direction, by applying a predetermined precharge voltage, the amount of charge necessary for the main charge can be reduced, and the power consumption can be reduced.

  The display element driving circuit has a configuration in which a precharge period of the data signal line by the precharge unit is variable according to a gradation difference between the video signal in the latest scanning line and the video signal in the previous scanning line. can do.

  According to the above configuration, the precharge time can be determined more accurately than the configuration in which the period for precharging the data signal line is fixed. If the precharge time can be accurately determined, the potential after precharge is determined from the potential before precharge and the precharge time, so that a desired potential after precharge can be obtained. You can charge.

  As described above, the display element driving circuit according to the present invention includes a plurality of scanning signal lines and a plurality of data signal lines provided so as to intersect with each other, and a thin film transistor at the intersection of the scanning signal line and the data signal line. A display element driving circuit for driving a display element having a pixel connected via a pixel, and comparing a video signal in the latest scanning line with a video signal in the previous scanning line, and a potential for each data signal line Based on the comparison unit for calculating the level change direction and the potential level change amount, and the potential level change direction and the potential level change amount for each data signal line calculated by the comparison unit, the data signal line to be short-circuited is determined. It is the structure which has the selection part to select, and the data signal line short circuit part which short-circuits the data signal lines selected by the said selection part.

  Therefore, from the comparison result between the video signal in the latest scanning line and the video signal in the previous scanning line, the potential level change direction and the potential level change amount are calculated for each data signal line, and based on this calculation result, The data signal line to be short-circuited can be optimally selected. Then, by short-circuiting the selected data signal lines, it is possible to perform more effective charge recovery than when all the data signal lines are short-circuited, and to improve the power consumption reduction effect. There is an effect.

  An embodiment of the present invention will be described with reference to the drawings.

[Configuration of liquid crystal display device]
FIG. 2 is a schematic configuration diagram illustrating a display device according to an embodiment of the present invention. In the present embodiment, a liquid crystal display device is exemplified as the display device.

  This liquid crystal display device is an active matrix type liquid crystal display device, and includes a display unit 1 having pixels PIX arranged in a matrix, a source driver (scanning signal line driver) 2 and a gate driver (driving each pixel PIX). (Scanning signal line driver) 3, a control circuit 4, a power supply circuit 5, and a plurality of data signal lines SL (SL1 to SLn) and scanning signal lines GL (GL1 to GLm) orthogonal to each other. When the control circuit 4 generates a video signal VIDEO indicating the display state of each pixel PIX, an image can be displayed on the display unit 1 based on the video signal VIDEO.

  The display unit 1 is composed of a liquid crystal panel, and a plurality of data signal lines SL and scanning signal lines GL are arranged so as to intersect with each other, and the data signal lines SL and scanning signal lines GL. This is a normal TFT liquid crystal panel in which a pixel PIX is connected to an intersection with... Via a TFT (Thin film transistor; not shown).

  The source driver 2 supplies a video signal (data signal) VIDEO to the pixel PIX via the data signal lines SL and the TFT. Further, the gate driver 3 supplies a scanning signal to the gate of the TFT via the scanning signal line GL. The source driver 2 and the gate driver 3 can be used by cascading a plurality of drivers when driving more data signal lines SL... Or scanning signal lines GL.

  The control circuit 4 outputs GSP (gate start pulse signal) and GCK (gate clock signal) to the gate driver 3, and supplies SSP (source start pulse signal), SCK (source clock signal), and video signal VIDEO to the source driver 2. Output to. The power supply circuit 5 inputs a source driver power supply and a gate driver power supply to the source driver 2 and the gate driver 3, respectively, and inputs a control circuit power supply to the control circuit 4.

[Configuration of drive circuit of liquid crystal display device]
FIG. 1 is a block diagram showing an internal configuration of a source driver 2 and a control circuit 4 as a drive circuit (display element drive circuit) of the liquid crystal display device.

  The source driver 2 includes a D / A converter (DAC) 21 and a sample hold circuit 22. The control circuit 4 includes an input I / F (interface) 41, a control logic 42, and an EEPROM 43. The D / A converter 21 includes a short circuit 211, and the control logic 42 includes a line memory 421.

  The input I / F unit 9 serves as an interface with the previous configuration of the control circuit 4, and when a video signal is input to the control logic 42 via the input I / F 41, the content of the input I / F unit 9 becomes a line. Temporarily stored in the memory 421. That is, the line memory 421 stores the previous data (data before one line).

  The control logic 42 transmits the clock signal CK for the sample hold circuit 22 and other control signals to the source driver 2 and outputs the video signal as a digital signal to the DAC 21. A program for operating the control logic 42 is stored in the EPROM 43 connected to the control logic 21.

  The D / A converter 21 in the source driver 2 converts the digital video signal input from the control circuit 4 into an analog video signal. The short circuit 211 provided in the D / A converter 21 has a function of setting the output of the source driver 2 to a high impedance state and short-circuiting the outputs of the source driver 2. The detailed configuration and operation of the short circuit 211 will be described later.

  The sample hold circuit 22 has a plurality of switches (not shown) and a plurality of capacitors (not shown), one of which is connected to the ground (the number of data signal lines SL...). The capacitor is charged, and the potential at the time of switching from holding to sampling is output to the data signal lines SL.

  Next, the operation of the liquid crystal display device according to this embodiment will be described. In the liquid crystal display device according to the present embodiment, before charging the liquid crystal capacitor (main charging or precharging), the source bus line is selectively short-circuited (charge sharing) for a certain period to reduce power consumption. It is intended. That is, in the present invention, the power consumption reduction effect due to charge sharing is improved by optimally selecting the source bus line to be short-circuited instead of short-circuiting all the source bus lines.

  Here, an algorithm for selecting a source bus line to be short-circuited will be described with reference to FIGS. The line selection by the algorithm is executed by the control logic 21, and FIG. 3 shows the configuration of the control logic 21 for performing the line selection.

  As described above, the video signal input to the control logic 42 via the input I / F 41 is temporarily stored in the line memory 421. Further, the line memory 421 is a line memory for two scanning lines (that is, a line memory for two scanning lines (that is, a gradation level signal) and a newly inputted signal of the latest scanning line so as to be compared. It has a line memory n-1 and a line memory n). The video signal input to the control logic 42 is sent to the D / A converter 21 via the data latch unit 424. The data latch unit 424 is connected to the video signal sent to the D / A converter 21 and described later. This is means for matching the transmission timing with the short selection line information.

  The comparison unit 422 compares the signal before the one scanning line stored in the line memory n−1 and the signal before the latest scanning line stored in the line memory n for each source bus line, and compares the comparison result. It transmits to the rearrangement calculation part 423. Here, the comparison result transmitted from the comparison unit 422 is the potential level change direction and the potential level change amount.

  As shown in FIG. 4, the rearrangement calculation unit 423, based on the data comparison result for each source bus line, shows a source bus line whose potential level changes in the + direction and a source whose potential level changes in the-direction. They are divided into bus lines, and further rearranged in descending order of potential level change amount in each change direction. In FIG. 4, the total number of source bus lines is 12 (lines 1 to 12) for the sake of simplicity.

  In addition, since the liquid crystal display device normally uses AC driving such as dot inversion driving, the output polarity to the source bus line may be inverted. In this case, when the output polarity to the source bus line changes from -polarity to + polarity, the potential level changes in the + direction, and when it changes from + polarity to -polarity, the potential level changes in the -direction. is there. For example, when the output in a certain source bus line changes from −V32 to + V32, the change in potential level is in the + direction, and the level change amount is 64 (represented as +64 in FIG. 4).

  Even if the output polarity of the source bus line does not change, the potential level change direction and the potential level change amount can be obtained. For example, when the output of a certain source bus line changes from + V32 to + V20, the potential level changes in the-direction, and the level change amount is 12 (represented as +12 in FIG. 4).

As a result of the data comparison for each source bus line, the rearrangement calculation unit 423 assumes that the rearrangement as shown in FIG. Thereafter, the source bus line to be short-circuited is selected by the following procedures (1) to (4) (see FIG. 5).
(1) Select the line with the largest level change as the first short selection line. In the example of FIG. 5, +40 line 3 is selected as the first selection line.
(2) Obtain the total potential change level of the short selection line at that time. For example, when the +3 line 3 is selected in the above (1), the total potential change level is +40.
(3) Select the line with the largest level change amount as the next short selection line from the lines whose potential change direction is opposite to the polarity of the total potential change level obtained in (2) above. . In the example of FIG. 5, the −37 line 7 is selected as the second selection line.
(4) The above processes (2) to (3) are repeated until there are no more selectable lines. In the example of FIG. 5, the selection lines are selected in the order of line 12, line 5, line 2, line 1, line 4, line 10, line 8, and line 11. The total potential change level at the time when the line 11 is selected is -7. At this time, no line with the potential change direction in the + direction remains, so that no further line selection is possible.

  Thus, when there are no selectable lines, the lines that have not been selected as the short selection line so far are not short-circuited. That is, in the example of FIG. 4, the lines 6 and 9 are not short-circuited.

  In the present invention, the source bus line selection algorithm is not limited to the algorithm described with reference to FIGS. 4 and 5 described above, and other algorithms may be used for selection. In the present invention, the method of selecting a source bus line to be short-circuited includes: (a) selecting more lines as the source bus line to be short-circuited; and (b) summing the potential change levels of the short-circuited selection lines. By targeting two points of approaching 0, the amount of charge recovered by shorting the source bus line can be increased, and the effect of reducing power consumption is increased.

  Next, an operation after the source bus line to be shorted is selected will be described. First, when the source bus line to be short-circuited is selected in the rearrangement calculation unit 423 of the control logic 42, information indicating the short selection line is notified to the short circuit 211 of the D / A converter 21.

  In the short circuit 211 notified of the short selection line information, the output from the D / A converter 21 to the sample hold circuit 22 is temporarily cut off, and the circuits after the sample hold circuit 22 are set in a high impedance state, and for a certain period. Shorten the source bus line to be used. A circuit configuration of the short circuit 211 for this purpose is shown in FIG.

  As shown in FIG. 6, the short circuit 211 includes a first switch group 211A, a second switch group 211B, and a short wiring 211C.

  Each switch of the first switch group 211A is provided for each source bus line immediately after the rear stage of the D / A converter unit. By opening the first switch group 211A at the same time, the D / A converter 21 and the sample hold circuit are provided. The output to 22 is disconnected.

  Each switch of the second switch group 211B is provided for each source bus line in the subsequent stage of the first switch, and each source bus line is connected to the short-circuit wiring 211C via the second switch. Each switch of the second switch group 211B is individually turned on / off based on the short selection line information notified from the control logic 42, and the source bus line connected to the second switch that is turned on is Shorted via the shorting wiring 211C.

  As described above, in the liquid crystal display device according to the present embodiment, the control logic 42 appropriately selects the source bus line to be short-circuited, and only the selected source bus line is short-circuited by the short circuit 211. Accordingly, in the hold type display device, charge sharing by short-circuiting the source bus line can be optimally performed before charging the pixel capacitance, and a higher power consumption reduction effect can be obtained.

  Further, in a liquid crystal display device, AC driving is performed to prevent liquid crystal burn-in and the like, and such AC driving includes driving methods such as dot inversion driving, line inversion driving, and frame inversion driving. Here, the line inversion drive has the same potential level change direction in all the source bus lines, and therefore, even if the source bus line is short-circuited, there is no particular effect, and the present invention is not applied. That is, the present invention is applied to dot inversion driving or frame inversion driving. In particular, in the dot inversion drive, the same number of source bus lines whose potential level change directions are opposite to each other. Therefore, the charge recovery effect due to the short of the source bus lines is great, and the present invention is preferably applied.

  In the liquid crystal display device described above, the line to be short-circuited is selected in order to balance the +/- direction of the potential level change direction in each source bus line. However, when the potential level change direction in all the source bus lines is a change only in the + direction or the-direction, even if the source bus lines are short-circuited, there is no charge recovery effect. Therefore, the display device of the present invention is further combined with a precharge circuit, and when the potential level change direction in all the source bus lines is one direction, the charge share due to the short of the source bus line as described above. It is possible to precharge the source bus line without performing the above.

  One configuration example of a liquid crystal display device capable of precharging the source bus line will be described below with reference to FIG. The source driver 6 shown in FIG. 7 includes a D / A converter (DAC) 21, a precharge circuit 61, and a sample hold circuit 22, and can be used in place of the source driver 2 in FIG. The D / A converter 21 and the sample hold circuit 22 have the same configuration as the D / A converter 21 and the sample hold circuit 22 in FIG.

  The precharge circuit 61 applies to the sample and hold circuit 22 before supplying the video signal VIDEO to the sample and hold circuit 22 so that the capacitive load (sample and hold circuit 22) is stably charged by a desired amount of charge. Pre-charge (pre-charge). Here, the capacitor load to be precharged is the sample-and-hold circuit 22, but it may be precharged with the data signal lines SL as capacitive loads.

  Here, the precharge circuit 61 is built in the source driver 6. However, the present invention is not limited to this configuration, and a precharge circuit is provided on the side opposite to the side where the source driver 6 is provided in the display unit 1. May be. That is, the display unit 1 may be sandwiched between the precharge circuit 61 and the source driver 6. With this configuration, it is possible to drive more data signal lines SL... Or scanning signal lines GL. That is, even if the number of data signal lines SL and scanning signal lines GL... Increases, sufficient space for the precharge circuit 61 and the source driver 6 can be secured.

  FIG. 8 is a schematic circuit diagram showing specific circuit configurations of the D / A converter 21 and the precharge circuit 61.

  As shown in the figure, the D / A converter 21 includes an operational amplifier (OpAmp) 21A and an analog switch 21B disposed at the subsequent stage of the operational amplifier 21A. Note that the switch is not limited to the analog switch 21B, and other switches may be substituted.

  The operational amplifier 21A has a role of supplying a voltage for performing precharging and main charging. The analog switch 21B has a function of setting the output of the D / A converter 21 to high impedance (Hi-z state) by turning off the analog switch 21B.

  Furthermore, one end of the operational amplifier 21A is connected to the ground GND (ground potential Vss), while the other end is connected to the power supply potential Vdd of 5V. In addition, the bias current can be cut by stopping the operation of the operational amplifier 21A during precharge (turning off the power supply of the operational amplifier 21A). Thereby, the power consumption of the drive circuit can be reduced.

  The analog switch 21B is not necessarily an essential component, and may not be provided when the output of the D / A converter 21 is not required to be high impedance.

  The precharge circuit 61 includes a + side precharge switch (analog switch) 61A and a − side precharge switch (analog switch) 61B. The + side precharge switch 61A and the − side precharge switch 61B are connected to each other via a node 61C provided on the path of the output signal from the operational amplifier 21A. More specifically, one end of the + precharge switch 61A is connected to the power supply potential Vdd, and the other end is connected to the node 61C. The negative precharge switch 61B has one end connected to the ground GND and the other end connected to the node 61C.

  The switching operation of the precharge circuit 61 is performed when the gradation A <gradation B is obtained by comparing the previous data signal level (gradation A) with the current data signal level (gradation B). The + precharge switch 61A connected to the power supply potential Vdd side is turned on for a certain period of time. On the other hand, when the gradation A> the gradation B, the negative precharge switch 61B connected to the ground potential Vss is turned on for a certain period of time. Note that whether the + precharge switch 61A or the − precharge switch 61B is made conductive is controlled by a signal indicating the polarity sent from the control logic 42.

  Further, in a configuration in which a precharge circuit is combined in a display device, a signal (grayscale level signal) one scan line before is compared with a newly input signal of the latest scan line, and a difference (level) of the signal level is compared. It is preferable to make the period for performing the precharge variable in accordance with the difference. For this purpose, a lookup table stored in association with a difference in signal level and a precharge period (number of clocks) is stored in a nonvolatile memory (for example, EEPROM 43) in the source driver, and the signal is obtained by referring to the table. The precharge period can be set according to the level difference.

  In this way, when the precharge period is set with reference to the lookup table, for example, the lookup table shown in FIG. 9 can be used.

  In the lookup table shown in FIG. 9, the previous data D1, the current data (video signal VIDEO; potential; gradation) D2, and the number of clocks (precharge time Tp) are associated with each other. That is, arbitrary two lines of data before and after are associated with a desired precharge time Tp for these data.

  More specifically, the table is such that the number of clocks is determined if the previous data D1 and the current data D2 are determined. In the figure, for example, if “previous data: 63 gradations, current data: 1 gradation”, the number of clocks is “5 clocks”. The lookup table 15 is a 64 × 64 gradation table, but it may be an 8 × 8 gradation, 32 × 32 gradation, 128 × 128 gradation, or 256 × 256 gradation table. . Further, the lookup table shown in FIG. 9 is merely an example.

  The look-up table may be stored in the EEPROM 43 in the control circuit 4, for example. When precharge is performed, the control logic 42 accesses the lookup table to read out the clock number, and the + precharge switch 61A or the negative precharge switch 61B is connected only during the period corresponding to the read clock number. The control signal may be output so that the

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims. That is, embodiments obtained by combining technical means appropriately changed within the scope of the claims are also included in the technical scope of the present invention.

  It can be suitably used for a source driver in a display device such as an image display device.

1, showing an embodiment of the present invention, is a block diagram illustrating a configuration of main parts of a source driver and a control circuit. FIG. 1, showing an embodiment of the present invention, is a schematic configuration diagram showing a liquid crystal display device (display device). FIG. 1, showing an embodiment of the present invention, is a block diagram illustrating a main configuration of a control logic. FIG. FIG. 10 is a diagram for explaining rearrangement of source bus lines based on a change direction and a change amount of a potential level for each source bus line when selecting a source bus line to be short-circuited. It is a figure explaining the selection order of the source bus line which should be short-circuited. 1, showing an embodiment of the present invention, is a diagram illustrating a configuration of a main part of a short circuit. FIG. 1, showing an embodiment of the present invention, is a block diagram illustrating a main configuration of a source driver including a precharge circuit. FIG. 1, showing an embodiment of the present invention, is a schematic circuit diagram showing specific circuit configurations of a D / A converter and a precharge circuit. FIG. 1, showing an embodiment of the present invention, is an explanatory diagram showing a schematic configuration of a lookup table. FIG.

Explanation of symbols

1 Display (display element, liquid crystal panel)
2, 6 Source driver (display element drive circuit)
3 Gate driver 4 Control circuit (Display element drive circuit)
21 D / A converter 61 Precharge circuit (precharge unit)
421 line memory (comparator)
422 Comparison part (comparison part)
423 Rearrangement calculation part (selection part)
211 Short circuit (Short section of data signal line)
GL1 to GLm scanning signal lines SL1 to SLn data signal lines PIX pixels

Claims (5)

A display element having a plurality of scanning signal lines and a plurality of data signal lines provided so as to intersect with each other, and a pixel connected to an intersection of the scanning signal line and the data signal line via a thin film transistor is driven. A display element driving circuit,
A comparison unit that compares the video signal in the latest scanning line with the video signal in the previous scanning line and calculates the change direction of the potential level and the potential level change amount for each data signal line;
A selection unit that selects a data signal line to be short-circuited based on the change direction of the potential level for each data signal line calculated by the comparison unit and the potential level change amount;
A display element driving circuit comprising: a data signal line short-circuit unit that short-circuits the data signal lines selected by the selection unit. Furthermore, a precharge unit for precharging the data signal line is provided,
When the comparison unit determines that the direction of the signal level change is the same in all the data signal lines, the selection unit does not select the data signal line to be short-circuited, and the precharge unit 2. The display element driving circuit according to claim 1, wherein the data signal line is precharged.   The precharge period of the data signal line by the precharge unit is variable according to a gradation difference between the video signal in the latest scanning line and the video signal in the previous scanning line. Display element drive circuit.   A liquid crystal display device comprising: the display element driving circuit according to claim 1; and a liquid crystal panel as the display element. A display element having a plurality of scanning signal lines and a plurality of data signal lines provided so as to intersect with each other, and a pixel connected to an intersection of the scanning signal line and the data signal line via a thin film transistor is driven. A display element driving method comprising:
Compare the signal of the latest scan line with the signal of the previous scan line, and select the data signal line to be short-circuited based on the comparison result,
A display element driving method comprising: charging the pixels of the display element after short-circuiting the selected data signal lines for a certain period.

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