JP2007094966A - Ic card - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To complicate specification of timing of encryption processing, or sensitive processing for a portion handling important data or the like in processing of an IC card. <P>SOLUTION: A watchdog timer circuit 403 is provided for carrying out CPU interruption after passage of a predetermined time, and a random number generating means 402 is provided for generating a random number. By a random number generated by the random number generating means, a timer value of the watchdog timer circuit is set, operation of the watchdog timer circuit is started, and dummy processing is carried out for a predetermined time at the stage of carrying out interruption by the watchdog timer circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to tamper resistance of an IC card.

  IC (Integrated Circuit) cards are used not only for settlement of credit cards, commuter passes, and other commercial transactions, but also in various fields as ID cards for employee cards, membership cards, insurance cards, etc. ing. This is because the IC has a CPU, ROM, RAM, EEPROM, etc. so that it can perform various functions compared to conventional magnetic cards, and it is difficult to forge. It is. Details of the IC card are defined in Non-Patent Document 1.

Since the IC card stores important information such as personal information, the data is encrypted using encryption or the card user is authenticated. Therefore, sufficient security is maintained in normal use. However, since attacks against IC cards are very powerful, it is very difficult to identify encryption processing units in the power consumption waveform that is a precondition for attacks, as well as establishing countermeasures that can withstand the attacks. It becomes important to.
ISO / IEC 7816-1part1, 2

  An object of the present invention is to make it difficult to specify the timing of sensitive processing such as encryption processing or a portion that handles important data in processing of an IC card.

  The invention according to an aspect of the present invention includes a watchdog timer circuit that performs a CPU interrupt after a predetermined time elapses, and a random number generation unit that generates a random number. The random number generated by the random number generation unit generates the watchdog timer. A timer value of the circuit is set, the operation of the watchdog timer circuit is started, and dummy processing is performed for a predetermined time when an interrupt is generated by the watchdog timer circuit.

  ADVANTAGE OF THE INVENTION According to this invention, the attack to a sensitive process can be made difficult and the safety | security of an IC card can be improved. Furthermore, it becomes difficult to predict sensitive processing timing during IC card processing, and various attacks that require timing information can be avoided.

  Embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing a schematic configuration of an IC card including a cryptographic operation circuit according to the present invention. The details of the IC card are defined in Non-Patent Document 1, as described above. As shown in FIG. 1, an IC chip 102 is mounted in a card 101. FIG. 2 is a diagram showing an internal configuration of a general IC chip. In the embodiment of the present invention, it is assumed that a cryptographic operation circuit is provided in order to make an attack from the outside difficult. However, the present invention can also be applied to an IC card that processes a cipher with a CPU. Of course there is.

  As shown in FIG. 2, an IC chip 102 according to the present invention includes a CPU 201, a RAM 202, a ROM 203, an EEPROM 204, an I / O port 205, a coprocessor 206, a cryptographic processing circuit 207, and a watchdog timer 208. It has.

  In the above configuration, the CPU 201 executes an IC card program stored in the ROM 203, and the RAM 202 and the EEPROM 204 store data necessary for processing. The I / O port 205 receives a command from an external device (for example, a reader / writer), and outputs the processing result of the CPU 201 as a response. A data bus 209 is a bus for transferring data between devices.

FIG. 4 is a diagram showing an outline of an internal configuration example of the cryptographic processing circuit 207. The cryptographic processing circuit 207 includes a cryptographic processing unit 401, a random number generation unit 402, a watch dog timer 403, and an I / F unit 404. In this embodiment, an embodiment is shown in which the process shifts to a dummy process by an interrupt process by the watchdog timer 403 during the cryptographic process in the cryptographic process circuit 207. However, the present invention is not limited to this. For example, a highly confidential process, for example, The present invention can also be applied to a case where the process shifts to a dummy process by an interrupt process by the watchdog timer 403 in a personal verification process or the like.
The encryption processing unit 401 encrypts the input received from the I / F unit using DES. The random number generation unit 402 generates a random number used for DES processing. The watchdog timer 403 performs interrupt processing, which will be described later in detail, on the cryptographic processing unit 401 according to the random number from the random number generation unit 402. The I / F unit 404 inputs and outputs data with the CPU 201 and the like.

With reference to FIG. 5, the operation of the IC card according to an embodiment of the present invention configured as described above will be described. FIG. 5 is a flowchart showing the operation of the IC card according to the embodiment of the present invention.
First, when a random number is generated and generated by the random number generation unit 402 in accordance with an instruction from the CPU (step 51), the random number is set in the watchdog timer 403 (step 52). Here, the value of the random number set in the watchdog timer 403 is set as the occurrence time of the timer interrupt, and the operation of the watchdog timer 403 is started. An interrupt is generated at 401 (step 53). A preset dummy process is performed in response to an interrupt by the watchdog timer 403 (step 54), and the process ends after a predetermined time has elapsed.
With the above processing, the watchdog timer 403 performs dummy interrupt processing according to the value of the random number in encryption processing or the like, making it difficult to predict and analyze the timing of encryption processing.

In this case, the watchdog timer 403 may be capable of setting a plurality of discrete timer values. In this case, a predetermined timer value may be selected according to a random value. Further, the timer value of the watchdog timer 403 may be arbitrarily set. Further, in those cases, the timer value may be limited to a predetermined time or less.
Furthermore, the dummy process may be repeated not only once but also one dummy process (or command) a plurality of times. In this case, the dummy process is continuously performed after the dummy process is completed until the process result is transmitted. It is preferable. Note that the dummy process may be executed not only by one instruction but also by a dummy process including a plurality of instructions.

The operation of the IC card according to another embodiment of the present invention will be described with reference to FIG. FIG. 6 is a flowchart showing the operation of the IC card according to another embodiment of the present invention. In the present embodiment, a dummy process interruption method by the watchdog timer 403 when a plurality of dummy processes are prepared will be described.
First, when a random number is generated and generated by the random number generation unit 402 according to an instruction from the CPU or the like (step 61), one dummy process executed by the interrupt process is selected by the watchdog timer 403 based on the random number. (Step S62). In this case, the watchdog timer 403 stores the start address of each dummy process (for example, the first dummy process starts at the address 8000 and the second dummy process starts at the 8100 address). In this case, the control may be transferred to each start address corresponding to the random value. When the start time of the interrupt process by the watchdog timer 403 is reached, the selected dummy process is executed (step S63), and the process is terminated after a predetermined time has elapsed.
Also in the processing of this embodiment, the watchdog timer 403 performs dummy interrupt processing according to the random number value in cryptographic processing or the like, as in the previous embodiment, so that the timing of cryptographic processing can be predicted and analyzed. It becomes difficult.

  Each of the above embodiments has been described separately, but can be applied in appropriate combination. For example, in the embodiment shown in FIG. 5, a plurality of dummy processes may be prepared, and the dummy processes may be shifted and executed one by one for each interrupt. It may be used for both setting and selection of dummy processing.

  The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention at the stage of implementation. For example, in each of the above embodiments, the execution time of the dummy process is fixed according to the contents of the dummy process. However, the dummy process time is set by a random number, and the time elapses. Alternatively, the dummy process may be performed. In the above-described embodiment, an example in which only the encryption processing unit is interrupted as the interrupt processing of the watchdog timer has been described. However, the CPU 208 may be connected to the bus 208 in order to execute the CPU interrupt. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements.

  In addition, for example, even if some structural requirements are deleted from all the structural requirements shown in each embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the effect of the invention Can be obtained as an invention.

The figure which shows schematic structure of the IC card provided with the cryptographic operation circuit which concerns on this invention. The figure which shows the general internal structure of an IC chip. The figure which shows the outline | summary of the internal structure of a cryptographic processing circuit. The flowchart which shows operation | movement of the IC card which concerns on one Embodiment of this invention. The flowchart which shows operation | movement of the IC card based on other embodiment of this invention.

Explanation of symbols

101 ... Card 102 ... IC chip 201 ... CPU
202 ... RAM
203 ... ROM
204… EEPROM
205 ... I / O port 206 ... Coprocessor 207 ... Cryptographic processing circuit 208 ... Watchdog timer 209 ... Data bus 401 ... Cryptographic processing unit 402 ... Random number generating unit 403 ... Watchdog timer 404 ... I / F unit

Claims (7)

A watchdog timer circuit for performing a CPU interrupt after a predetermined time;
Random number generating means for generating random numbers,
The timer value of the watchdog timer circuit is set by the random number generated by the random number generation means, the operation of the watchdog timer circuit is started, and a dummy signal is output for a predetermined time when an interrupt is generated by the watchdog timer circuit. An IC card that performs processing. 2. The IC card according to claim 1, wherein the watchdog timer circuit is capable of setting a plurality of discrete timer values, and the timer value is set according to the random number. card. 2. The IC card according to claim 1, wherein the watchdog timer circuit can arbitrarily set a timer set value. The IC card according to any one of claims 1 to 3, wherein dummy processing by interruption of the watchdog timer circuit is repeated between the end of dummy processing and processing result data transmission. IC card. 5. The IC card according to claim 1, wherein the dummy process is a process including a plurality of instructions, and performs a process related to the plurality of instructions. 6. The IC card according to any one of claims 1 to 5, wherein the dummy process includes a plurality of dummy processes, and at least one dummy process executed by the random number is selected. IC card to do. 7. The IC card according to claim 1, wherein the watchdog timer circuit sets the execution time of the dummy process by the random number so that the dummy process time of each time is different. IC card.

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