JP2007094318A - Driver ic for liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driver IC for liquid crystal display device applicable to liquid crystal display devices with various resolution. <P>SOLUTION: The driver IC has an SEG/COM combination terminal group 12 as well as an SEG exclusive terminal group 11 and a COM exclusive terminal group 13. Each SEG/COM combination terminal belonging to the SEG/COM combination terminal group 12 is grouped. Then, groups of the respective SEG/COM combination terminals arranged on both sides of the SEG exclusive terminal group 11, respectively are paired and an operation instruction signals are transmitted from a bit area 22 in a register 21 to the pairs of the respective groups. The operation instruction signals are input in switches according to the pair of the respective groups and kinds of output voltage are restricted by the switches. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a driver IC for a liquid crystal display device, and more particularly to a one-chip driver IC for a liquid crystal display device used in a liquid crystal display device in which liquid crystal is sandwiched between a plurality of common electrodes and a plurality of segment electrodes.

  A conventional one-chip driver IC for a liquid crystal display device is described in Patent Document 1, for example. In a conventional driver IC for a liquid crystal display device of one chip, as described in Patent Document 1, a segment driver is disposed at the center of one side of the chip, and a common driver is disposed outside the segment driver.

  As a method for driving a liquid crystal display device, IAPT (Improved Alto-Pleshko Technique) is known. In IAPT, six types of voltage levels are used and periodically switched between positive polarity driving and negative polarity driving. In addition, the positive polarity driving is driving so that the potential of the selected common electrode is higher than the potential of the segment electrode. The negative polarity driving is driving so that the potential of the selected common electrode is lower than the potential of the segment electrode.

Hereinafter, describing the six voltage levels used in IAPT as _V 0 ~V _5. The description will be made assuming that V ₅ <V ₄ <V ₃ <V ₂ <V ₁ <V ₀ . FIG. 20A is an explanatory diagram illustrating an example of a driving waveform at the time of positive polarity driving in IAPT. FIG. 20B is an explanatory diagram showing an example of a driving waveform at the time of negative polarity driving in IAPT. In FIG. 20, the driving waveform indicated by a solid line indicates a change in voltage applied to one common electrode, and the driving waveform indicated by a broken line indicates a change in voltage applied to one segment electrode. Yes.

As shown in FIG. 20A, in the case of positive polarity driving, the voltage V ₀ is applied to the common electrode during the selection period. Further, the common electrode is not selected, the voltage V ₄ is applied. Further, during the selection period of a common electrode, the segment electrodes of the column in which the pixel to be there on (light transmission state) the voltage V ₅ is applied, there is a pixel should be turned off (light scattering state) the voltage V ₃ is applied to the segment electrode of the column.

Further, as shown in FIG. 20 (b), when the negative polarity driving, the common electrode during the selection period, the voltage V ₅ is applied. Further, the common electrode is not selected, the voltages V ₁ is applied. In addition, during the selection period of a certain common electrode, the voltage V ₀ is applied to the segment electrode of the column where the pixel to be turned on (light transmission state) exists, and there is a pixel to be turned off (light scattering state). the voltage V ₂ is applied to the segment electrode of the column.

That is, the voltage V ₀ is a voltage that is applied to the common electrode selected during the positive polarity driving, and is applied to the segment electrode in the column where the pixel to be turned on exists during the negative polarity driving. Voltages V ₁ is the voltage applied to the common electrode that is not selected during a negative polarity driving. Voltage V ₂ is the voltage applied to the segment electrodes of the column in which the pixel to be turned off when a negative polarity driving is present. Voltage V ₃ is the voltage pixels to be turned off during the positive drive is applied to the segment electrodes of columns that exist. Voltage V ₄ is the voltage applied to the common electrode that is not selected during positive drive. Voltage V ₅ is applied to the common electrode selected at a negative polarity driving, also the voltage applied to the segment electrodes of the column in which the pixel to be turned on during the positive drive is present. The description of the voltage level used in such IAPT is described in Patent Document 2, for example. However, in Patent Document _2, it is described as a _{V 0 <V 1 <V 2} <V 3 <V 4 <V 5.

Japanese Patent Laying-Open No. 2003-20392 (paragraph 0009, FIG. 1) JP 200454220 A (paragraphs 0066 and 0067)

  In the case of a one-chip driver IC for a liquid crystal display device as described in Patent Document 1, there is a problem that the liquid crystal display devices that can use the driver IC are limited. For example, in the driver IC for a liquid crystal display device described in Patent Document 1, the number of segment driver terminals (connecting terminals to the segment electrodes) arranged at the center of one side of the chip is M and arranged outside thereof. It is assumed that the number of the common electrode driver terminals (connection terminals with the common electrode) is N. Then, the driver IC for the liquid crystal display device can be used only for a liquid crystal display device in which the number of segment electrodes is M or less and the number of common electrodes is N or less. That is, the liquid crystal display device having more than M segment electrodes or more than N common electrodes cannot be used because there are not enough segment driver terminals or common electrode driver terminals.

  For example, in the driver IC for a liquid crystal display device described in Patent Document 1, it is assumed that the number of segment electrode terminals is 128, and 64 common electrode terminals are arranged on the outside thereof. Then, the driver IC is applicable to a liquid crystal display device having a resolution of 128 × 128 (128 segment electrodes and 128 common electrodes) shown in FIG. However, it cannot be applied to a liquid crystal display device having a resolution of 160 × 96 (160 segment electrodes and 96 common electrodes) shown in FIG. This is because the number of segment electrode terminals of the driver IC is insufficient with respect to the number of segment electrodes 160.

  As described above, the conventional driver ICs for liquid crystal display devices are limited in usable liquid crystal display devices. Therefore, if the resolution of the liquid crystal display device is different, a new driver IC for the liquid crystal display device has to be developed so that it can be applied to the liquid crystal display device. For example, since a liquid crystal display device used as a sub-display of a mobile phone is adopted with emphasis on the design of the mobile phone, the resolution is often different for each type of mobile phone. Therefore, a new driver IC for a liquid crystal display device has to be developed for each sub-display of various mobile phones. In addition, IC evaluation and software development must be performed for each driver IC for liquid crystal display devices, and the development cost of driver ICs for liquid crystal display devices has increased.

  In addition, since the liquid crystal display devices that can be used are limited, it is difficult to increase the number of driver ICs for liquid crystal display devices even if a driver IC for liquid crystal display devices is developed in accordance with the required resolution. There was also a problem.

  Accordingly, an object of the present invention is to provide a driver IC for a liquid crystal display device that can be applied to liquid crystal display devices having various resolutions.

  Aspect 1 of the present invention is a driver IC for a liquid crystal display device that drives a liquid crystal display device that holds liquid crystal between a plurality of scanning electrodes and a plurality of signal electrodes, and a plurality of signals that are connected only to the signal electrodes. A liquid crystal display driver comprising: an electrode dedicated terminal; a plurality of scan electrode dedicated terminals connected only to the scan electrode; and a plurality of shared terminals connectable to both the signal electrode and the scan electrode Provide IC.

  Aspect 2 of the present invention is selected in aspect 1 by selecting the voltage used when the shared terminal is connected to the signal electrode or the voltage used when the shared terminal is connected to the scan electrode. Provided is a driver IC for a liquid crystal display device including a voltage selection switch that allows a voltage to be applied to an electrode connected to a shared terminal.

  Aspect 3 of the present invention is the operation instruction signal according to aspect 2, wherein a voltage selection switch is provided for each set of a predetermined number of dual-purpose terminals, and each voltage selection switch indicates that the corresponding dual-purpose terminal is connected to the signal electrode. When the dual-purpose terminal is connected to the signal electrode, the voltage output section used when the dual-purpose terminal is connected to the signal electrode and the corresponding dual-purpose terminal can be connected, and the corresponding dual-purpose terminal is connected to the scan electrode. When an operation instruction signal indicating that the common terminal is connected to the scan electrode, a driver for a liquid crystal display device that enables connection between the voltage output unit used when the dual terminal is connected to the scan electrode and the corresponding dual terminal Provide IC.

  Aspect 4 of the present invention is the driver for a liquid crystal display device according to aspect 3, provided with a register for previously storing an operation instruction signal for each set of a predetermined number of dual-purpose terminals, wherein each voltage selection switch inputs the operation instruction signal from the register. Provide IC.

  Aspect 5 of the present invention includes an external setting terminal for inputting an operation instruction signal from the outside for each set of a plurality of dual-purpose terminals in aspect 3, and each voltage selection switch operates from the outside via the external setting terminal. A driver IC for a liquid crystal display device for inputting an instruction signal is provided.

  According to the present invention, since the configuration includes a plurality of dual-purpose terminals that can be connected to either the signal electrode or the scan electrode, it can be applied to liquid crystal display devices having various resolutions. As a result, it is not necessary to develop a driver IC for a liquid crystal display device for each liquid crystal display device having various resolutions, and the development cost of the driver IC for a liquid crystal display device can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a liquid crystal display device to which a driver IC for a liquid crystal display device of the present invention (hereinafter referred to as a driver IC) is applied will be described. The liquid crystal display device includes a plurality of common electrodes (scanning electrodes) on one of a pair of substrates, and a plurality of segment electrodes (signal electrodes) on the other substrate. The pair of substrates are arranged such that a plurality of common electrodes and a plurality of segment electrodes are orthogonal to each other. Then, STN (Super Twisted Nematic) liquid crystal is sandwiched between the plurality of common electrodes and the plurality of segment electrodes. The intersection between the common electrode and the segment electrode is a pixel. This liquid crystal display device is line-sequentially driven by a driver IC. The liquid crystal display device is driven by a driver IC and displays a binary image that does not include halftones or a grayscale image that includes halftones.

  Next, output terminals (terminals connected to the electrodes) of the driver IC of the present invention will be described. The output terminal is sometimes called a PAD. FIG. 1 is an explanatory view showing an arrangement example of output terminals of a driver IC for a liquid crystal display device of the present invention. The driver IC for a liquid crystal display device includes a segment electrode dedicated output terminal group 11, a segment electrode / common electrode combined output terminal group 12, and a common electrode dedicated output terminal group 13 on a rectangular chip 1. The segment electrode dedicated output terminal is a terminal connected only to the segment electrode, and is hereinafter referred to as a SEG dedicated terminal. The segment electrode / common electrode combined output terminal is a terminal that can be connected to either the segment electrode or the common electrode, and is hereinafter referred to as a SEG / COM combined terminal. The common electrode dedicated output terminal is a terminal connected only to the common electrode, and is hereinafter referred to as a COM dedicated terminal.

  As shown in FIG. 1, the SEG dedicated terminal group 11 is arranged at the center of one side of the chip 1. SEG / COM combined terminal groups 12 are arranged on both sides of the SEG dedicated terminal group 11 respectively. The number of SEG / COM shared terminals belonging to each SEG / COM shared terminal group 12 arranged on both sides of the SEG dedicated terminal group 11 is the same. A COM dedicated terminal group 13 is arranged next to each SEG / COM combined terminal group 12. The COM dedicated terminal group 13 is arranged on the opposite side of the SEG dedicated terminal group 11 with the SEG / COM combined terminal group 12 as a reference. That is, in the example shown in FIG. 1, the COM dedicated terminal group 13 is disposed outside one side of the chip 1 and is sandwiched between the COM dedicated terminal group 13 so that the SEG / COM combined terminal group 12 and the SEG dedicated terminal group 11 are disposed. Is placed. The number of COM dedicated terminals belonging to each COM dedicated terminal group 13 arranged outside one side of the chip 1 is the same.

  The SEG dedicated terminal group 11 and each SEG / COM combined terminal group 12 are arranged on one side (the same side) of the chip 1. However, the COM dedicated terminal group 13 may be arranged on a different side from the SEG dedicated terminal group 11 and each SEG / COM combined terminal group 12. FIG. 2 is an explanatory diagram showing an example in which the COM dedicated terminal group 13 is arranged on a different side from the SEG dedicated terminal group 11 and each SEG / COM combined terminal group 12. In the example shown in FIG. 2, the COM dedicated terminal group 13 is arranged on both sides adjacent to the side where the SEG dedicated terminal group 11 and each SEG / COM combined terminal group 12 are arranged.

  The reason why the SEG dedicated terminal group 11 and each SEG / COM combined terminal group 12 are arranged on one side of the chip 1 is that the SEG dedicated terminal group 11 and each SEG / COM combined terminal group 12 are arranged on different sides of the chip. This is because it is difficult to route the wiring from the SEG / COM combined terminal group 12 to the segment electrode. As a first aspect that makes it difficult to route the wiring to the segment electrode, the wiring from the SEG / COM shared terminal group 12 to the segment electrode is routed depending on the size of the liquid crystal panel (liquid crystal display device) and the driver IC. The aspect that it cannot do is mentioned. As a second mode in which it is difficult to route the wiring to the segment electrode, even if the wiring can be routed from the SEG / COM combined terminal group 12 to the segment electrode, as shown in FIG. The lengths of the lead wires from the lead wires to the segment electrodes and the lead wires from the SEG / COM combined terminal group 12 to the segment electrodes are different, and the resistance values of the lead wires cannot be made uniform, resulting in non-uniform display. The aspect that it will end up is mentioned. By arranging the SEG dedicated terminal group 11 and each SEG / COM combined terminal group 12 on one side of the chip 1, it is possible to eliminate the difficulty of wiring as described above.

  As shown in FIG. 1 and FIG. 2, an interface terminal 15 with an external MPU (microprocessor) is provided on the opposite side of the side where the SEG dedicated terminal group 11 and each SEG / COM combined terminal group 12 are arranged. Be placed.

  In the present embodiment, it is assumed that the number of SEG dedicated terminals belonging to the SEG dedicated terminal group 11 is a multiple of eight. The total number of SEG / COM shared terminals belonging to the SEG / COM shared terminal group 12 is a multiple of 16. The SEG / COM shared terminals that are multiples of 16 are divided in half and are arranged as SEG / COM shared terminal groups 12 on both sides of the SEG dedicated terminal group 11, respectively.

  Eight SEG / COM shared terminals belonging to each SEG / COM shared terminal group 12 on both sides of the SEG dedicated terminal group 11 are grouped. The SEG / COM combined terminal groups are arranged so as to be separated from each other by a predetermined distance. In addition, this predetermined space | interval is 100 micrometers, for example. FIG. 4 is an explanatory diagram showing an interval between groups of SEG / COM combined terminals. As shown in FIG. 4, the SEG / COM terminal groups are arranged with an interval of, for example, 100 μm or more.

  The SEG / COM combined terminal can be used as a terminal connected to the segment electrode or a terminal connected to the common electrode. Whether to use as a terminal connected to the segment electrode or as a terminal connected to the common electrode is set for each group. Therefore, some SEG / COM shared terminals belonging to a certain group are not connected to the segment electrode, and other SEG / COM shared terminals belonging to the group are not connected to the common electrode.

  The reason why the interval between the groups is more than the predetermined interval is to allow different voltages to be applied to the segment electrode and the common electrode during panel inspection. Since each SEG / COM shared terminal belonging to the same group is connected to either the segment electrode or the common electrode, a common voltage is applied to the electrode during panel inspection. Therefore, the interval between the SEG / COM shared terminals belonging to the same group may be narrower than the interval between the groups.

  Further, the SEG / COM combined terminal adjacent to the SEG dedicated terminal may be set as a terminal connected to the common electrode. Even in such a case, it is necessary to be able to apply different voltages to the segment electrode and the common electrode during panel inspection. Therefore, as shown in FIG. 4, the distance between the SEG-dedicated terminal at the end and the SEG / COM combined terminal adjacent to the SEG-dedicated terminal is also a predetermined distance (for example, 100 μm) or more.

  As shown in FIG. 1, when the SEG / COM combined terminal group 12 and the COM dedicated terminal group 13 are arranged adjacent to each other, the SEG / COM shared terminal adjacent to the COM dedicated terminal is connected to the segment electrode. Sometimes set. Therefore, when the SEG / COM combined terminal group 12 and the COM dedicated terminal group 13 are arranged adjacent to each other, the interval between the extreme COM dedicated terminal and the SEG / COM shared terminal adjacent to the COM dedicated terminal is also predetermined. More than the interval (for example, 100 μm).

  Next, a driving method of the liquid crystal display device employed by the driver IC of the present invention will be described. The driver IC of the present invention employs IAPT as a driving method of the liquid crystal display device.

As already described, six voltage levels V _{0 to} V ₅ are used in IAPT. Here, it is assumed that V ₅ <V ₄ <V ₃ <V ₂ <V ₁ <V ₀ . At this time, the voltage V ₀ is applied to the common electrode selected at the time of positive polarity driving and also applied to the segment electrode of the column where the pixel to be turned on at the time of negative polarity driving exists. Voltages V ₁ is the voltage applied to the common electrode that is not selected during a negative polarity driving. Voltage V ₂ is the voltage applied to the segment electrodes of the column in which the pixel to be turned off when a negative polarity driving is present. Voltage V ₃ is the voltage pixels to be turned off during the positive drive is applied to the segment electrodes of columns that exist. Voltage V ₄ is the voltage applied to the common electrode that is not selected during positive drive. Voltage V ₅ is applied to the common electrode selected at a negative polarity driving, also the voltage applied to the segment electrodes of the column in which the pixel to be turned on during the positive drive is present.

The electrodes to which the voltage levels V _{0 to} V ₅ are applied are summarized as shown in FIG. As shown in FIG. 5, the difference between the voltage applied to the common electrode and the voltage applied to the segment electrode is small, and there are also voltages applied to both the common electrode and the segment electrode, such as V ₀ and V ₅ . Therefore, the withstand voltage hardly changes even when the terminals belonging to each SEG / COM combined terminal group 12 are connected to the segment electrodes or the common electrodes. Further, there are four types of voltages applied to the common electrode and four types of voltages applied to the segment electrodes. Therefore, the number of output levels does not change regardless of whether the terminals belonging to each SEG / COM combined terminal group 12 are connected to the segment electrodes or to the common electrodes. In view of the above, in the present invention having the SEG / COM combined terminal that can be connected to either the common electrode or the segment electrode, it is preferable to employ IAPT as a driving method of the liquid crystal display device.

Next, the memory will be described. Although not shown in FIGS. 1 and 2, the driver IC of the present invention includes a memory (hereinafter referred to as a built-in memory) that stores display data of an image to be displayed on the liquid crystal display device. FIG. 6 is an explanatory diagram showing the configuration of the built-in memory. The driver IC includes a memory having a capacity of (P / 2) ² × n bits as a built-in memory. Here, P is the total number of output terminals (the sum of the number of SEG dedicated terminals, the number of SEG / COM combined terminals, and the number of COM dedicated terminals). Since P is an even number, P / 2 is always an integer.

n is the number of bits per pixel necessary for displaying an image in gray scale. If n bits are used per pixel, display can be performed with 2 ⁿ gradations. When n = 1, a binary image is displayed. (P / 2) ² represents the maximum number of pixels when the total number of output terminals is P. When the total number of output terminals is determined, the number of pixels is maximized when the number of terminals connected to the segment electrode is the same as the number of terminals connected to the common electrode. The number of pixels varies depending on whether the SEG / COM shared terminal is connected to the segment electrode or the common electrode. However, even when the number of pixels is maximized, the display data storage area is not short. The driver IC includes a (P / 2) ² × n-bit internal memory. If the built-in memory having such a capacity is provided, the display data storage area will not be insufficient regardless of the setting of the SEG / COM shared terminal.

Also, as shown in FIG. 6, the bit width in the built-in memory is 8 × n bits. Word length (value storage capacity divided by the bit width of the internal memory) is ^{(P / 2) 2/8} .

When the number of segment electrodes included in the liquid crystal display device is M, display data for one line is expressed by M × n bits. In the present invention, when the display data is read from the built-in memory, the display data for one line is not read at a time, but is read every 8 × n bits. FIG. 7 is an explanatory diagram showing the timing of reading the display data of each line. In FIG. 7, COM ₁ and COM ₂ represent driving waveforms of the first row common electrode and the second row common electrode, respectively. During a period in which one line is selected (selection period), display data of a line selected later is read out. For example, the display data of the second row is read during the selection period of the first row. The display data for one line is M × n bits, and the data is read from the built-in memory every 8 × n bits. Therefore, within the selection period of one line, (M × n) / (8 × n) = The display data for one line is read in M / 8 times. Similarly, in the selection period of each line after the second row, the display data is read out divided into M / 8.

  FIG. 8 is an explanatory diagram showing a specific example of the number of memory reads per line and the maximum memory cycle. The number of memory reads per line is M / 8 times as described above. Therefore, when the number M of segment electrodes is 96, 128, and 224, the number of memory readings per line is 12, 16, and 28, respectively.

The maximum memory cycle is a speed (time) for reading display data from the built-in memory once. If the time for reading display data once from the built-in memory is slower than the maximum memory cycle, driving at a desired frame frequency cannot be realized. When the maximum memory cycle is S [μs], the desired frame frequency is F [Hz], and the number of common electrodes is N, S = 10 ⁶ / {F × N × (M / 8)}. Thus, for example, when the number of segment electrodes is 96, the number of common electrodes is 160, and the desired frame frequency is 60 Hz, the maximum memory cycle is 10 ⁶ / {60 × 160 × (96 / 8)} = 8.7 μs. The same applies to other cases.

  The memory access speed realized at the present time (September 2005) is about 100 to 300 ns. Therefore, it is now possible to make the time for reading display data once from the built-in memory faster than the maximum memory cycle illustrated in FIG. That is, there is no problem even if the display data for one line is read in M / 8 times.

  Next, an aspect of setting whether to use each of the SEG / COM shared terminals belonging to the SEG / COM shared terminal group 12 as a segment electrode terminal or a common electrode will be described. FIG. 9 is an explanatory diagram showing an example of this setting mode.

  As already described, eight SEG / COM terminals belonging to each SEG / COM terminal group 12 on both sides of the SEG dedicated terminal group 11 are grouped by eight. In the example shown in FIG. 9, the 64 SEG / COM shared terminals belonging to the SEG / COM shared terminal group 12 arranged on the left side of the SEG dedicated terminal group 11 are grouped into 8 groups from 1st to 8th. It becomes. Similarly, 64 SEG / COM shared terminals belonging to the SEG / COM shared terminal group 12 arranged on the right side of the SEG dedicated terminal group 11 are grouped into 8 groups from 9th to 16th.

The driver IC stores information (hereinafter referred to as an operation instruction signal) indicating whether to use as a segment electrode terminal or a common electrode for SEG / COM combined terminals belonging to each group. A register 21 having a plurality of 1-bit areas (hereinafter referred to as bit areas) is provided. The number of bit regions 22 is A / 16 when the total number of SEG / COM shared terminals belonging to each SEG / COM shared terminal group 12 on both sides of the SEG dedicated terminal group 11 is A. In the example shown in FIG. 9, the total number of SEG / COM shared terminals belonging to each SEG / COM shared terminal group 12 on both sides of the SEG dedicated terminal group 11 is 64 + 64 = 128. Therefore, the number of bit areas 22 is 8 (= 128/16) as shown in FIG. The operation instruction signal stored in one bit area includes one group belonging to the SEG / COM shared terminal group 12 on one side of the SEG dedicated terminal group 11 and the SEG / COM shared side on the other side of the SEG dedicated terminal group 11. It is sent to one group belonging to the terminal group 12. That is, one group belonging to the SEG / COM shared terminal group 12 on one side of the SEG dedicated terminal group 11 and one group belonging to the SEG / COM shared terminal group 12 on the other side of the SEG dedicated terminal group 11 are paired. Thus, the same operation instruction signal is sent from the same bit area to the two groups (8 × 2 = 16 SEG / COM combined terminals) in pairs. Therefore, all the settings of the SEG / COM shared terminals belonging to the two groups to be paired are common. More specifically, an operation instruction signal is sent from one bit area to a V ₁ V ₂ selection switch 64 and a V ₃ V ₄ selection switch 65 (see FIG. 13) described later. For example, _one V ₁ V ₂ selection switch 64 and one V ₃ V ₄ selection switch 65 are provided for each pair of SEG / COM combined terminals belonging to two pairs.

  Each group belonging to the SEG / COM shared terminal group 12 on one side of the SEG dedicated terminal group 11 is in one-to-one relationship with each group belonging to the SEG / COM shared terminal group 12 on the other side of the SEG dedicated terminal group 11. Paired. At this time, the groups are paired in order from the groups arranged at positions close to the SEG dedicated terminal group 11. For example, in the example shown in FIG. 9, the eighth group and the ninth group arranged at the position closest to the SEG dedicated terminal group 11 are paired. An operation instruction signal (shown as SEL_SEG8 in FIG. 9) is sent from the eighth bit area in the register 21 to the eighth group and the ninth group. Similarly, a seventh group (not shown) and a tenth group arranged at the second closest position to the SEG dedicated terminal group 11 are paired, and the two groups include the seventh group in the register 21. An operation instruction signal (shown as SEL_SEG7 in FIG. 9) is sent from a bit area (not shown). The other groups are also paired in the same manner, and a common operation instruction signal is sent from one bit area. Then, the first group and the sixteenth group arranged at the farthest position from the SEG dedicated terminal group 11 are paired, and these two groups have an operation instruction signal (see FIG. 9) from the first bit area in the register. Is shown as SEL_SEG1).

  The operation instruction signal is stored in each bit area 22 so that the setting for the segment electrode terminal is performed in order from the group arranged near the SEG dedicated terminal group 11. As a result, as shown in FIG. 10A, the groups set as the segment electrode terminals are continuously arranged from the SEG dedicated terminal group 11. The reason why each group is paired in order from the groups arranged in the position close to the SEG dedicated terminal group 11 is that the setting as the segment electrode terminal is changed from the group arranged in the position close to the SEG dedicated terminal group 11. This is so that it can be done in order. For example, if each group of SEG / COM combined terminals arranged on both sides of the SEG dedicated terminal group 11 is sequentially paired from the left side, it is connected to the segment electrode as shown in FIG. In some cases, there is a terminal connected to the common electrode between the two terminals. Then, the wiring connecting the common electrode and the SEG / COM combined terminal and the wiring connecting the segment electrode and the SEG / COM combined terminal cross each other, and the wiring cannot be routed (see FIG. 10 (b).) Therefore, each group is paired in order from the groups arranged at positions close to the SEG dedicated terminal group 11.

  The operation of storing the operation instruction signal in each bit area in the register 21 may be performed by, for example, an external MPU via the interface terminal 15 (see FIG. 1 or 2). Further, when the driver IC is connected to the liquid crystal display device and the driver IC is driving the liquid crystal display device, the setting change of each group is prohibited and the setting change is not performed. The operation instruction signal is sent from each bit area of the register 21 to each SEG / COM shared terminal group, and the operation for setting each group may be performed at the time of initialization of the driver IC, and the setting need not be changed thereafter. .

  FIG. 9 shows a case where each group is set by the register 21 having the bit area 22. The driver IC may not include the register 21, and an operation instruction signal for each group may be input from the outside, and the operation instruction signal may be sent to each group for setting. In this case, the driver IC includes a plurality of external setting terminals (not shown) to which an operation instruction signal is input from the outside (for example, a microprocessor provided outside the driver IC). The number of external setting terminals may be A / 16, similar to the number of bit areas 22 described above (A is the SEG / COM belonging to each SEG / COM shared terminal group 12 on both sides of the SEG dedicated terminal group 11). Total number of dual-purpose terminals). The mode in which the operation instruction signal is transmitted from each external setting terminal to each group is the same as the mode in which the operation instruction signal is transmitted from the bit area 11 to each group. That is, one group belonging to the SEG / COM shared terminal group 12 on one side of the SEG dedicated terminal group 11 and one group belonging to the SEG / COM shared terminal group 12 on the other side of the SEG dedicated terminal group 11 are paired. Thus, an operation instruction signal is sent from one external setting terminal to two groups (8 × 2 = 16 SEG / COM combined terminals) in pairs.

Next, an analog switch (hereinafter simply referred to as a switch) for connecting each voltage output unit used in IAPT and various terminals included in the driver IC of the present invention will be described. Each voltage used in IAPT _(V 0 ~V ₅₎ is supplied from a power supply circuit (not shown.) To driver IC.

FIG. 11 is an explanatory diagram illustrating a configuration example of a switch that connects a COM dedicated terminal and an output unit of each voltage. Voltages V ₀ , V ₅ , V ₄ , and V ₁ are supplied to the COM dedicated terminal group 13. The COM dedicated terminal group 13 is provided with a V ₀ V ₅ selection switch 42 and a V ₄ V ₁ selection switch 43, and a selection / non-selection changeover switch 41 is provided for each COM dedicated terminal.

The selection / non-selection changeover switch 41 is input with control information (hereinafter referred to as SEL) instructing whether or not to select the common electrode connected to the COM dedicated terminal. Note that SEL is input to the selection / non-selection changeover switch 41 from the latch corresponding to each common electrode. The configuration of the driver IC including the latch will be described later with reference to FIG. When the SEL instructs to select the common electrode, the selection / non-selection switch 41 connects the COM dedicated terminal and the V ₀ V ₅ selection switch 42. Further, when the SEL instructs not to select the common electrode, the selection / non-selection switch 41 connects the COM dedicated terminal and the V ₄ V ₁ selection switch 43.

The V ₀ V ₅ selection switch 42 and the V ₄ V ₁ selection switch 43 are input with a control signal (hereinafter referred to as POL) indicating polarity. When POL instructs positive polarity driving, the V ₀ V ₅ selection switch 42 connects the selection / non-selection change-over switch 41 connected to itself and the output unit of the voltage V ₀ . In this case, the voltage V ₀ is applied to the selected common electrode. When POL instructs negative polarity driving, the V ₀ V ₅ selection switch 42 connects the selection / non-selection changeover switch 41 connected to itself and the output unit of the voltage V ₅ . In this case, the voltage V ₅ is applied to the common electrode selected.

Further, when the POL instructs positive polarity driving, the V ₄ V ₁ selection switch 43 connects the selection / non-selection changeover switch 41 connected to itself and the output unit of the voltage V ₄ . In this case, voltage V ₄ is applied to the common electrode is not selected. When the POL instructs negative polarity driving, the V ₄ V ₁ selection switch 43 connects the selection / non-selection changeover switch 41 connected to itself and the output portion of the voltage V ₁ . In this case, the voltage V ₁ is applied to the common electrode is not selected.

As a result, each common electrode has a voltage (any _one of V ₀ , V ₅ , V ₄ , and V ₁ ) depending on whether it is selected and whether it is positive polarity driving or negative polarity driving. Applied.

FIG. 12 is an explanatory diagram illustrating a configuration example of a switch that connects the SEG dedicated terminal and the output unit of each voltage. Voltages V ₅ , V ₃ , V ₀ and V ₂ are supplied to the SEG dedicated terminal group 11. The SEG dedicated terminal group 11 is provided with a V ₅ V ₀ selection switch 52 and a V ₃ V ₂ selection switch 53, and a data switch 51 is provided for each individual SEG dedicated terminal.

  The data switch 51 is input with data (denoted as DATA in FIG. 12) indicating which of the applied voltage when the pixel is to be turned on and the applied voltage when the pixel is to be turned off. Is done. DATA is input to the data switch 51 from a latch (see FIG. 15 described later) corresponding to each segment electrode. When performing binary display, the data of each pixel is represented by 1-bit data “1” or “0”, and this 1-bit data is input from the latch to the data switch 51 as DATA. In the following description, “1” represents an application voltage selection instruction when the pixel should be turned on, and “0” represents an application voltage selection instruction when the pixel should be turned off. I will explain.

  When halftone display is performed, the data of each pixel is represented by data of 2 bits or more. The data of 2 bits or more turns off the applied voltage and the pixel when the pixel should be turned on. It is converted into 1-bit data indicating which of the applied voltages to be selected is to be selected. This conversion is performed by a gradation control circuit (see FIGS. 17 and 18), which will be described later, in accordance with the timing or frame within the selection period. The data converted into 1-bit data by the gradation control circuit is input to the latch, and is input from the latch to the data switch 51 as DATA.

When the DATA instructs selection of an applied voltage when the pixel is to be turned on, the data switch 51 connects the SEG dedicated terminal and the V ₅ V ₀ selection switch 52. Further, when the DATA instructs selection of an applied voltage when the pixel is to be turned off, the data switch 51 connects the SEG dedicated terminal and the V ₃ V ₂ selection switch 53.

A control signal (POL) indicating polarity is input to the V ₅ V ₀ selection switch 52 and the V ₃ V ₂ selection switch 53. When the POL instructs positive polarity driving, the V ₅ V ₀ selection switch 52 connects the data switch 51 connected to the V ₅ V ₀ selection switch to the output unit of the voltage V ₅ . In this case, the voltage V ₅ to the segment electrode of the column containing the pixel to be turned on is applied. When POL instructs negative polarity driving, the V ₅ V ₀ selection switch 52 connects the data switch 51 connected to itself and the output unit of the voltage V ₀ . In this case, the voltage V ₀ is applied to the segment electrode of the column including the pixel to be turned on.

Further, when the POL instructs the positive drive, the V ₃ V ₂ selection switch 53 connects the data switch 51 connected to the V ₃ V ₂ selection switch to the output unit of the voltage V ₃ . In this case, the voltage V ₃ is applied to the segment electrode of the column containing the pixel to be turned off. When POL instructs negative polarity driving, the V ₃ V ₂ selection switch 53 connects the data switch 51 connected to itself and the output portion of the voltage V ₂ . In this case, the voltage V ₂ is applied to the segment electrode of the column containing the pixel to be turned off.

As a result, each segment electrode is input with an instruction for selecting an applied voltage when the pixel is to be turned on, an instruction for selecting an applied voltage when the pixel is to be turned off, and the positive polarity. A voltage (any one of V ₅ , V ₀ , V ₃ , V ₂ ) according to whether driving or negative polarity driving is applied.

FIG. 13 is an explanatory diagram illustrating a configuration example of a switch that connects the SEG / COM shared terminal and the output unit of each voltage. Voltages V ₀ , V ₁ , V ₂ , V ₃ , V ₄ and V ₅ are supplied to the SEG / COM combined terminal group 12.

Of these voltages V _{0 to} V ₅ , the voltages V ₁ and V ₂ are selectively used depending on whether the SEG / COM combined terminal is designated as a common electrode terminal or a segment electrode terminal. It is done. That is, the voltage V ₁ is used when the SEG / COM combined terminal is designated as a common electrode terminal, and the voltage V ₂ is used when the SEG / COM combined terminal is designated as a segment electrode terminal. It is done. Then, the SEG / COM shared terminal group 12, it is _V 1 _{V 2} selection switch 64 for selecting either the voltage _V 1, _{V 2} are provided.

The V ₁ V ₂ selection switch 64 selects the output unit of the voltage V ₁ when an operation instruction signal indicating that the SEG / COM combined terminal is a common electrode terminal is input. _That, V 1 _{V 2} selective switch 64, by connecting the first polarity switching switch 62 and the output portion of the voltages _{V 1,} which is connected thereto, and an output portion of the voltages _{V 1,} corresponding SEG / COM combined The terminal can be connected.

Further, the V ₁ V ₂ selection switch 64 selects the output part of the voltage V ₂ when an operation instruction signal indicating that the SEG / COM combined terminal is used as the segment electrode terminal is input. _That, V 1 _{V 2} selective switch 64, by connecting the first polarity output of the changeover switch 62 and the voltage _{V 2} which is connected thereto, and an output portion of the voltage _{V 2,} corresponding SEG / COM combined The terminal can be connected.

Similarly, among the voltages V _{0 to} V ₅ , the voltages V ₃ and V ₄ are also selected depending on whether the SEG / COM combined terminal is designated as a common electrode terminal or a segment electrode terminal. Used for. That is, used when the voltage V ₃ is used when SEG / COM shared pins are designated as terminals for the segment electrodes, the voltage V ₄ is the SEG / COM shared pins are designated as terminals for the common electrode It is done. Then, the SEG / COM shared terminal group 12, the _V 3 _{V 4} selection switch 65 for selecting either the voltage _V 3, _{V 4} are provided.

The V ₃ V ₄ selection switch 65 selects the output unit of the voltage V ₄ when an operation instruction signal indicating that the SEG / COM combined terminal is a common electrode terminal is input. _That, V 3 _{V 4} selection switch 65, by connecting the output of the first polarity switching switch 62 and the voltage _{V 4} that is connected to it, and an output portion of the voltage _{V 4,} the corresponding SEG / COM combined The terminal can be connected.

Further, the V ₃ V ₄ selection switch 65 selects the output part of the voltage V ₃ when the operation instruction signal indicating that the SEG / COM combined terminal is used as the segment electrode terminal is input. _That, V 3 _{V 4} selection switch 65, by connecting the output of the first polarity switching switch 62 and the voltage _{V 3} which is connected thereto, and an output portion of the voltage _{V 3,} corresponding SEG / COM combined The terminal can be connected.

As already described, eight SEG / COM shared terminals are grouped, and each of the SEG / COM shared terminals belonging to two pairs of the groups arranged on both sides of the SEG dedicated terminal group 11 is paired. All settings are common. Therefore, since eight SEG / COM shared terminals belong to one group, the 16 SEG / COM shared terminals belonging to the two groups to be paired have a common setting. Therefore, _one V ₁ V ₂ selection switch 64 and one V ₃ V ₄ selection switch 65 may be provided for each of the 16 SEG / COM shared terminals. Here it will be described as providing one 16 SEG / COM shared pins _V 1 _{V 2} selection switches 64 and _V 3 _{V 4} selection switch 65 for each. _One V ₁ V ₂ selection switch 64 and one V ₃ V ₄ selection switch 65 may be provided for every eight SEG / COM shared terminals. _However, V 1 _{V 2} to minimize the number of selection switches 64 and _V 3 _{V 4} selection switch 65, _V 1 _{V 2} selection switches 64 and _V 3 _{V 4} selection switch 65 for each 16 SEG / COM shared pins Are preferably provided one by one.

For example, an operation instruction signal is input to the V ₁ V ₂ selection switch 64 and the V ₃ V ₄ selection switch 65 from the register 21 (see FIG. 9) or an external setting terminal (not shown) when the driver IC is initialized. Is done. After that, it is not necessary to switch the V ₁ V ₂ selection switch 64 and the V ₃ V ₄ selection switch 65.

Of the voltages _V 0 ~V _5, there in case voltage _V 0, _{V 5,} even if the SEG / COM shared pins are designated as terminals for the common electrode, which are designated as terminals for the segment electrodes Even used.

  Each SEG / COM combined terminal is provided with one combination of the data switch 61, the first polarity changeover switch 62, and the second polarity changeover switch 63.

  When the SEG / COM combined terminal is used as a terminal connected to the common electrode, the data switch 61 receives control information (SEL) indicating whether or not to select the common electrode from the latch. When the SEG / COM combined terminal is used as a terminal connected to the segment electrode, the data switch 61 has either an applied voltage when the pixel is to be turned on or an applied voltage when the pixel is to be turned off. Data indicating whether to select is input from the latch. The data switch 61 connects the SEG / COM combined terminal to either the first polarity changeover switch 62 or the second polarity changeover switch 63 in accordance with the input control information (SEL) or data.

The first polarity changeover switch 62 and the second polarity changeover switch 63 are supplied with a control signal (POL) indicating polarity. The first polarity changeover switch 62 selects the data switch 61 as the V ₁ V ₂ selection switch 64 or V ₃ V ₄ depending on whether the POL instructs positive polarity driving or negative polarity driving. Connect to one of the switches 65. The second polarity changeover switch 63 sets the data switch to either the output unit of the voltage V ₀ or the output unit of the voltage V ₅ depending on whether the POL instructs the positive polarity drive or the negative polarity drive. Connect to

The SEG / COM dual-purpose terminal according to data and control signals input to the data switch 61, the first polarity changeover switch 62, the second polarity changeover switch 63, the V ₁ V ₂ selection switch 64, and the V ₃ V ₄ selection switch 65 The voltage applied to the electrode connected to is determined. FIG. 14 is an explanatory diagram showing the voltage applied to the electrode connected to the SEG / COM combined terminal in accordance with the input to each switch. In FIG. 14, the operation instruction signal for instructing use as a segment electrode terminal is set to “0”. In addition, an operation instruction signal for instructing use as a common electrode terminal is set to “1”. Further, POL for instructing positive polarity driving is set to “0”, and POL for instructing negative polarity driving is set to “1”.

A case where “0 (instruction to use as segment electrode terminal)” is input as an operation signal to the V ₁ V ₂ selection switch 64 and the V ₃ V ₄ selection switch 65 will be described. In this case, the V ₁ V ₂ selection switch 64 selects the V ₂ output section, and the V ₃ V ₄ selection switch 65 selects the V ₃ output section. In this case, the data switch 61 has data indicating which one of the applied voltage when the pixel is to be turned on and the applied voltage when the pixel is to be turned off (in FIGS. 13 and 14). DATA.) Is input.

When “0 (voltage instruction when turned off)” is input to the data switch 61 as the DATA, the data switch 61 connects the SEG / COM combined terminal to the first polarity switch 62. At this time, it is assumed that “0 (positive polarity instruction)” is input to the first polarity changeover switch 62 as POL. Then, the first polarity changeover switch 62 connects the data switch 61 to the V ₃ V ₄ selection switch 65. Since the V ₃ V ₄ selection switch 65 is in the state of selecting the output portion of the voltage V ₃ , as a result, V ₃ is applied to the segment electrode connected to the SEG / COM shared terminal (see FIG. 14). Aspect 1) shown. Further, it is assumed that “1 (negative polarity instruction)” is input to the first polarity changeover switch 62 as POL. Then, the first polarity changeover switch 62 connects the data switch 61 to the V ₁ V ₂ selection switch 64. Since the V ₁ V ₂ selection switch 64 is in the state of selecting the output portion of the voltage V ₂ , as a result, V ₂ is applied to the segment electrode connected to the SEG / COM combined terminal (see FIG. 14). Aspect 3) shown.

When “1 (voltage instruction when ON)” is input to the data switch 61, the data switch 61 connects the SEG / COM shared terminal to the second polarity switch 63. At this time, it is assumed that “0 (positive polarity instruction)” is input to the second polarity changeover switch 63 as POL. Then, the second polarity switching switch 63 to connect the data switch 61 to the output of the voltage V _5. As a result, _{V 5} is applied to the segment electrode connected to the SEG / COM shared pins (embodiment shown in FIG. 14 5). Further, it is assumed that “1 (negative polarity instruction)” is input to the second polarity changeover switch 63 as POL. Then, the second polarity switching switch 63 to connect the data switch 61 to the output of the voltage V _0. As a result, V ₀ is applied to the segment electrode connected to the SEG / COM combined terminal (mode 7 shown in FIG. 14).

Next, a case where “1 (instruction to use as a common electrode terminal)” is input as an operation signal to the V ₁ V ₂ selection switch 64 and the V ₃ V ₄ selection switch 65 will be described. In this case, the V ₁ V ₂ selection switch 64 selects the V ₁ output section, and the V ₃ V ₄ selection switch 65 selects the V ₄ output section. In this case, control information (SEL) indicating whether or not to select the common electrode is input to the data switch 61. Here, SEL for not selecting the common electrode connected to the SEG / COM shared terminal is set to “0”, and SEL for selecting the common electrode connected to the SEG / COM shared terminal is set to “1”. To do.

When “0 (instruction not to select the common electrode connected to the terminal)” is input to the data switch 61 as the SEL, the data switch 61 connects the SEG / COM combined terminal to the first polarity switch 62. . At this time, it is assumed that “0 (positive polarity instruction)” is input to the first polarity changeover switch 62 as POL. Then, the first polarity changeover switch 62 connects the data switch 61 to the V ₃ V ₄ selection switch 65. Since the V ₃ V ₄ selection switch 65 is in the state of selecting the output portion of the voltage V ₄ , as a result, V ₄ is applied to the common electrode connected to the SEG / COM shared terminal (see FIG. 14). Aspect 2) shown. Further, it is assumed that “1 (negative polarity instruction)” is input to the first polarity changeover switch 62 as POL. Then, the first polarity changeover switch 62 connects the data switch 61 to the V ₁ V ₂ selection switch 65. Since the V ₁ V ₂ selection switch is in the state of selecting the output section of the voltage V ₁ , as a result, V ₁ is applied to the common electrode connected to the SEG / COM shared terminal (shown in FIG. 14). Aspect 4).

When “1 (instruction to select a common electrode connected to a terminal)” is input to the data switch 61 as the SEL, the data switch 61 connects the SEG / COM combined terminal to the second polarity switch 63. . At this time, it is assumed that “0 (positive polarity instruction)” is input to the second polarity changeover switch 63 as POL. Then, the second polarity switching switch 63 to connect the data switch 61 to the output of the voltage V _0. As a result, V ₀ is applied to the common electrode connected to the SEG / COM combined terminal (mode 6 shown in FIG. 14). Further, it is assumed that “1 (negative polarity instruction)” is input to the second polarity changeover switch 63 as POL. Then, the second polarity switching switch 63 to connect the data switch 61 to the output of the voltage V _5. As a result, V ₅ is applied to the common electrode connected to the SEG / COM combined terminal (mode 8 shown in FIG. 14).

  Next, the configuration of the entire driver IC will be described. Here, in order to simplify the description, first, the case where the built-in memory stores the display data of the binary image will be described as an example. FIG. 15 is a block diagram illustrating a configuration example of the driver IC. The driver IC includes an analog switch group 71, an analog switch group 72, an analog switch group 73, in addition to the SEG dedicated terminal group 11, the SEG / COM combined terminal group 12, and the COM dedicated terminal group 13 shown in FIG. A latch 75, a multiplexer 76, a line buffer 78, a first COM buffer 81, a second COM buffer 82, and a built-in memory 83 are provided. In addition, although not shown in FIG. 15, a control unit that outputs control signals such as a POL, a latch signal, and a write signal is provided. Also, the source of the operation instruction signal (for example, the register 21 shown in FIG. 9) is not shown in FIG.

The V ₀ V ₅ selection switch 42, the V ₄ V ₁ selection switch 43, and the selection / non-selection changeover switch 41 (see FIG. 11) provided for each individual COM terminal correspond to the analog switch group 71. . Further, the V ₁ V ₂ selection switch 64, the V ₃ V ₄ selection switch 65, the data switch 61 provided for each SEG / COM combined terminal, the first polarity switching switch 62, the second polarity switching switch 63 (FIG. 13). (Refer to the analog switch group 72). Further, the V ₅ V ₀ selection switch 52, the V ₃ V ₂ selection switch 53, and the data switch 51 (see FIG. 12) provided for each individual SEG dedicated terminal correspond to the analog switch group 73.

  The line buffer 78 corresponds to the total number of terminals belonging to the SEG dedicated terminal group 11 and the terminals belonging to the SEG / COM shared terminal groups 12 arranged on both sides of the SEG dedicated terminal group 11 (this total number is Q). This is realized by a register having the number of bits. If the line buffer 78 includes a Q-bit register, the line buffer 78 can be used for one line even when all the terminals belonging to the SEG / COM shared terminal group 12 are set as the segment electrode terminals. Display data can be stored.

  Further, as described above, when the display data for one line is read from the built-in memory 83, the display data for one line is not read at a time, but is read every 8 × n bits. In this example, display data of a binary image is read out, so reading is performed every 8 bits. The line buffer 78 and the control unit (not shown) are connected by signal wiring for Q / 8 dedicated write signals. For example, when there are 96 terminals belonging to the SEG dedicated terminal group 11 and each SEG / COM combined terminal group disposed on both sides of the SEG dedicated terminal group 11 includes 64 terminals, Q = 96 + 64 × 2 = 224. Therefore, the number of signal lines of the dedicated write signal is 224/8 = 28.

  Depending on which signal wiring is transmitted from the control unit via the dedicated write signal, it is determined in which area of the line buffer 78 the 8-bit display data read from the built-in memory is stored. In synchronization with the reading of the internal memory 83, the control unit transmits a dedicated write signal via the signal wiring corresponding to the writing area so as to write 8-bit data in the line buffer 78. The control unit reads out display data from the built-in memory 83 and stores display data in the line buffer 78.

  FIG. 16 is an explanatory diagram showing storage of display data in the line buffer 78. When the display data is stored in the bits corresponding to, for example, it is assumed that the left terminal (segment electrode terminal) group in FIG. 16 is sequentially stored. In this case, the control unit (not shown) transmits a dedicated write signal via a wiring signal corresponding to the bit group “No. 1” shown in FIG. Write to group No. 1 ". Next, a dedicated write signal is transmitted via a wiring signal corresponding to the bit group “No. 2” shown in FIG. 16, and display data is written in the group “No. 2”. The same operation is repeated, and data for one line is written into the line buffer within the selection period.

  The first COM buffer 81 is realized by a register having the number of bits corresponding to the terminals belonging to the COM dedicated terminal group 13. Each bit included in the first COM buffer 81 corresponds to a COM dedicated terminal. Each bit included in the first COM buffer 81 stores control information (SEL) indicating whether or not to select the corresponding common electrode.

  The second COM buffer 82 is realized by a register having the number of bits corresponding to the terminals belonging to the SEG / COM combined terminal group 12. If the second COM buffer 82 includes a register for the number of bits corresponding to the terminals belonging to the SEG / COM shared terminal group 12, all the terminals belonging to the SEG / COM shared terminal group 12 are set as the common electrode terminals. Even in this case, the control information indicating whether or not to select each common electrode can be stored in the first COM buffer 81 and the second COM buffer 82.

  Note that a register for realizing the first COM buffer 81 and the second COM buffer may be a shift register or a general-purpose register.

  The driver IC includes the same number of multiplexers 76 as the number of terminals belonging to the SEG / COM shared terminal group 12. Each multiplexer 76 has a one-to-one correspondence with each SEG / COM shared terminal. Each multiplexer 76 receives 1-bit data from the second COM buffer 82 and the line buffer 78 as data of the corresponding SEG / COM shared terminal. The multiplexer 76 functions as a selector that selects and outputs only one of the two types of input data. When an operation instruction signal (SEL_SEG) indicating that the corresponding SEG / COM shared terminal is used as a segment electrode terminal is input to the multiplexer 76, the multiplexer 76 selects data from the line buffer 78. Output to latch. When an operation instruction signal (SEL_SEG) indicating that the corresponding SEG / COM shared terminal is a common electrode terminal is input to the multiplexer 76, the multiplexer 76 receives data from the second common buffer 82. Is output to the latch.

  The multiplexers 76 are grouped in the same manner as the corresponding SEG / COM shared terminals. The same bit area as the bit area 22 (see FIG. 9) for sending an operation instruction signal to the group of SEG / COM shared terminals to the group of multiplexers 76 corresponding to the corresponding group of SEG / COM shared terminals. Sends an operation instruction signal. For example, to the group of multiplexers 76 corresponding to the SEG / COM shared terminals of the eighth group and the ninth group shown in FIG. 9, an operation instruction signal is sent to the eighth group and the ninth group shown in FIG. An operation instruction signal is sent from the eighth bit area. The same applies to an operation instruction signal transmitted from the outside to the multiplexer 76 via an external setting terminal (not shown).

  The operation of transmitting the operation instruction signal to each multiplexer 76 and setting each multiplexer 76 may be performed at the time of initialization of the driver IC, and the setting need not be changed thereafter.

  Information (display data and SEL) stored in the line buffer 78, the first COM buffer 81, and the second COM buffer 82 is sent to the latch 75 at the end of the selection period. The information stored in the line buffer 78, the first COM buffer 81, and the second COM buffer 82 is updated.

Also, among the display data stored in the line buffer 78, display data corresponding to the SEG dedicated terminal is transmitted to the latch 75 _c included in the latch 75. Latch 75 _c has a storage area of the number of bits equal to the SEG dedicated terminals. When the latch signal to the latch 75 is transmitted from the control unit, the latch 75 _c outputs the display data corresponding to each SEG dedicated terminal, the data switch 51 in the analog switch group 73 (see FIG. 12.). The control unit outputs POL in synchronization with the data output from the latch 75. As a result, each switch in the analog switch group 73 is set, and the voltage corresponding to the display data and POL is output to each SEG dedicated terminal.

Display data stored in the line buffer 78 and corresponding to each SEG / COM shared terminal set as a segment electrode terminal is sent to each multiplexer 76 corresponding to each SEG / COM shared terminal. It is done. Each multiplexer 76 receives an operation instruction signal indicating that the corresponding SEG / COM combined terminal is used as a segment electrode terminal when the driver IC is initialized. Thus, each multiplexer 76 described above, the data is input from the first 2COM buffer 82, and outputs only the display data input from the line buffer 78 to the latch 75 _b. Latch 75 _b has a storage area of the number of bits equal to the respective SEG / COM shared terminal. Each multiplexer 76 described above, the display data inputted from the line buffer 78, and outputs the corresponding bit in the latch 75 _b. When the latch signal to the latch 75 is transmitted from the control unit, the latch 75 _b outputs the data stored in the bit, the data switch 61 corresponding analog switch group 72 (see FIG. 13.). The control unit outputs POL in synchronization with the data output from the latch 75. An operation instruction signal (SEL_SEG) is input in advance to the V ₁ V ₂ selection switch 64 and the V ₃ V ₄ selection switch 65. As a result, each switch in the analog switch group 73 is set, and a voltage corresponding to the display data and POL is output to each SEG / COM shared terminal set as the segment electrode terminal.

The control information (SEL) stored in the second COM buffer 82 and corresponding to each SEG / COM shared terminal set as the common electrode terminal is represented by each multiplexer corresponding to each SEG / COM shared terminal. 76. Each multiplexer 76 receives an operation instruction signal indicating that the corresponding SEG / COM combined terminal is a common electrode terminal when the driver IC is initialized. Thus, each multiplexer 76 described above, the data is input from the line buffer 78, and outputs only the display data input from the 2COM buffer 82 to latch 75 _b. Each multiplexer 76 described above, the SEL input from the 2COM buffer 82, and outputs the corresponding bit in the latch 75 _b. When the latch signal to the latch 75 is transmitted from the control unit, the latch 75 _b outputs a SEL stored in this bit, the data switch 61 corresponding analog switch group 72 (see FIG. 13.). The control unit outputs POL in synchronization with the data output from the latch 75. An operation instruction signal is input to the V ₁ V ₂ selection switch 64 and the V ₃ V ₄ selection switch 65 in advance. As a result, each switch in the analog switch group 73 is set, and a voltage corresponding to SEL and POL is output to each SEG / COM shared terminal set as the common electrode terminal.

The SEL stored in the first COM buffer 81 is sent to _a latch 75 _a included in the latch 75. The latch 75a has _a storage area with the same number of bits as the COM dedicated terminal. When the latch signal to the latch 75 is transmitted from the control unit, the latch 75 _a is output, the SEL corresponding to the COM-only terminals, the in the analog switch group 71 selected / non-selected selector switch 41 (see FIG. 11.) To do. The control unit outputs POL in synchronization with the data output from the latch 75. As a result, each switch in the analog switch group 71 is set, and a voltage corresponding to SEL and POL is output to each COM dedicated terminal.

  Next, the case where the built-in memory stores grayscale display data will be described as an example. As a method of displaying an image in gray scale, for example, there are FRC (Frame Rate Control) and PWM (Pulse Width Modulation).

  FIG. 17 is a block diagram illustrating a configuration example of a driver IC when the FRC is employed. Constituent parts similar to the constituent parts shown in FIG. A driver IC in the case of employing FRC is different from the driver IC shown in FIG. 15 in that it includes a gradation control circuit 91.

  The built-in memory 83 shown in FIG. 17 stores n-bit display data per pixel. The gradation control circuit 91 stores display data from the built-in memory 83 every 8 × n bits in response to a command from a control unit (not shown). In the FRC, the voltage applied to the segment electrode is not changed during the selection period. The voltage applied to the segment electrodes in FRC is changed at the start of the frame period. For each frame period, the gradation control circuit 91 determines whether a voltage for turning on is applied to the segment electrode or a voltage for turning off is applied to the segment electrode for each pixel. Information on whether a voltage for turning on or a voltage for turning off is applied can be represented by “0” or “1”. That is, when focusing on one frame period, the data amount of one pixel can be reduced from n bits to 1 bit. The gradation control circuit 91 performs processing for converting the data of each pixel included in the display data from n bits to 1 bit. Then, the converted data is stored. However, whether the same pixel is converted to “0” or “1” differs depending on the frame period.

  The line buffer 78 is realized by a register of Q bits as in the case shown in FIG. Then, the display data for one line converted by the gradation control circuit 91 is stored. The operation for storing the converted data stored in the gradation control circuit 91 in the line buffer 78 is the same as the operation for storing the data for one line stored in the built-in memory 83 in the line buffer 78 in the configuration shown in FIG. It is.

  Other operations are the same as those in the configuration shown in FIG.

  FIG. 18 is a block diagram illustrating a configuration example of a driver IC when the PWM is employed. Constituent parts similar to the constituent parts shown in FIG. A driver IC in the case of employing PWM is different from the driver IC shown in FIG. Further, the gradation control circuit 93 illustrated in FIG. 18 performs processing different from that of the gradation control circuit 91 illustrated in FIG.

  The internal memory 83 shown in FIG. 18 stores n-bit display data per pixel. The line buffer 78 shown in FIG. 18 is realized by a Q × n-bit register, unlike the configuration shown in FIG. When reading display data for one line from the built-in memory 83, it is read every 8 × n bits. The 8 × n-bit data is stored in an area in the line buffer 78 designated by the dedicated write signal. The amount of data in one data read and storage in the line buffer is different from that shown in FIG. 15, but the other points regarding display data storage in the line buffer 78 are the same as the operations described in FIG. 15.

The gradation control circuit 93 reads display data for one line stored in the line buffer 78. In PWM, the applied voltage to the segment electrode is changed not only at the start of the selection period but also during the selection period. When the display data of one pixel is represented by n bits, for example, the voltage applied to the segment electrode can be changed every period obtained by dividing the selection period into n equal parts. Gradation control circuit 93, at the start of the selection period, and outputs the data of the most significant bit of each pixel included in one line, in each multiplexer 76 and latch 75 _c corresponding to each pixel. The operation of the multiplexer 76 that has received 1-bit data from the gradation control circuit 93 is the same as that described with reference to FIG. Thereafter, during the selection period of one common electrode, the gradation control circuit 93 sequentially changes the 1-bit data of each pixel included in one line from the upper bit every time 1 / n of the selection period elapses. to be output to the multiplexer 76 and latch 75 _c corresponding to each pixel. Multiplexer 76 outputs a 1-bit data input from the gradation control circuit 76 to the latch 75 _b.

In addition, the control unit (not shown) outputs a latch signal to the latches 75 _b and 75 _c every period obtained by dividing the selection period into n equal parts. As a result, the latches 75 _b and 75 _c output 1-bit display data (“0” or “1”) every period obtained by dividing the selection period into n equal parts. The control unit may output a latch signal at the beginning of the selection period to the latch 75 _a.

  Other operations are the same as those in the configuration shown in FIG. By such an operation, the voltage applied to the segment electrode is changed according to the display data during the selection period, and the gray scale display of the display data by PWM is performed.

  The driver IC of the present invention includes not only a SEG dedicated terminal group and a COM dedicated terminal group but also a SEG / COM combined terminal group. Therefore, the present invention can be applied to liquid crystal display devices with various resolutions depending on whether the terminals included in the SEG / COM combined terminal group are set as segment electrode terminals or common electrode terminals.

  For example, FIG. 19 is an explanatory diagram showing an example of a liquid crystal display device to which the driver IC of the present invention can be applied. The driver IC has 96 terminals as the SEG dedicated terminal group 11, has a total of 128 (64 × 2) terminals as the SEG / COM combined terminal group 12, and has a total of 32 as the COM dedicated terminal group 13. It is assumed that (16 × 2) terminals are provided. When all 128 SEG / COM shared terminals are set as common electrode terminals, as shown in FIG. 19A, a driver IC is applied to a liquid crystal display device using STN liquid crystal with a resolution of 96 × 160. can do. When all 128 SEG / COM shared terminals are set as segment electrode terminals, as shown in FIG. 19B, a driver IC is used for a liquid crystal display device using STN liquid crystal having a resolution of 224 × 32. Can be applied. Also, by setting some of the 128 SEG / COM shared terminals as segment electrode terminals and the rest as common electrode terminals, the driver IC can be applied to, for example, a 128 × 128 liquid crystal display device. can do. Thus, the driver IC of the present invention can be applied to liquid crystal display devices with various resolutions. As a result, there is no need to develop a driver IC for each liquid crystal display device with various resolutions, and the cost required for driver IC development such as evaluation of driver ICs and software development can be reduced.

  Since the driver IC of the present invention can be applied to liquid crystal display devices with various resolutions, the number of production can be increased.

In the present invention, the setting of the SEG / COM dual-purpose terminal and the common electrode terminal or the segment electrode terminal is set to the V ₁ V ₂ selection switch 64 and the V ₃ V ₄ selection switch 65 (see FIG. 13). .)) By transmitting an operation instruction signal. The V ₁ V ₂ selection switch 64 and the V ₃ V ₄ selection switch 65 may be provided, for example, for each set of 16 SEG / COM combined terminals, so that the number of switches does not increase remarkably. Also good.

The signal electrode dedicated terminal described in the claims is realized by an SEG dedicated terminal. The scanning electrode dedicated terminal is realized by a COM dedicated terminal. The shared terminal is realized by an SEG / COM shared terminal. The voltage selection switch is realized by a V ₁ V ₂ selection switch 64 and a V ₃ V ₄ selection switch 65.

  The present invention can be applied to a one-chip driver IC for driving a liquid crystal display device.

Explanatory drawing which shows the example of arrangement | positioning of the output terminal of driver IC for liquid crystal display devices of this invention. Explanatory drawing which shows the example at the time of arrange | positioning a COM exclusive terminal group in the edge | side different from a SEG exclusive terminal group and each SEG / COM combined terminal group. Explanatory drawing which shows the reason for arrange | positioning a SEG exclusive terminal group and each SEG / COM combined terminal group in the same edge | side. Explanatory drawing which shows the space | interval of the group of SEG / COM combined terminal. Explanatory drawing which shows to which electrode each voltage level used in IAPT is applied. Explanatory drawing which shows the structure of a built-in memory. Explanatory drawing which shows the timing which reads the display data of each line. Explanatory drawing which shows the specific example of the memory read count per line and the maximum memory cycle. Explanatory drawing which shows an example of the setting aspect of each SEG / COM combined terminal. Explanatory drawing which shows the reason for making each group a pair in order from the groups arrange | positioned in the position close | similar to a SEG exclusive terminal group. Explanatory drawing which shows the structural example of the switch which connects a COM exclusive terminal and the output part of each voltage. Explanatory drawing which shows the structural example of the switch which connects the SEG exclusive terminal and the output part of each voltage. Explanatory drawing which shows the structural example of the switch which connects the SEG / COM combined terminal and the output part of each voltage. Explanatory drawing which shows the voltage applied to the electrode connected to the SEG / COM combined terminal according to the input to each switch. The block diagram which shows the structural example of driver IC. Explanatory drawing which shows the storage of the display data to the line buffer 78. FIG. The block diagram which shows the structural example of driver IC in the case of employ | adopting FRC. The block diagram which shows the structural example of driver IC in the case of employ | adopting PWM. FIG. 6 is an explanatory diagram illustrating an example of a liquid crystal display device to which the driver IC of the present invention can be applied. Explanatory drawing which shows the example of the drive waveform in IAPT. Explanatory drawing which shows the restriction | limiting of the resolution in the conventional driver IC for liquid crystal display devices.

Explanation of symbols

1 chip 11 SEG dedicated terminal group 12 SEG / COM combined terminal group 13 COM dedicated terminal group 71 to 73 analog switch group 75 latch 76 multiplexer 78 line buffer 81 first COM buffer 82 second COM buffer 83 built-in memory

Claims (5)

A driver IC for a liquid crystal display device that drives a liquid crystal display device that sandwiches liquid crystal between a plurality of scanning electrodes and a plurality of signal electrodes,
A plurality of signal electrode dedicated terminals connected only to the signal electrodes;
A plurality of scan electrode dedicated terminals connected only to the scan electrodes;
A driver IC for a liquid crystal display device comprising a plurality of dual-purpose terminals that can be connected to either a signal electrode or a scanning electrode. Select the voltage used when the dual-purpose terminal is connected to the signal electrode, or the voltage used when the dual-purpose terminal is connected to the scan electrode, and apply the selected voltage to the electrode connected to the dual-purpose terminal The driver IC for a liquid crystal display device according to claim 1, further comprising a voltage selection switch that enables the liquid crystal display device. A voltage selection switch is provided for each set of a predetermined number of dual-purpose terminals,
Each voltage selection switch
When an operation instruction signal indicating that the corresponding shared terminal is connected to the signal electrode is input, a voltage output unit used when the shared terminal is connected to the signal electrode and the corresponding shared terminal are connected. It is possible to connect,
When an operation instruction signal indicating that the corresponding dual-purpose terminal is connected to the scan electrode is input, a voltage output unit used when the dual-purpose terminal is connected to the scan electrode and the corresponding dual-purpose terminal are connected. The driver IC for a liquid crystal display device according to claim 2, wherein the driver IC is in a connectable state. A register for storing an operation instruction signal in advance for each set of a predetermined number of dual-purpose terminals is provided,
The liquid crystal display driver IC according to claim 3, wherein each voltage selection switch receives an operation instruction signal from a register. An external setting terminal for inputting an operation instruction signal from the outside is provided for each set of a predetermined number of dual-purpose terminals,
The liquid crystal display driver IC according to claim 3, wherein each voltage selection switch receives an operation instruction signal from the outside via an external setting terminal.

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