JP2007093666A - Driving circuit of eletro-optic device and electro-optic device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To match a frame period when a high frequency clock is used to a frame period when a low frequency clock is used without increasing packaging area. <P>SOLUTION: This electro-optic device is characterized by being equipped with a first oscillation circuit 18 which generates a first clock for generating a timing signal for a first display mode, a second oscillation circuit 19 which generates a second clock for generating a timing signal for a second display mode and with frequency lower than that of the first clock and an adjustment means 17 for adjusting the frequency of the second clock according to a frame period to be regulated by the timing signal on the basis of the first clock based on the control signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a drive circuit for an electro-optical device suitable for a liquid crystal display panel that reduces power consumption by using a plurality of clocks having different frequencies, and an electro-optical device using the drive circuit.

  A liquid crystal display device, which is an example of an electro-optical device, includes a liquid crystal display module (LCD module) in which pixels are configured by interposing liquid crystals between substrates, and a driver that drives the LCD module. Examples of the driver include a scanning line driving circuit and a data line driving circuit.

  When displaying an image on the LCD module, the display data stored in the video RAM is read out by the liquid crystal controller and transferred to the LCD module. When performing gradation display, the liquid crystal controller uses a high-frequency clock in order to perform transfer to the LCD module at high speed.

  In addition, a binary image may be displayed on the LCD module. In such a case, display data may be transferred to the LCD module at a low transfer rate, and the liquid crystal controller performs data transfer using a low frequency clock.

In Patent Document 1, a high-frequency oscillation circuit that generates a high-frequency clock and a low-frequency oscillation circuit that generates a low-frequency clock are prepared, and the high-frequency oscillation circuit is intermittently operated in accordance with a display data processing command, whereby a liquid crystal display device Technologies for reducing the overall power consumption have been proposed.
Japanese Patent Laid-Open No. 2002-40978

  By the way, in the proposal of patent document 1, low-frequency clock and high-frequency clock are generated by separate circuits, and each circuit is individually controlled to reduce power consumption.

  However, since the low-frequency oscillation circuit and the high-frequency oscillation circuit are configured separately, the frame frequency differs slightly when using the low-frequency clock and when using the high-frequency clock due to variations in the oscillation frequency of each oscillation circuit. There is.

  Due to such a difference in frame frequency, there is a problem that the contrast is different between the gradation display and the binary image display, and the color changes.

  The present invention has been made in view of such a problem, and is a drive circuit for an electro-optical device that can match the frame frequency when using a low-frequency clock and when using a high-frequency clock, and an electro-optical device using the same The purpose is to provide.

  The drive circuit of the electro-optical device according to the present invention includes a first oscillation circuit that generates a first clock for generating a timing signal for the first display mode, and a timing signal for the second display mode. A second oscillation circuit for generating a second clock having a frequency lower than that of the first clock, and a timing based on the first clock based on a control signal And adjusting means for adjusting the frequency of the second clock in correspondence with a frame period defined by the signal.

  According to such a configuration, the first oscillation circuit generates the first clock, and the timing signal for the first display mode is generated using the first clock. In the second display mode, a second clock is generated by the second oscillation circuit, and a timing signal is generated based on the second clock. The second clock has a frequency lower than that of the first clock, and lower power consumption can be achieved in the second display mode than in the first display mode. The adjusting means adjusts the frequency of the second clock based on the control signal so as to correspond to the frame period defined by the timing signal based on the first clock. Thereby, the frame period in the second display mode using the second clock can be matched with the frame period in the first display mode. The frequency of the second clock can be adjusted by the control signal, and the display quality in the first display mode and the second display mode can be easily aligned.

  Further, the oscillation frequency of the second oscillation circuit varies depending on the values of the resistance and the capacitance, and the adjustment unit controls the value of at least one of the resistance and the capacitance based on the control signal, thereby The frequency of the second clock is adjusted.

  According to such a configuration, the oscillation frequency of the second oscillation circuit can be changed by the values of the resistance and the capacitance. The adjusting unit adjusts the frequency of the second clock by controlling at least one of the resistance and the capacitance based on the control signal. Thereby, the display quality in the first display mode and the second display mode can be easily aligned.

  The adjusting means adjusts the frequency of the second clock by controlling on and off a switch element for selecting one of a plurality of resistance values based on the control signal. It is characterized by.

  According to such a configuration, the adjustment means can be configured by providing a switch element for selecting a resistance value, and the display quality in the first display mode and the second display mode can be configured with a simple configuration. Can be aligned.

  Further, the first display mode is gradation display, and the second display mode is binary image display.

  According to such a configuration, it is possible to prevent the display quality from changing between the gradation display and the binary image display.

  According to another aspect of the invention, an electro-optical device includes a driving circuit for the electro-optical device and pixels corresponding to intersections of a plurality of scanning lines and a plurality of data lines. And a display region in which pixels are driven.

  According to such a configuration, it is possible to display an image with the same display quality in the first and second display modes.

  Further, the first and second oscillation circuits are formed on a substrate provided with the pixels.

  According to such a configuration, the characteristics of the first and second oscillation circuits can be substantially matched, and the frame period in the first display mode can be achieved even when the frequencies of the first and second clocks vary. And the frame period in the second display mode can be relatively matched.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a drive circuit of an electro-optical device according to an embodiment of the present invention. This embodiment shows an example in which the electro-optical device is applied to a liquid crystal display device using, for example, a TFD (Thin Film Diode) that is a two-terminal switching element. FIG. 2 is a perspective view schematically showing the entire structure of the liquid crystal display device.

<Configuration>
As shown in FIG. 2, the electro-optical device 31 has a configuration in which a pair of substrates 32 and 33 are disposed to face each other and a liquid crystal 34 is sealed between the substrates. The substrates 32 and 33 have a matrix of pixels corresponding to intersections of a plurality of scanning lines (not shown) extending in the horizontal direction and a plurality of data lines (not shown) extending in the vertical direction. Arranged in a shape.

  In the display area 37 surrounded by a broken line, a data signal is supplied to each pixel via a data line, and a scanning signal is supplied via a scanning line. A data signal is given to each pixel of the line selected by the scanning signal via the data line. As a result, the state of the liquid crystal 34 between the substrates 32 and 33 changes, and the transmittance of each pixel changes according to the display data. In this way, image display is performed.

  On the element substrate 32 constituting the electro-optical device 31, a driver unit 35 for driving the scanning lines and the data lines is formed in a region other than the display region 37 where the pixels are formed. The driver unit 35 includes a scanning line driving circuit 20 (see FIG. 1) and a data line driving circuit 21 which will be described later, and is mounted by a COG (Chip On Glass) technique. The scanning line driving circuit supplies a scanning signal to the scanning line, and the data line driving circuit supplies a data signal to the data line.

  An FPC (Flexible Printed Circuit) substrate 36 and the like are attached on the element substrate 32. Various signals such as data signals and commands are supplied to the driver unit 35 by the FPC board 36.

  FIG. 1 shows a specific configuration of the driver unit 35 in FIG. In FIG. 1, it is assumed that the entire configuration of the driver unit 35 is provided on the element substrate 32 of FIG. 2, but only a part of the configuration is provided on the element substrate 32. May be adopted. For example, only the data line driving circuit 20 and the scanning line driving circuit 21 are provided on the element substrate 32, and other components are not mounted on the element substrate 32 by COG, but using TAB (Tape Automated Bonding) technology, It is good also as a structure which mounts on (Tape Carrier Package) and is electrically and mechanically connected by the anisotropic conductive film provided in the predetermined position of a board | substrate.

  In FIG. 1, the MPU 12 controls the entire driver unit 35. Display data and various commands are input to the MPU 12. The I / F control circuit 13 performs an interface between a signal input via the FPC board 36 and a signal handled in the electro-optical device 31. The command decoder 14 analyzes the input command and supplies a signal for performing control based on the analysis result to each unit. For example, the MPU 12 generates various control signals according to the input command and controls the VRAM control circuit 15 and the oscillation control circuit 17 and the like.

  The VRAM control circuit 15 has a VRAM (video memory) 16 and is controlled by the MPU 12 to store display data from the MPU 12 in the VRAM 16. Further, when displaying an image on the screen, the VRAM control circuit 15 reads display data from the VRAM 16 and supplies it to the data line driving circuit 20 via the data bus.

  The oscillation control circuit 17 includes a high frequency oscillation circuit 18 and a low frequency oscillation circuit 19 and is controlled by a command from the MPU 12 to generate a high frequency clock and a low frequency oscillation clock. The high frequency oscillation circuit 18 generates a high frequency clock, and the low frequency oscillation circuit 19 generates a low frequency clock. These high frequency clock and low frequency clock are supplied to the data line driving circuit 20 and the scanning line driving circuit 21.

  Power is supplied from the power control circuit 27 to the data line driving circuit 20 and the scanning line driving circuit 21. The display data read from the VRAM 16 is supplied to the data line driving circuit 20 and the scanning line driving circuit 21.

  The data line driving circuit 20 includes an LCD driving circuit 22, a PWM circuit 23, and a timing control circuit 24. The PWM circuit 23 performs PWM modulation on the input display data. The LCD drive circuit 22 supplies the display data subjected to PWM modulation to each corresponding data line. In this case, the LCD drive circuit 22 performs writing to the data line at a timing corresponding to the timing signal from the timing control circuit 24.

  The timing control circuit 24 generates various timing signals including horizontal and vertical synchronization signals based on the high-frequency clock and the low-frequency clock, and controls the LCD drive circuit 22 and the PWM circuit 23.

  The scanning line driving circuit 21 includes an LCD driving circuit 25 and a timing control circuit 26. The LCD drive circuit 25 generates a scanning signal and sequentially supplies it to each scanning line. In this case, the LCD driving circuit 25 generates a scanning signal to be supplied to each scanning line at a timing corresponding to the timing signal from the timing control circuit 26.

  The timing control circuit 26 generates various timing signals including horizontal and vertical synchronization signals based on the high frequency clock and the low frequency clock, and controls the LCD drive circuit 25.

  In the present embodiment, as will be described later, the frequencies of the high-frequency clock and the low-frequency clock are determined corresponding to the frame frequency based on the high-frequency clock. Accordingly, the frame frequencies defined by the timing signals of the timing control circuits 24 and 26 are the same when the high frequency clock is used and when the low frequency clock is used.

  FIG. 3 is a circuit diagram showing a specific configuration of the low-frequency oscillation circuit 19 in FIG.

  The example of FIG. 3 is an example applied to a three-stage CMOS oscillation circuit. The NAND circuit 43, the inverters 44 and 45, the capacitor C1, and the resistors R1 to R4 constitute an oscillation unit.

The output of the NAND circuit 43 is supplied to the inverter 44, and the output of the inverter 44 is fed back to one input terminal of the NAND circuit 43 via the capacitor C1. An output of the command control circuit 41 is given to the other input terminal of the NAND circuit 43. The output of the inverter 44 is also supplied to the inverter 45, and the output of the inverter 45 is fed back to one input terminal of the NAND circuit 43 through the feedback resistor group 47.

  A control signal from the MPU 12 is input to the command control circuit 41. The command control circuit 41 gives a high level (hereinafter referred to as “H”) signal to the other input terminal of the NAND circuit 43 when the control signal instructs the oscillation of the low frequency clock. As a result, the output of the NAND circuit 43 is supplied to the inverter 44 and the oscillation operation is started.

  The oscillation frequency of the low-frequency oscillation circuit 19 in FIG. 3 is determined by the resistance value of the feedback resistor group 47 and the capacitance of the capacitor C1. In the present embodiment, the selection circuit 42 can change the resistance value of the feedback resistor group 47.

  The feedback resistor group 47 has a plurality (four in FIG. 3) of resistors R1 to R4 connected in series to the output terminal of the inverter 45. Switches SW <b> 1 to SW <b> 4 are provided between the connection points of the resistors R <b> 1 to R <b> 4 and the end of the resistor R <b> 4 and one input end of the NAND circuit 43, respectively. The selection circuit 42 is supplied with the control signal from the command control circuit 41, and turns on one of the switches SW1 to SW4 and turns off the other switches based on the input control signal. Thereby, the resistance value of the feedback resistor group 47, that is, the resistance value between the output terminal of the inverter 45 and the input terminal of the NAND circuit 43 is based on the control signal supplied to the selection circuit 42.

  In the feedback type oscillation circuit shown in FIG. 3, the oscillation frequency is determined by the time delay of the feedback signal as described above. The resistance value of the feedback resistor group 47 is based on the control signal supplied to the selection circuit 42, and the oscillation frequency of the low frequency oscillation circuit 19 changes according to the control signal.

  In the present embodiment, the MPU 12 determines the oscillation frequency of the low frequency clock of the low frequency oscillation circuit 19 based on the oscillation frequency of the high frequency clock. In other words, the MPU 12 determines the oscillation frequency of the low frequency clock so that the frame period obtained using the low frequency clock matches the frame period obtained using the high frequency clock.

  Note that various methods can be employed as the oscillation circuit. Any type of oscillation circuit may be adopted as long as the oscillation frequency can be controlled by an external command.

  The low frequency oscillation circuit 19 and the high frequency oscillation circuit 18 are formed on the substrate by the same semiconductor process. That is, the resistors R1 to R4 of the feedback resistor group 47 are not external parts but are COG mounted. Therefore, the mounting area does not increase as in the case where a feedback resistor is mounted as an external component. Further, it is not necessary to consider the shape of the FPC or the like in order to arrange the feedback resistor, and the degree of design freedom can be improved.

  Further, the high frequency oscillation circuit 18 and the low frequency oscillation circuit 19 are formed at positions close to each other on the substrate. Thereby, device characteristics such as temperature characteristics can be substantially matched. Therefore, when one oscillation frequency fluctuates after the frequency adjustment by the selection circuit 42, the other oscillation frequency also fluctuates in accordance with this variation, and the frame periods can be relatively matched.

<Action>
Next, the operation of the embodiment configured as described above will be described with reference to FIGS. FIG. 4 is a timing chart for explaining the switching timing of clocks used in the data line driving circuit 20 and the scanning line driving circuit 21, and FIG. 5 explains the relationship between the high frequency clock and the low frequency clock in this embodiment. It is a timing chart for. FIG. 4 shows the oscillation period by hatching.

  In the present embodiment, in the display area 37 of the electro-optical device 31, image display by gradation display can be performed and binary image display can also be performed. Assume that gradation display is performed. Display data is supplied to the MPU 12. The MPU 12 transfers display data to the VRAM control circuit 15. The VRAM control circuit 15 stores the transferred display data in the VRAM 16. Further, the MPU 12 receives a command indicating that gradation display is performed, and outputs a control signal for causing the oscillation control circuit 17 to generate a high frequency clock.

  The oscillation control circuit 17 stops the operation of the low frequency oscillation circuit 19 and operates the high frequency oscillation circuit 18 to generate a high frequency clock. The low frequency oscillation circuit 19 stops oscillation by outputting a low level (hereinafter referred to as “L”) signal from the command control circuit 41.

  The high frequency oscillation circuit 18 generates a high frequency clock having a predetermined frequency and outputs it to the data line driving circuit 20 and the scanning line driving circuit 21. The data line driving circuit 20 and the scanning line driving circuit 21 generate various timing signals using the input high frequency clock. For example, as the timing signal, a horizontal synchronization signal, a vertical synchronization signal, or the like is generated. FIG. 4 shows an example of the vertical synchronization signal Vsync.

  On the other hand, the VRAM control circuit 15 reads the display data stored in the VRAM and outputs it to the data line driving circuit 20. The data line driving circuit 20 PWM modulates display data by the PWM circuit 23, and the LCD driving circuit 22 writes the modulated signal to the data line at the timing of the timing signal from the timing control circuit 24.

  In the scanning line driving circuit 21, the LCD driving circuit 25 writes the scanning signal to the scanning line at the timing of the timing signal from the timing control circuit 24. Thereby, each line of the display area 37 is sequentially selected, and each pixel is driven in accordance with a signal supplied from the data line. In this way, the liquid crystal transmittance is controlled for each pixel, and gradation display is performed.

  Here, it is assumed that binary image display is instructed instead of gradation display. For example, when the present embodiment is applied to a mobile phone or the like, a binary image display is instructed in a standby screen display mode or the like. When the MPU 12 receives a command to be set to the binary image display mode at the timing t0 in FIG. 4, the MPU 12 causes the VRAM control circuit 15 to read the display data for the binary image from the VRAM 16 and causes the oscillation control circuit 17 to Directs oscillation of the frequency clock.

  The oscillation control circuit 17 starts the low-frequency oscillation circuit 19 instead of the oscillation operation of the high-frequency oscillation circuit 18. That is, the oscillation control circuit 17 instructs the low-frequency oscillation circuit 19 to oscillate at the timing t1 in FIG. The command control circuit 41 of the low frequency oscillation circuit 19 supplies an “H” signal to the other input terminal of the NAND circuit 43 in accordance with the received control signal. As a result, the NAND circuit 43 starts to output the inverted output of the feedback signal from the capacitor C1 to the inverter 44, and oscillation is started.

  Further, the command control circuit 41 outputs a control signal for determining which of the switches SW1 to SW4 is selected to the selection circuit 42. The selection circuit 42 is controlled by the command control circuit 41 to turn on one of the switches SW1 to SW4. As a result, the resistance value of the feedback resistor group 47 is determined, and oscillation is performed at an oscillation frequency corresponding to the resistance value and the capacitance value of the capacitor C1. The oscillation output (low frequency clock) is output via a terminal 46.

  The low frequency clock from the low frequency oscillation circuit 19 is supplied to the timing control circuits 24 and 26 of the data line driving circuit 20 and the scanning line driving circuit 21. The timing control circuits 24 and 26 generate various timing signals using the inputted low frequency clock.

  In the present embodiment, the oscillation frequency of the low frequency clock from the low frequency oscillation circuit 19 corresponds to the oscillation frequency of the high frequency clock from the high frequency oscillation circuit 19. As a result, the timing signals generated in the timing control circuits 24 and 26 correspond to the timing signals generated when the high-frequency clock is used, and the frame periods coincide with each other.

  FIG. 5 shows an example of the relationship between the high frequency clock from the high frequency oscillation circuit 18 and the low frequency clock from the low frequency oscillation circuit 19. FIG. 5 shows an example in which the frequency ratio between the high frequency clock and the low frequency clock is set to a relatively small value in order to simplify the drawing.

  The example of FIG. 5 shows an example in which a low frequency clock is generated at a frequency that is 1/4 times the frequency of the high frequency clock. The frame period is set to 4n (n is a positive integer) times the period of the high-frequency clock. Thereby, the frame period based on the timing signal generated using the high-frequency clock can be matched with the frame period based on the timing signal generated using the low-frequency clock.

  Note that when this embodiment is applied to a display panel of a mobile phone, for example, the number of pixels is 320 × 240, and actually, a high frequency clock used for 64 gradation display is set to a frequency of about 10 MHz. The low frequency clock used for binary image display is set to a frequency of about 100 kHz.

  When the oscillation frequency of the low-frequency clock is stabilized, the MPU 12 stops the high-frequency clock and generates a timing signal using the low-frequency clock at timing t2 in FIG. Thus, the display mode is switched to the binary image display.

  As described above, in this embodiment, the clock to be used is switched between the high frequency clock and the low frequency clock according to the display mode. In this case, the frequency of the low frequency clock is set to a frequency corresponding to the frame period when the high frequency clock is used. Thereby, it is possible to prevent the display quality from changing according to the display mode. The frequency of the low frequency clock is adjusted by switching the resistance value of the resistor group formed on the substrate by a command. Since the frequency adjusting resistor is formed by a semiconductor process, an increase in the mounting area can be prevented, and the degree of freedom in design can be improved. Further, the resistance value can be adjusted by setting the command, and the adjustment work is simple. Further, the high-frequency oscillation circuit and the low-frequency oscillation circuit can be arranged at relatively close positions on the substrate, and the device characteristics can be matched. Thereby, even when the clock frequency fluctuates, the frame periods for the respective display modes can be relatively matched.

  In the above embodiment, the example of adjusting the oscillation frequency of the low frequency oscillation circuit has been described. Conversely, it is conceivable to adjust the oscillation frequency of the high-frequency oscillation circuit based on the oscillation frequency of the low-frequency oscillation circuit. However, the high frequency clock is based on the resolution of the display data and the like, and adjusting the frequency of the high frequency clock has an effect on these. Therefore, it is better to adjust the frequency on the low frequency clock side.

  In the above embodiment, the example in which the resistance value of the feedback resistor is controlled by the command has been described. However, the oscillation frequency can be controlled by changing the capacitance value of the feedback capacitor, and the capacitance of the feedback capacitor can be controlled by the command. May be controlled.

  The electro-optical device of the present invention is not limited to a passive matrix type liquid crystal display panel but an active matrix type liquid crystal panel (for example, a liquid crystal display panel including a TFT (thin film transistor) or a TFD (thin film diode) as a switching element). It is possible to apply to the same. In addition to liquid crystal display panels, electroluminescence devices, organic electroluminescence devices, plasma display devices, electrophoretic display devices, devices using electron emission (such as Field Emission Display and Surface-Conduction Electron-Emitter Display), DLP ( The present invention can be similarly applied to various electro-optical devices such as Digital Light Processing (aka DMD: Digital Micromirror Device). Furthermore, although the liquid crystal panel of the above embodiment has a so-called COF (Chip On Film) type structure, it may be a liquid crystal panel having a structure in which an IC chip is directly mounted.

1 is a block diagram illustrating a drive circuit of an electro-optical device according to an embodiment of the invention. The perspective view which shows roughly the whole structure of a liquid crystal display device. FIG. 2 is a circuit diagram showing a specific configuration of a low-frequency oscillation circuit 19 in FIG. 1. 6 is a timing chart for explaining switching timing of clocks used in the data line driving circuit 20 and the scanning line driving circuit 21. FIG. 4 is a timing chart for explaining a relationship between a high-frequency clock and a low-frequency clock in this embodiment.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 12 ... MPU, 15 ... VRAM control circuit, 17 ... oscillation control circuit, 18 ... high frequency oscillation circuit, 19 ... low frequency oscillation circuit, 20 ... data line drive circuit, 21 ... scan line drive circuit, 24,26 ... timing control circuit .

Claims (6)

A first oscillation circuit for generating a first clock for generating a timing signal for a first display mode;
A second oscillation circuit for generating a second clock for generating a timing signal for the second display mode, the second clock having a frequency lower than that of the first clock;
Adjusting means for adjusting a frequency of the second clock in accordance with a frame period defined by a timing signal based on the first clock based on a control signal;
A drive circuit for an electro-optical device. The second oscillation circuit has an oscillation frequency that varies depending on resistance and capacitance values.
2. The electro-optic according to claim 1, wherein the adjusting unit adjusts the frequency of the second clock by controlling at least one of the resistance and the capacitance based on the control signal. Device drive circuit.   The adjusting means adjusts the frequency of the second clock by controlling on and off a switch element for selecting one of a plurality of resistance values based on the control signal. The drive circuit for the electro-optical device according to claim 2. The first display mode is gradation display,
The electro-optical device drive circuit according to claim 1, wherein the second display mode is a binary image display. A drive circuit for an electro-optical device according to any one of claims 1 to 4,
A display area in which pixels are provided corresponding to intersections of a plurality of scanning lines and a plurality of data lines, and the pixels are driven by a driving circuit of the electro-optical device;
An electro-optical device comprising:   The electro-optical device according to claim 5, wherein the first and second oscillation circuits are configured on a substrate provided with the pixels.

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