JP2007088217A - Oscillation transistor and oscillation circuit - Google Patents

Oscillation transistor and oscillation circuit Download PDF

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JP2007088217A
JP2007088217A JP2005275377A JP2005275377A JP2007088217A JP 2007088217 A JP2007088217 A JP 2007088217A JP 2005275377 A JP2005275377 A JP 2005275377A JP 2005275377 A JP2005275377 A JP 2005275377A JP 2007088217 A JP2007088217 A JP 2007088217A
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transistor
oscillation
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Sadao Tanikoshi
貞夫 谷越
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Toshiba Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a several GHz band oscillation circuit that is improved in phase noise characteristics near an oscillation frequency by reducing mutual inductance between the base of an oscillation transistor and an emitter bonding wire. <P>SOLUTION: The oscillation circuit is equipped with a first bonding wire 15 that connects the base of the oscillation transistor to a base terminal 12, and a second bonding wire 16 that connects the emitter of the oscillation transistor to an emitter terminal 13. The wiring direction of the base terminal 12 crosses that of the emitter terminal 13 at a right angle, and also the wiring direction of the first bonding wire 15 crosses that of the second bonding wire 16 at a right angle. A magnetic shielding material may be inserted between the bonding wires 15 and 16 or between the base terminal 12 and the emitter terminal 13. Mutual inductance between the bonding wires 15 and 16 can be reduced so as to obtain an oscillation circuit excellent in phase noise characteristics near an oscillation frequency. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

数ギガヘルツ帯の発振回路において使用され、発振周波数近傍における位相雑音特性を改善する発振回路用トランジスタ及び発振回路に関するものである。   The present invention relates to an oscillation circuit transistor and an oscillation circuit that are used in an oscillation circuit of several gigahertz band and improve phase noise characteristics in the vicinity of an oscillation frequency.

従来の高周波用発振回路の構成例の１例は、共振回路部、負性抵抗回路部及びバッファ回路部から構成されている。負性抵抗回路部のバイポーラトランジスタは、発振トランジスタであり、入力インピーダンスが負性を示すように、ベース・エミッタ間及びエミッタ・接地間にコンデンサ等が付加されている。共振回路部と負性抵抗回路部とで発振回路部を構成する。
この共振回路部は、インダクタ及び可変容量ダイオードから構成され、可変容量ダイオードへの印加電圧で共振周波数が可変となっており、電圧制御発振回路を構成する。発振トランジスタのコレクタは、コンデンサを介して交流的に接地されており、発振トランジスタのベースから見た入力インピーダンスが負性となり、この入力インピーダンスの実数部が発振トランジスタのベースから見た共振回路のインピーダンスの実数部より大きい場合発振が起こる。
バッファ回路部は、発振トランジスタとカスコード接続されたベース接地トランジスタ（バッファトランジスタ）で構成されている。バッファ回路部は、発振回路の負荷インピーダンスに対する安定性を改善する目的で設けられている。すなわち、発振回路の負荷インピーダンス変動が発振周波数変動や位相雑音特性の劣化を引き起こす。バッファ回路部により発振回路部が負荷から隔離され、発振周波数変動や位相雑音特性の劣化が改善される。 One example of a configuration example of a conventional high-frequency oscillation circuit includes a resonance circuit unit, a negative resistance circuit unit, and a buffer circuit unit. The bipolar transistor of the negative resistance circuit section is an oscillation transistor, and a capacitor or the like is added between the base and the emitter and between the emitter and the ground so that the input impedance is negative. The resonance circuit unit and the negative resistance circuit unit constitute an oscillation circuit unit.
This resonance circuit unit is composed of an inductor and a variable capacitance diode, and the resonance frequency is variable by the voltage applied to the variable capacitance diode, and constitutes a voltage controlled oscillation circuit. The collector of the oscillation transistor is AC-grounded via a capacitor, and the input impedance viewed from the base of the oscillation transistor is negative. The real part of this input impedance is the impedance of the resonance circuit viewed from the base of the oscillation transistor. If it is larger than the real part, oscillation occurs.
The buffer circuit section is composed of a grounded base transistor (buffer transistor) that is cascode-connected to the oscillation transistor. The buffer circuit section is provided for the purpose of improving the stability against the load impedance of the oscillation circuit. That is, fluctuations in the load impedance of the oscillation circuit cause fluctuations in oscillation frequency and phase noise characteristics. The oscillation circuit unit is isolated from the load by the buffer circuit unit, and oscillation frequency fluctuations and phase noise characteristic degradation are improved.

発振トランジスタのパッケージ構造は、バッファトランジスタとは独立のパッケージのトランジスタを用いた場合と、実装スペース削減のために１つのパッケージに２つのトランジスタを搭載する場合がある。
発振トランジスタのベースとエミッタのボンディングワイヤは隣接しており、しかもほぼ平行に配置されている。このため両ボンディングワイヤ間の相互インダクタンス又は誘導結合は無視できない値となっており、このような誘導結合あるいは相互インダクタンスを低減したトランジスタあるいはパッケージ構造が必要となっている。
従来技術として特許文献１には半導体基板に発振用トランジスタ素子とバッファアンプ用トランジスタ素子とを形成して１チップ化することによりダイパッドを１つとし、ダイパッド面積と外部端子数が削減されて小型化された表面実装型モールドパッケージ半導体装置及びこの半導体装置を適用した発振器が記載されている。
特開２００３−１６３２１７号公報 As the package structure of the oscillation transistor, there are a case where a transistor of a package independent from the buffer transistor is used and a case where two transistors are mounted in one package in order to reduce mounting space.
The base and emitter bonding wires of the oscillation transistor are adjacent to each other, and are arranged substantially in parallel. For this reason, the mutual inductance or inductive coupling between the bonding wires is a value that cannot be ignored, and a transistor or package structure in which such inductive coupling or mutual inductance is reduced is required.
As a conventional technique, Patent Document 1 discloses that an oscillation transistor element and a buffer amplifier transistor element are formed on a semiconductor substrate to form one chip, thereby reducing the die pad area and the number of external terminals, thereby reducing the size. A surface mounted mold package semiconductor device and an oscillator to which the semiconductor device is applied are described.
JP 2003-163217 A

本発明は、ベース部のボンディングワイヤとエミッタ部のボンディングワイヤ間の相互インダクタンスを低減することにより、数ギガヘルツ帯の発振回路において使用される発振トランジスタ及び発振周波数近傍における位相雑音特性の良好な発振回路を提供する。   The present invention reduces the mutual inductance between the bonding wire of the base part and the bonding wire of the emitter part, and thereby the oscillation transistor used in the oscillation circuit of several gigahertz band and the oscillation circuit having a good phase noise characteristic in the vicinity of the oscillation frequency I will provide a.

本発明の発振トランジスタの一態様は、発振トランジスタと、ベース端子と、エミッタ端子と、前記発振トランジスタのベースと前記ベース端子とを接続する第１のボンディングワイヤと、前記発振トランジスタのエミッタと前記エミッタ端子とを接続する第２のボンディングワイヤと、前記発振トランジスタ、前記ベース端子の一部、前記エミッタ端子の一部、前記第１及び第２のボンディングワイヤを封止するパッケージとを備え、前記ベース端子と前記エミッタ端子の配線方向が直角であり、且つ前記第１及び第２のボンディングワイヤの配線方向が直角であることを特徴としている。   One aspect of the oscillation transistor of the present invention includes an oscillation transistor, a base terminal, an emitter terminal, a first bonding wire connecting the base of the oscillation transistor and the base terminal, the emitter of the oscillation transistor, and the emitter. A second bonding wire for connecting a terminal; and a package for sealing the oscillation transistor, a part of the base terminal, a part of the emitter terminal, and the first and second bonding wires. The wiring direction of the terminal and the emitter terminal is a right angle, and the wiring direction of the first and second bonding wires is a right angle.

また、本発明の発振トランジスタの一態様は、発振トランジスタと、ベース端子と、エミッタ端子と、前記発振トランジスタのベースと前記ベース端子とを接続する第１のボンディングワイヤと、前記発振トランジスタのエミッタと前記エミッタ端子とを接続する第２のボンディングワイヤと、前記発振トランジスタ、前記ベース端子の一部、前記エミッタ端子の一部、前記第１及び第２のボンディングワイヤを封止するパッケージとを備え、前記パッケージ内において、前記ベース端子と前記エミッタ端子との間又は前記第１及び第２のボンディングワイヤの間もしくは前記ベース端子と前記エミッタ端子との間及び前記第１及び第２のボンディングワイヤの間に磁気シールド材を挿入したことを特徴としている。
本発明の発振回路の一態様は、発振周波数を設定する共振回路部と、発振トランジスタである第１のトランジスタを含み入力抵抗が負性を示す負性抵抗回路部と、第２のトランジスタを含み前記負性抵抗回路部の出力信号を増幅して出力するバッファ回路部とを備え、前記第１のトランジスタと前記第２のトランジスタは同一パッケージ内に組み込まれ、前記パッケージ内において、前記第１のトランジスタのベースとベース端子とを接続する第１のボンディングワイヤの配置方向と、前記第１のトランジスタのエミッタとエミッタ端子とを接続する第２のボンディングワイヤの配置方向とが直角であることを特徴としている。 An aspect of the oscillation transistor of the present invention includes an oscillation transistor, a base terminal, an emitter terminal, a first bonding wire connecting the base of the oscillation transistor and the base terminal, an emitter of the oscillation transistor, A second bonding wire for connecting to the emitter terminal; a package for sealing the oscillation transistor, a part of the base terminal, a part of the emitter terminal, and the first and second bonding wires; Within the package, between the base terminal and the emitter terminal, between the first and second bonding wires, or between the base terminal and the emitter terminal, and between the first and second bonding wires. It is characterized by inserting a magnetic shield material into the.
One aspect of the oscillation circuit of the present invention includes a resonance circuit section that sets an oscillation frequency, a negative resistance circuit section that includes a first transistor that is an oscillation transistor, and has negative input resistance, and a second transistor. A buffer circuit section that amplifies and outputs an output signal of the negative resistance circuit section, and the first transistor and the second transistor are incorporated in the same package, and the first transistor The arrangement direction of the first bonding wire connecting the base and base terminal of the transistor is perpendicular to the arrangement direction of the second bonding wire connecting the emitter and emitter terminal of the first transistor. It is said.

また、本発明の発振回路の一態様は、発振周波数を設定する共振回路部と、発振トランジスタである第１のトランジスタを含み入力抵抗が負性を示す負性抵抗回路部と、第２のトランジスタを含み前記負性抵抗回路部の出力信号を増幅して出力するバッファ回路部とを備え、前記第１のトランジスタと前記第２のトランジスタは同一パッケージ内に組み込まれ、前記パッケージ内において、前記第１のトランジスタのベースとベース端子とを接続する第１のボンディングワイヤと、前記第１のトランジスタのエミッタとエミッタ端子とを接続する第２のボンディングワイヤの中間及び前記ベース端子と前記エミッタ端子との中間に磁気シールド材を挿入することを特徴としている。   Further, according to one aspect of the oscillation circuit of the present invention, a resonance circuit section that sets an oscillation frequency, a negative resistance circuit section that includes a first transistor that is an oscillation transistor and has negative input resistance, and a second transistor A buffer circuit unit that amplifies and outputs an output signal of the negative resistance circuit unit, and the first transistor and the second transistor are incorporated in the same package, and the first transistor and the second transistor are incorporated in the package. A first bonding wire that connects a base and a base terminal of one transistor, a middle of a second bonding wire that connects an emitter and an emitter terminal of the first transistor, and the base terminal and the emitter terminal It is characterized by inserting a magnetic shield material in the middle.

ベース部のボンディングワイヤとエミッタ部のボンディングワイヤ間の相互インダクタンスを低減することにより数ギガヘルツ帯の発振回路において使用される発振トランジスタが得られ、発振周波数近傍における位相雑音特性の良好な発振回路が得られる。   By reducing the mutual inductance between the bonding wire of the base part and the bonding wire of the emitter part, an oscillation transistor used in an oscillation circuit of several gigahertz band is obtained, and an oscillation circuit with good phase noise characteristics near the oscillation frequency is obtained. It is done.

以下、実施例を参照して発明の実施の形態を説明する。   Hereinafter, embodiments of the invention will be described with reference to examples.

図１乃至図８を参照して実施例１を説明する。図１は、この実施例の発振トランジスタの樹脂封止体（パッケージ）内部を透過した概略平面図及びこのトランジスタの回路図、図２は、図１のパッケージに組み込まれるチップの概略断面図、図３は、図１のトランジスタが組み込まれた発振回路の回路図、図４は、２つの回路Ｃ１・Ｃ２間の相互インダクタンスを求める式（ノイマンの公式）の説明図、図５は、平行導体間の相互インダクタンスを求める式の説明図、図６は、２つの回路Ｃ１・Ｃ２間の相互インダクタンスを求めるノイマンの公式を示す図、図７は、ボンディングワイヤ間の誘導結合による発振回路の位相雑音特性に及ぼす影響を説明する発振トランジスタ（比較例）の平面図及び回路図、図８は、発振トランジスタのパッケージ内部のベース側ボンディングワイヤとエミッタ側ボンディングワイヤ間の相互インダクタンスを変化させた場合の発振出力信号の位相雑音特性（Ｃ／Ｎ（信号対位相雑音）比）の計算値を示す特性図である。   A first embodiment will be described with reference to FIGS. 1 is a schematic plan view showing the inside of a resin sealing body (package) of the oscillation transistor of this embodiment and a circuit diagram of the transistor. FIG. 2 is a schematic cross-sectional view of a chip incorporated in the package of FIG. 3 is a circuit diagram of an oscillation circuit incorporating the transistor of FIG. 1, FIG. 4 is an explanatory diagram of an equation (Neumann's formula) for obtaining a mutual inductance between the two circuits C1 and C2, and FIG. FIG. 6 is a diagram showing Neumann's formula for obtaining the mutual inductance between the two circuits C1 and C2, and FIG. 7 is a phase noise characteristic of the oscillation circuit due to inductive coupling between the bonding wires. FIG. 8 is a plan view and a circuit diagram of an oscillation transistor (comparative example) for explaining the influence on the base, and FIG. Tsu is a characteristic diagram showing the calculated values of the phase noise characteristics of the oscillation output signal (C / N (signal-to-phase noise) ratio) varying the mutual inductance between the other side a bonding wire.

まず、図４乃至図８を参照して、トランジスタのベースとエミッタのボンディングワイヤ間の誘導結合による発振回路の位相雑音特性に及ぼす影響について考察する。
図４に示す回路Ｃ１・Ｃ２間の相互インダクタンスＭ12［ヘンリー］は、図６のノイマンの公式（１）から計算される。この公式（１）において、ｒは、回路Ｃ１・Ｃ２の線要素ｄs1・ｄs2間の距離、θは、両要素の方向の間の角度である。例えば、図５に示す平行導体間（ｃｏｓθ＝１）の相互インダクタンスＭは、（１）式の積分を実行して、図６の（２）式で表される。ここで、μは、透磁率であり、ｌは、線の長さであり、ｄは、２本の導体間距離である。 First, the influence of the inductive coupling between the transistor base and emitter bonding wires on the phase noise characteristics of the oscillation circuit will be discussed with reference to FIGS.
The mutual inductance M 12 [Henry] between the circuits C1 and C2 shown in FIG. 4 is calculated from the Neumann formula (1) in FIG. In this formula (1), r is the distance between the line elements d s1 and d s2 of the circuits C1 and C2, and θ is the angle between the directions of both elements. For example, the mutual inductance M between the parallel conductors (cos θ = 1) shown in FIG. 5 is expressed by the equation (2) in FIG. 6 by performing the integration of the equation (1). Here, μ is the magnetic permeability, l is the length of the line, and d is the distance between the two conductors.

（２）式をトランジスタパッケージ内のボンディングワイヤにあてはめて相互インダクタンスを計算すると、ボンディングワイヤの長さｌ＝０．８ｍｍ、２本のボンディングワイヤ間の距離ｄ＝０．２ｍｍの時、Ｍ＝０．２１ｎＨ（ナノヘンリー）となる。但し（２）式は、２本のワイヤが直線、且つ平行に配置された場合に当てはまるが、実際にはボンディングワイヤは円弧状に曲がっているため、実際の相互インダクタンス値は一般的に（２）式から算出される値より大きくなる。ボンディングワイヤの長さや２本のボンディングワイヤ間の距離の変動も考慮すると、トランジスタパッケージ内の隣り合ったボンディングワイヤ同士の相互インダクタンス値は、０．１〜０．３ｎＨ程度になると考えられる。
また、２本のボンディングワイヤを直交させて配置した場合、（１）式においてｃｏｓθ＝０となるため、相互インダクタンスＭは零となる。 When the equation (2) is applied to the bonding wire in the transistor package to calculate the mutual inductance, when the length of the bonding wire l = 0.8 mm and the distance d between the two bonding wires d = 0.2 mm, M = 0 .21 nH (nanohenry). However, although the expression (2) is true when two wires are arranged in a straight line and in parallel, since the bonding wire is actually bent in an arc shape, the actual mutual inductance value is generally (2 ) Larger than the value calculated from the equation. Considering the variation of the length of the bonding wire and the distance between the two bonding wires, the mutual inductance value between adjacent bonding wires in the transistor package is considered to be about 0.1 to 0.3 nH.
In addition, when two bonding wires are arranged orthogonally, cos θ = 0 in equation (1), so that the mutual inductance M becomes zero.

次に、この誘導結合が発振回路特性に与える影響を図７及び図８を参照しながら考察する。図７は、ボンディングワイヤ間の相互インダクタンスの影響を考慮しない発振トランジスタ（比較例）のパッケージ構造の概略平面図及び発振トランジスタの回路図である。図において、発振トランジスタを封止するエポキシ樹脂封止体などのパッケージ５０は、コレクタ、ベース、エミッタなどの外部端子５１、５２、５３を一端を除いて封止している。コレクタ端子５１には発振トランジスタを構成するトランジスタチップ５４が接合され、トランジスタチップ５４からベース端子５２及びエミッタ端子５３へはそれぞれボンディングワイヤ５５、５６が接続されている。トランジスタチップ５４及びボンディングワイヤ５５、５６は、共にパッケージ５０に封止されている。
発振周波数ｆosc ＝２ＧＨｚ、ボンディングワイヤ５５、５６の自己インダクタンスを各々０．５ｎＨとした場合、相互インダクタンスを変化させた時の位相雑音特性（Ｃ／Ｎ）を図８に示す。 Next, the effect of this inductive coupling on the oscillation circuit characteristics will be considered with reference to FIGS. FIG. 7 is a schematic plan view of a package structure of an oscillation transistor (comparative example) that does not consider the influence of mutual inductance between bonding wires and a circuit diagram of the oscillation transistor. In the figure, a package 50 such as an epoxy resin sealing body that seals an oscillation transistor seals external terminals 51, 52, and 53 such as a collector, a base, and an emitter except for one end. A transistor chip 54 constituting an oscillation transistor is joined to the collector terminal 51, and bonding wires 55 and 56 are connected from the transistor chip 54 to the base terminal 52 and the emitter terminal 53, respectively. Both the transistor chip 54 and the bonding wires 55 and 56 are sealed in the package 50.
FIG. 8 shows the phase noise characteristics (C / N) when the mutual inductance is changed when the oscillation frequency f osc = 2 GHz and the self-inductances of the bonding wires 55 and 56 are 0.5 nH, respectively.

上の例では相互インダクタンスが０の場合の信号対位相雑音電力比（Ｃ／Ｎ）は１１７．２５ｄＢｃであるが、相互インダクタンスＭが大きくなるに従いＣ／Ｎは、劣化し、Ｍ＝０．３ｎＨとすると１１５ｄＢｃとなり、無視できない劣化量となる。
このように、発振トランジスタのベースとエミッタのボンディングワイヤ間の誘導結合により発振回路の位相雑音特性が大きく劣化するため、誘導結合あるいは相互インダクタンスを低減したトランジスタあるいはパッケージ構造が必要となる。 In the above example, the signal-to-phase noise power ratio (C / N) when the mutual inductance is 0 is 117.25 dBc. However, as the mutual inductance M increases, the C / N deteriorates, and M = 0.3 nH Then, it becomes 115 dBc, which is a non-negligible deterioration amount.
As described above, inductive coupling between the base and emitter bonding wires of the oscillation transistor greatly deteriorates the phase noise characteristic of the oscillation circuit, so that a transistor or package structure with reduced inductive coupling or mutual inductance is required.

次に、図１乃至図３を参照してこの実施例の発振トランジスタを説明する。この発振トランジスタは、図３に示す発振回路の共振回路部を構成する負性抵抗回路部内のトランジスタＱ２に用いられる。発振回路は、発振周波数を設定する共振回路部及び入力抵抗が負性を示す負性抵抗回路部から構成された発振回路部と、前記負性抵抗回路部の出力信号を増幅して出力するバッファ回路部とからなる。負性抵抗回路部は、発振トランジスタＱ２を備え、一端が発振トランジスタＱ２のベースＢに接続され、他端が共振回路部につながるコンデンサ素子Ｃ３と、一端が発振トランジスタＱ２のエミッタＥに接続され、他端が接地されたコンデンサ素子Ｃ５と、一端が発振トランジスタＱ２のベースＢ／コンデンサ素子Ｃ３間に接続され、他端が発振トランジスタＱ２のエミッタＥ／コンデンサ素子Ｃ５間に接続れたコンデンサ素子Ｃ４と、一端が発振トランジスタＱ２のエミッタＥ／コンデンサ素子Ｃ５間に接続れたコイルＬ３と、一端がコイルＬ３に接続され、他端が接地された抵抗素子Ｒ４と、一端が発振トランジスタＱ２のベースＢ／コンデンサ素子Ｃ３間に接続され、他端が接地された抵抗素子Ｒ１とを備えている。   Next, the oscillation transistor of this embodiment will be described with reference to FIGS. This oscillating transistor is used as the transistor Q2 in the negative resistance circuit part that constitutes the resonant circuit part of the oscillating circuit shown in FIG. An oscillation circuit includes an oscillation circuit unit including a resonance circuit unit for setting an oscillation frequency and a negative resistance circuit unit whose input resistance is negative, and a buffer for amplifying and outputting an output signal of the negative resistance circuit unit It consists of a circuit part. The negative resistance circuit section includes an oscillation transistor Q2, one end connected to the base B of the oscillation transistor Q2, the other end connected to the capacitor element C3 connected to the resonance circuit section, and one end connected to the emitter E of the oscillation transistor Q2. A capacitor element C5 having the other end grounded, and a capacitor element C4 having one end connected between the base B / capacitor element C3 of the oscillation transistor Q2 and the other end connected between the emitter E / capacitor element C5 of the oscillation transistor Q2. A coil L3 having one end connected between the emitter E / capacitor element C5 of the oscillation transistor Q2, a resistance element R4 having one end connected to the coil L3 and the other end grounded, and one end being the base B / of the oscillation transistor Q2. And a resistor element R1 connected between the capacitor elements C3 and having the other end grounded.

共振回路部は、入力Ｖtuneと、入力Ｖtuneと前記負性抵抗回路部のコンデンサ素子Ｃ３との間に接続されたコイルＬ１と、一端が入力Ｖtune／コイルＬ１間に接続され、他端が接地されたコンデンサ素子Ｃ１と、一端がコイルＬ１／コンデンサ素子Ｃ３間に接続され、他端が接地されたコンデンサ素子Ｃ２と、一端がコイルＬ１／コンデンサ素子Ｃ３間に接続されたダイオードＤ１と、一端がダイオードＤ１の他端に接続され、他端が接地されたコイルＬ２とを備えている。   The resonance circuit section includes an input Vtune, a coil L1 connected between the input Vtune and the capacitor element C3 of the negative resistance circuit section, one end connected between the input Vtune / coil L1, and the other end grounded. The capacitor element C1, one end connected between the coil L1 / capacitor element C3, the other end grounded, the diode D1 connected at one end between the coil L1 / capacitor element C3, and one end a diode A coil L2 connected to the other end of D1 and grounded at the other end.

バッファ回路部は、負性抵抗回路部の出力信号を増幅して出力するトランジスタＱ１を備え、一端がバッファトランジスタＱ１のベースＢに接続され、他端が接地されたコンデンサ素子Ｃ９と、一端がバッファトランジスタＱ１のエミッタＥと発振トランジスタＱ２のコレクタＣとの間に接続され、他端が接地されたコンデンサ素子Ｃ６と、一端がコンデンサ素子Ｃ３と発振トランジスタＱ２のベースＢとの間に接続され、他端がバッファトランジスタＱ１のベースＢとコンデンサ素子Ｃ９との間に接続された抵抗素子Ｒ２と、一端が電源Ｖccに接続され、他端が接地されたコンデンサ素子Ｃ８と、一端が電源Ｖdd／コンデンサ素子Ｃ８間に接続され、他端がバッファトランジスタＱ１のベースＢとコンデンサ素子Ｃ９との間に接続された抵抗素子Ｒ３と、一端が電源Ｖdd／コンデンサ素子Ｃ８間に接続され、他端がバッファトランジスタＱ１のコレクタＣに接続されたコイルＬ４と、出力Ｖout と、一端が出力に接続され、他端がバッファトランジスタＱ１のコレクタＣに接続されたコンデンサ素子７とを備えている。   The buffer circuit section includes a transistor Q1 that amplifies and outputs the output signal of the negative resistance circuit section, one end of which is connected to the base B of the buffer transistor Q1, the other end is grounded, and one end is a buffer. The capacitor element C6 is connected between the emitter E of the transistor Q1 and the collector C of the oscillation transistor Q2, the other end is grounded, and one end is connected between the capacitor element C3 and the base B of the oscillation transistor Q2. A resistor element R2 having one end connected between the base B of the buffer transistor Q1 and the capacitor element C9, a capacitor element C8 having one end connected to the power source Vcc and the other end grounded, and one end being the power source Vdd / capacitor element A resistor connected between C8 and having the other end connected between the base B of the buffer transistor Q1 and the capacitor element C9 The element R3, one end connected between the power supply Vdd / capacitor element C8, the other end connected to the collector C of the buffer transistor Q1, the output Vout, one end connected to the output, and the other end to the buffer transistor And a capacitor element 7 connected to the collector C of Q1.

図１及び図２に示すバッファトランジスタは、図３に示す発振回路の発振トランジスタＱ２に適用されている。図２のトランジスタは、図１のトランジスタの一例である。図２に示すように、発振トランジスタが形成されたチップ１４にはコレクタ１、ベース２、エミッタ３が形成されている。例えば、エポキシ樹脂などの樹脂封止体からなるパッケージ１０内には、一端がパッケージ１０から一部露出したコレクタ端子１１、ベース端子１２及びエミッタ端子１３などの外部端子が設けられている。コレクタ端子１１には裏面がコレクタ１であるチップ１４が接合されており、ベース端子（Ｂ）１２及びエミッタ端子（Ｅ）１３とチップ１４内のベース２及びエミッタ３とは、それぞれボンディングワイヤ１５、１６により接合されている。ベース端子１２及びエミッタ端子１３の配置方向は互いに直交するように配置されており、同様にボンディングワイヤ１５、１６も互いに配線方向が直交するように配置されている。   The buffer transistor shown in FIGS. 1 and 2 is applied to the oscillation transistor Q2 of the oscillation circuit shown in FIG. The transistor in FIG. 2 is an example of the transistor in FIG. As shown in FIG. 2, a collector 1, a base 2, and an emitter 3 are formed on a chip 14 on which an oscillation transistor is formed. For example, an external terminal such as a collector terminal 11, a base terminal 12, and an emitter terminal 13 whose one end is partially exposed from the package 10 is provided in a package 10 made of a resin sealing body such as an epoxy resin. A chip 14 whose back surface is the collector 1 is joined to the collector terminal 11, and the base terminal (B) 12 and the emitter terminal (E) 13 and the base 2 and the emitter 3 in the chip 14 are respectively connected to the bonding wire 15, 16 is joined. The arrangement directions of the base terminal 12 and the emitter terminal 13 are arranged so as to be orthogonal to each other. Similarly, the bonding wires 15 and 16 are arranged so that the wiring directions are orthogonal to each other.

パッケージ内の外部端子及びボンディングワイヤがこのように配置されているので前述の理由から相互インダクンスが０もしくはそれに近い値となり、信号対位相雑音電力比（Ｃ／Ｎ）の劣化量が著しく減少する。   Since the external terminals and the bonding wires in the package are arranged in this way, the mutual inductance becomes 0 or a value close to it for the above-mentioned reason, and the deterioration amount of the signal-to-phase noise power ratio (C / N) is remarkably reduced.

次に、図９を参照して実施例２を説明する。
図９は、この実施例の発振トランジスタ及び他のバッファトランジスタを１つのパッケージ内部に収納した半導体装置の概略平面図及びパッケージ内のトランジスタの回路図である。この発振トランジスタは、図３に示す発振回路の共振回路部を構成する負性抵抗回路部内のトランジスタＱ２に用いられる。発振回路は、発振周波数を設定する共振回路部及び入力抵抗が負性を示す負性抵抗回路部から構成された発振回路部と、前記負性抵抗回路部の出力信号を増幅して出力するバッファ回路部とからなる。この実施例のパッケージは、発振トランジスタＱ２と共にバッファ回路部のバッファトランジスタＱ１もパッケージングされている。 Next, Embodiment 2 will be described with reference to FIG.
FIG. 9 is a schematic plan view of a semiconductor device in which the oscillation transistor and other buffer transistors of this embodiment are housed in one package, and a circuit diagram of the transistors in the package. This oscillating transistor is used as the transistor Q2 in the negative resistance circuit part that constitutes the resonant circuit part of the oscillating circuit shown in FIG. An oscillation circuit includes an oscillation circuit unit configured by a resonance circuit unit that sets an oscillation frequency and a negative resistance circuit unit whose input resistance is negative, and a buffer that amplifies and outputs an output signal of the negative resistance circuit unit It consists of a circuit part. In the package of this embodiment, the buffer transistor Q1 of the buffer circuit portion is packaged together with the oscillation transistor Q2.

例えば、エポキシ樹脂などの樹脂封止体からなるパッケージ２０内には発振トランジスタ（Ｑ２）及びバッファトランジスタ（Ｑ１）が形成されたチップ２４、２４′が収納されている。パッケージ２０内には、一端がパッケージから一部露出したコレクタ端子２１、ベース端子２２及びエミッタ端子２３などの外部端子が設けられている。コレクタ端子２１（Ｃ２）には裏面がコレクタであるチップ２４が接合されており、ベース端子（Ｂ２）２２及びエミッタ端子（Ｅ２）２３とチップ２４内のベース及びエミッタとは、それぞれボンディングワイヤ２５、２６により接合されている。ベース端子２２及びエミッタ端子２３の配置方向は互いに平行するように配置されているが、ボンディングワイヤ２５、２６は互いに配線方向が直交するように配置されている。以上が発振トランジスタＱ２のパッケージ２０内の配置である。   For example, in a package 20 made of a resin sealing body such as an epoxy resin, chips 24 and 24 'on which an oscillation transistor (Q2) and a buffer transistor (Q1) are formed are housed. In the package 20, external terminals such as a collector terminal 21, a base terminal 22, and an emitter terminal 23 that are partially exposed from the package are provided. The collector terminal 21 (C2) is joined with a chip 24 whose back surface is a collector, and the base terminal (B2) 22 and emitter terminal (E2) 23 and the base and emitter in the chip 24 are respectively connected to a bonding wire 25, 26 is joined. Although the arrangement directions of the base terminal 22 and the emitter terminal 23 are arranged in parallel to each other, the bonding wires 25 and 26 are arranged so that the wiring directions are orthogonal to each other. The above is the arrangement of the oscillation transistor Q2 in the package 20.

一方、パッケージ２０内には、バッファトランジスタＱ１も収納されている。一端がパッケージから一部露出したコレクタ端子２１′、ベース端子２２′及びエミッタ端子２３′などの外部端子が設けられている。コレクタ端子（Ｃ１）２１′には裏面がコレクタであるチップ２４′が接合されており、ベース端子（Ｂ１）２２′及びエミッタ端子（Ｅ１）２３′とチップ２４′内のベース及びエミッタとは、それぞれボンディングワイヤ２５′、２６′により接合されている。ベース端子２２′及びエミッタ端子２３′の配置方向は特に規定されていない。ボンディングワイヤ２５′、２６′の配線方向も特に限定されていない。
パッケージ内の発振トランジスタのボンディングワイヤが以上のように配置されているので前述の理由からその部分の相互インダクンスが０もしくはそれに近い値となり、信号対位相雑音電力比（Ｃ／Ｎ）の劣化量が著しく減少する。 On the other hand, a buffer transistor Q1 is also accommodated in the package 20. External terminals such as a collector terminal 21 ', a base terminal 22', and an emitter terminal 23 ', one end of which is partially exposed from the package, are provided. The collector terminal (C1) 21 ′ is joined to a chip 24 ′ whose collector is the back surface. The base terminal (B1) 22 ′ and the emitter terminal (E1) 23 ′ and the base and emitter in the chip 24 ′ are They are joined by bonding wires 25 'and 26', respectively. The arrangement direction of the base terminal 22 'and the emitter terminal 23' is not particularly defined. The wiring direction of the bonding wires 25 'and 26' is not particularly limited.
Since the bonding wires of the oscillation transistors in the package are arranged as described above, the mutual inductance of the portion becomes 0 or a value close to it for the above-mentioned reason, and the deterioration amount of the signal-to-phase noise power ratio (C / N) is reduced. Remarkably reduced.

次に、図１０及び図１１を参照して実施例３を説明する。
図１０は、この実施例の発振トランジスタをパッケージ内部に収納した半導体装置の概略平面図及びパッケージ内のトランジスタ（図３のＱ２に相当する）の回路図、図１１は、図１０に示す半導体装置の斜視図である。
この発振トランジスタは、図３に示す発振回路の共振回路部を構成する負性抵抗回路部内のトランジスタＱ２に用いられる。発振回路は、発振周波数を設定する共振回路部及び入力抵抗が負性を示す負性抵抗回路部から構成された発振回路部と、前記負性抵抗回路部の出力信号を増幅して出力するバッファ回路部とからなる。例えば、エポキシ樹脂などの樹脂封止体からなるパッケージ２０内には発振トランジスタ（Ｑ２）が形成されたチップ３４が収納されている。 Next, Embodiment 3 will be described with reference to FIGS. 10 and 11.
10 is a schematic plan view of a semiconductor device in which the oscillation transistor of this embodiment is housed in a package, and a circuit diagram of a transistor (corresponding to Q2 in FIG. 3) in the package. FIG. 11 is a semiconductor device shown in FIG. FIG.
This oscillating transistor is used as the transistor Q2 in the negative resistance circuit part that constitutes the resonant circuit part of the oscillating circuit shown in FIG. An oscillation circuit includes an oscillation circuit unit including a resonance circuit unit for setting an oscillation frequency and a negative resistance circuit unit whose input resistance is negative, and a buffer for amplifying and outputting an output signal of the negative resistance circuit unit It consists of a circuit part. For example, a chip 34 in which an oscillation transistor (Q2) is formed is housed in a package 20 made of a resin sealing body such as an epoxy resin.

発振トランジスタは、例えば、エポキシ樹脂などの樹脂封止体からなるパッケージ３０内に形成され、パッケージ３０内には一端がパッケージ３０から一部露出したコレクタ端子３１、ベース端子３２及びエミッタ端子３３などの外部端子が設けられている。コレクタ端子３１には裏面がコレクタであるチップ３４が接合されており、ベース端子（Ｂ）３２及びエミッタ端子（Ｅ）３３とチップ３４内のベース及びエミッタとは、それぞれボンディングワイヤ３５、３６により接合されている。パッケージ３０内のベースのボンディングワイヤ３５とエミッタのボンディングワイヤ３６の中間に磁気シールド材３７を挿入する。これを挿入することにより、ボンディングワイヤ間の誘導結合を阻止し相互インダクタンスが低減される。磁気シールド材３７としては鉄などの金属磁性体や樹脂状の電波吸収体などを用いることができる。
このように、ボンディングワイヤ間の誘導結合を阻止し相互インダクタンスの低減を図っているので相互インダクンスが０もしくはそれに近い値となり、信号対位相雑音電力比（Ｃ／Ｎ）の劣化量が著しく減少する。 The oscillation transistor is formed in, for example, a package 30 formed of a resin sealing body such as an epoxy resin, and the collector terminal 31, the base terminal 32, the emitter terminal 33, and the like that are partially exposed from the package 30 in the package 30. External terminals are provided. A chip 34 whose back surface is a collector is joined to the collector terminal 31, and the base terminal (B) 32 and emitter terminal (E) 33 and the base and emitter in the chip 34 are joined by bonding wires 35 and 36, respectively. Has been. A magnetic shield material 37 is inserted between the base bonding wire 35 and the emitter bonding wire 36 in the package 30. By inserting this, inductive coupling between the bonding wires is prevented and the mutual inductance is reduced. As the magnetic shield material 37, a metal magnetic material such as iron, a resinous electromagnetic wave absorber, or the like can be used.
In this way, the inductive coupling between the bonding wires is prevented and the mutual inductance is reduced, so that the mutual inductance becomes 0 or a value close thereto, and the amount of degradation of the signal-to-phase noise power ratio (C / N) is remarkably reduced. .

次に、図１２を参照して実施例４を説明する。
図１２は、この実施例の発振トランジスタ及び他のバッファトランジスタを１つのパッケージ内部に収納した半導体装置の概略平面図である。この発振トランジスタは、図３に示す発振回路の共振回路部を構成する負性抵抗回路部内のトランジスタＱ２に用いられる。発振回路は、発振周波数を設定する共振回路部及び入力抵抗が負性を示す負性抵抗回路部から構成された発振回路部と、前記負性抵抗回路部の出力信号を増幅して出力するバッファ回路部とからなる。この実施例のパッケージは、発振トランジスタＱ２と共にバッファ回路部のバッファトランジスタＱ１もパッケージングされている。
パッケージ４０は、例えば、エポキシ樹脂などの樹脂封止体からなり、パッケージ４０内には発振トランジスタ（Ｑ２）及びバッファトランジスタ（Ｑ１）が形成されたチップ４４、４４′が収納されている。パッケージ４０内には、一端がパッケージから一部露出したコレクタ端子４１、ベース端子４２及びエミッタ端子４３などの外部端子が設けられている。コレクタ端子４１（Ｃ２）には裏面がコレクタであるチップ４４が接合されており、ベース端子（Ｂ２）４２及びエミッタ端子（Ｅ２）４３とチップ４４内のベース及びエミッタとは、それぞれボンディングワイヤ４５、４６により接合されている。 Next, Example 4 will be described with reference to FIG.
FIG. 12 is a schematic plan view of a semiconductor device in which the oscillation transistor and other buffer transistors of this embodiment are housed in one package. This oscillating transistor is used as the transistor Q2 in the negative resistance circuit part that constitutes the resonant circuit part of the oscillating circuit shown in FIG. An oscillation circuit includes an oscillation circuit unit configured by a resonance circuit unit that sets an oscillation frequency and a negative resistance circuit unit whose input resistance is negative, and a buffer that amplifies and outputs an output signal of the negative resistance circuit unit It consists of a circuit part. In the package of this embodiment, the buffer transistor Q1 of the buffer circuit portion is packaged together with the oscillation transistor Q2.
The package 40 is made of, for example, a resin sealing body such as an epoxy resin, and chips 44 and 44 'on which the oscillation transistor (Q2) and the buffer transistor (Q1) are formed are accommodated in the package 40. In the package 40, external terminals such as a collector terminal 41, a base terminal 42, and an emitter terminal 43, which are partially exposed from the package, are provided. The collector terminal 41 (C2) is joined with a chip 44 whose back surface is a collector, and the base terminal (B2) 42 and the emitter terminal (E2) 43 and the base and emitter in the chip 44 are respectively connected to a bonding wire 45, 46 is joined.

パッケージ４０内のベースのボンディングワイヤ４５とエミッタのボンディングワイヤ４６の中間に磁気シールド材４７を挿入する。これを挿入することにより、ボンディングワイヤ間の誘導結合を阻止し相互インダクタンスが低減される。磁気シールド材４７としては鉄などの金属磁性体や樹脂状の電波吸収体などを用いることができる。
以上が発振トランジスタＱ２のパッケージ４０内の配置である。
一方、パッケージ４０内には、バッファトランジスタＱ１も収納されている。一端がパッケージから一部露出したコレクタ端子４１′、ベース端子４２′及びエミッタ端子４３′などの外部端子が設けられている。コレクタ端子（Ｃ１）４１′には裏面がコレクタであるチップ４４′が接合されており、ベース端子（Ｂ１）４２′及びエミッタ端子（Ｅ１）４３′とチップ４４′内のベース及びエミッタとは、それぞれボンディングワイヤ４５′、４６′により接合されている。ベース端子４２′及びエミッタ端子４３′の配置方向は特に規定されていない。ボンディングワイヤ４５′、４６′の配線方向も特に限定されていない。 A magnetic shield material 47 is inserted between the base bonding wire 45 and the emitter bonding wire 46 in the package 40. By inserting this, inductive coupling between the bonding wires is prevented and the mutual inductance is reduced. As the magnetic shield material 47, a metal magnetic material such as iron, a resinous electromagnetic wave absorber, or the like can be used.
The above is the arrangement of the oscillation transistor Q2 in the package 40.
On the other hand, the buffer transistor Q1 is also accommodated in the package 40. External terminals such as a collector terminal 41 ', a base terminal 42', and an emitter terminal 43 ', one end of which is partially exposed from the package, are provided. The collector terminal (C1) 41 ′ is joined with a chip 44 ′ whose back surface is a collector, and the base terminal (B1) 42 ′ and the emitter terminal (E1) 43 ′ and the base and emitter in the chip 44 ′ are: They are joined by bonding wires 45 'and 46', respectively. The arrangement direction of the base terminal 42 'and the emitter terminal 43' is not particularly defined. The wiring direction of the bonding wires 45 'and 46' is not particularly limited.

パッケージ内の発振トランジスタのボンディングワイヤが以上のように配置されているので前述の理由からその部分の相互インダクンスが０もしくはそれに近い値となり、信号対位相雑音電力比（Ｃ／Ｎ）の劣化量が著しく減少する。
以上のように、発振トランジスタＱ２のパッケージ内においてトランジスタチップとパッケージの外部端子とを接続するボンディングワイヤの内、ベースのボンディングワイヤとエミッタのボンディングワイヤ間の相互インダクタンスに着目し、この相互インダクタンスの値が大きいと、発振回路出力信号の位相雑音特性の悪化を招くことが明らかになった。即ち、本発明に依れば有害な相互インダクタンスを低減することができ、良好な位相雑音特性を有する発振出力信号を得ることができる。 Since the bonding wires of the oscillation transistors in the package are arranged as described above, the mutual inductance of the portion becomes 0 or a value close to it for the above-mentioned reason, and the deterioration amount of the signal-to-phase noise power ratio (C / N) is reduced. Remarkably reduced.
As described above, paying attention to the mutual inductance between the bonding wire of the base and the bonding wire of the emitter in the bonding wire connecting the transistor chip and the external terminal of the package in the package of the oscillation transistor Q2, the value of this mutual inductance It has been clarified that the phase noise characteristic of the oscillation circuit output signal deteriorates when the value is large. That is, according to the present invention, harmful mutual inductance can be reduced, and an oscillation output signal having good phase noise characteristics can be obtained.

本発明の一実施例である実施例１のパッケージを透過した発振トランジスタの概略平面図及び回路図。The schematic plan view and circuit diagram of the oscillation transistor which permeate | transmitted the package of Example 1 which is one Example of this invention. 図１のパッケージに組み込まれるチップ内部の概略断面図。FIG. 2 is a schematic cross-sectional view of the inside of a chip incorporated in the package of FIG. 1. 図１のトランジスタが組み込まれた発振回路の回路図。FIG. 2 is a circuit diagram of an oscillation circuit in which the transistor of FIG. 1 is incorporated. ２つの回路Ｃ１・Ｃ２間の相互インダクタンスを求める式（ノイマンの公式）の説明図。Explanatory drawing of the formula (Neumann's formula) which calculates | requires the mutual inductance between two circuits C1 and C2. 平行導体間の相互インダクタンスを求める式の説明図。Explanatory drawing of the type | formula which calculates | requires the mutual inductance between parallel conductors. ２つの回路Ｃ１・Ｃ２間の相互インダクタンスを求めるノイマンの公式を示す図。The figure which shows the Neumann formula which calculates | requires the mutual inductance between two circuits C1 * C2. ボンディングワイヤ間の誘導結合による発振回路の位相雑音特性に及ぼす影響を説明する発振トランジスタ（比較例）の平面図及び回路図。The top view and circuit diagram of an oscillation transistor (comparative example) explaining the influence which it has on the phase noise characteristic of an oscillation circuit by the inductive coupling between bonding wires. 発振トランジスタのパッケージ内部のベース側ボンディングワイヤとエミッタ側ボンディングワイヤ間の相互インダクタンスを変化させた場合の発振出力信号の位相雑音特性（Ｃ／Ｎ（信号対位相雑音）比）の計算値を示す特性図。A characteristic indicating the calculated value of the phase noise characteristic (C / N (signal to phase noise) ratio) of the oscillation output signal when the mutual inductance between the base side bonding wire and the emitter side bonding wire inside the package of the oscillation transistor is changed. Figure. 本発明の一実施例である実施例２に係る発振トランジスタのパッケージを透過した概略平面図及び回路図。The schematic plan view and circuit diagram which permeate | transmitted the package of the oscillation transistor which concerns on Example 2 which is one Example of this invention. 本発明の一実施例である実施例３に係る発振トランジスタのパッケージを透過した概略平面図。The schematic plan view which permeate | transmitted the package of the oscillation transistor which concerns on Example 3 which is one Example of this invention. 図１０の発振トランジスタの概略斜視図。FIG. 11 is a schematic perspective view of the oscillation transistor of FIG. 10. 本発明の一実施例である実施例４に係る発振トランジスタのパッケージを透過した概略平面図。The schematic plan view which permeate | transmitted the package of the oscillation transistor which concerns on Example 4 which is one Example of this invention.

符号の説明Explanation of symbols

１・・・コレクタ ２・・・ベース ３・・・エミッタ
１０、２０、３０、４０、５０・・・パッケージ（樹脂封止体）
１１、２１、２１′、３１、４１、４１′、５１・・・コレクタ端子（Ｃ）
１２、２２、２２′、３２、４２、４２′、５２・・・ベース端子（Ｂ）
１３、２３、２３′、３３、４３、４３′、５３・・・エミッタ端子（Ｅ）
１４、２４、２４′、３４、４４、４４′、５４・・・チップ
１５、２５、２５′、３５、４５、４５′、５５・・・ベース用ボンディングワイヤ
１６、２６、２６′、３６、４６、４６′、５６・・・エミッタ用ボンディングワイヤ
３７、４７・・・磁気シールド材
Ｒ１、Ｒ２、Ｒ３、Ｒ４・・・抵抗素子
Ｃ１、Ｃ２、Ｃ３、Ｃ４、Ｃ５、Ｃ６、Ｃ７、Ｃ８、Ｃ９・・・コンデンサ素子
Ｌ１、Ｌ２、Ｌ３、Ｌ４・・・インダクタ素子（固定インダクタ又は伝送線路）
Ｄ１・・・可変容量ダイオード又はコンデンサ素子
Ｑ１・・・バッファトランジスタ
Ｑ２・・・発振トランジスタ

DESCRIPTION OF SYMBOLS 1 ... Collector 2 ... Base 3 ... Emitter 10, 20, 30, 40, 50 ... Package (resin sealing body)
11, 21, 21 ', 31, 41, 41', 51 ... collector terminal (C)
12, 22, 22 ', 32, 42, 42', 52 ... Base terminal (B)
13, 23, 23 ', 33, 43, 43', 53 ... Emitter terminal (E)
14, 24, 24 ', 34, 44, 44', 54 ... Chips 15, 25, 25 ', 35, 45, 45', 55 ... Base bonding wires 16, 26, 26 ', 36, 46, 46 ', 56 ... Emitter bonding wires 37, 47 ... Magnetic shield materials R1, R2, R3, R4 ... Resistance elements C1, C2, C3, C4, C5, C6, C7, C8, C9: Capacitor element L1, L2, L3, L4: Inductor element (fixed inductor or transmission line)
D1 Variable diode or capacitor element Q1 Buffer transistor Q2 Oscillation transistor

Claims (5)

発振トランジスタと、
ベース端子と、
エミッタ端子と、
前記発振トランジスタのベースと前記ベース端子とを接続する第１のボンディングワイヤと、
前記発振トランジスタのエミッタと前記エミッタ端子とを接続する第２のボンディングワイヤと、
前記発振トランジスタ、前記ベース端子の一部、前記エミッタ端子の一部、前記第１及び第２のボンディングワイヤを封止するパッケージとを備え、
前記ベース端子と前記エミッタ端子の配線方向が直角であり、且つ前記第１及び第２のボンディングワイヤの配線方向が直角であることを特徴とする発振トランジスタ。 An oscillation transistor;
A base terminal;
An emitter terminal;
A first bonding wire connecting the base of the oscillation transistor and the base terminal;
A second bonding wire connecting the emitter of the oscillation transistor and the emitter terminal;
A package for sealing the oscillation transistor, a part of the base terminal, a part of the emitter terminal, and the first and second bonding wires;
An oscillation transistor, wherein a wiring direction of the base terminal and the emitter terminal is a right angle, and a wiring direction of the first and second bonding wires is a right angle. 発振トランジスタと、
ベース端子と、
エミッタ端子と、
前記発振トランジスタのベースと前記ベース端子とを接続する第１のボンディングワイヤと、
前記発振トランジスタのエミッタと前記エミッタ端子とを接続する第２のボンディングワイヤと、
前記発振トランジスタ、前記ベース端子の一部、前記エミッタ端子の一部、前記第１及び第２のボンディングワイヤを封止するパッケージとを備え、
前記パッケージ内において、前記ベース端子と前記エミッタ端子との間又は前記第１及び第２のボンディングワイヤの間もしくは前記ベース端子と前記エミッタ端子との間及び前記第１及び第２のボンディングワイヤの間に磁気シールド材を挿入したことを特徴とする発振トランジスタ。 An oscillation transistor;
A base terminal;
An emitter terminal;
A first bonding wire connecting the base of the oscillation transistor and the base terminal;
A second bonding wire connecting the emitter of the oscillation transistor and the emitter terminal;
A package for sealing the oscillation transistor, a part of the base terminal, a part of the emitter terminal, and the first and second bonding wires;
Within the package, between the base terminal and the emitter terminal, between the first and second bonding wires, between the base terminal and the emitter terminal, and between the first and second bonding wires. An oscillation transistor comprising a magnetic shielding material inserted in 前記発振トランジスタは、発振周波数を設定する共振回路部と、入力抵抗が負性を示す負性抵抗回路部と、前記負性抵抗回路部の出力信号を増幅して出力するバッファ回路部とから構成される発振回路に用いられ、前記発振トランジスタは、前記負性抵抗回路部に組み込まれることを特徴とする請求項１又は請求項２に記載の発振トランジスタ。 The oscillation transistor includes a resonance circuit unit that sets an oscillation frequency, a negative resistance circuit unit whose input resistance is negative, and a buffer circuit unit that amplifies and outputs an output signal of the negative resistance circuit unit The oscillation transistor according to claim 1, wherein the oscillation transistor is incorporated in the negative resistance circuit unit. 発振周波数を設定する共振回路部と、
発振トランジスタである第１のトランジスタを含み入力抵抗が負性を示す負性抵抗回路部と、
第２のトランジスタを含み前記負性抵抗回路部の出力信号を増幅して出力するバッファ回路部とを備え、
前記第１のトランジスタと前記第２のトランジスタは同一パッケージ内に組み込まれ、前記パッケージ内において、前記第１のトランジスタのベースとベース端子とを接続する第１のボンディングワイヤの配置方向と、前記第１のトランジスタのエミッタとエミッタ端子とを接続する第２のボンディングワイヤの配置方向とが直角であることを特徴とする発振回路。 A resonant circuit for setting the oscillation frequency;
A negative resistance circuit portion including a first transistor which is an oscillation transistor and having negative input resistance;
A buffer circuit unit that includes a second transistor and amplifies and outputs an output signal of the negative resistance circuit unit;
The first transistor and the second transistor are incorporated in the same package, and in the package, an arrangement direction of a first bonding wire connecting a base and a base terminal of the first transistor, and the first transistor An oscillation circuit characterized in that an arrangement direction of a second bonding wire connecting the emitter and emitter terminal of one transistor is perpendicular. 発振周波数を設定する共振回路部と、
発振トランジスタである第１のトランジスタを含み入力抵抗が負性を示す負性抵抗回路部と、
第２のトランジスタを含み前記負性抵抗回路部の出力信号を増幅して出力するバッファ回路部とを備え、
前記第１のトランジスタと前記第２のトランジスタは同一パッケージ内に組み込まれ、前記パッケージ内において、前記第１のトランジスタのベースとベース端子とを接続する第１のボンディングワイヤと、前記第１のトランジスタのエミッタとエミッタ端子とを接続する第２のボンディングワイヤの中間及び前記ベース端子と前記エミッタ端子との中間に磁気シールド材を挿入することを特徴とする発振回路。



A resonant circuit for setting the oscillation frequency;
A negative resistance circuit portion including a first transistor which is an oscillation transistor and having negative input resistance;
A buffer circuit unit that includes a second transistor and amplifies and outputs an output signal of the negative resistance circuit unit;
The first transistor and the second transistor are incorporated in the same package, and in the package, a first bonding wire that connects a base and a base terminal of the first transistor, and the first transistor An oscillation circuit, wherein a magnetic shield material is inserted in the middle of a second bonding wire for connecting the emitter and the emitter terminal and in the middle of the base terminal and the emitter terminal.



JP2005275377A 2005-09-22 2005-09-22 Oscillation transistor and oscillation circuit Pending JP2007088217A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011166620A (en) * 2010-02-12 2011-08-25 Murata Mfg Co Ltd Lc filter
CN111800096A (en) * 2019-04-05 2020-10-20 株式会社村田制作所 Power amplifying device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011166620A (en) * 2010-02-12 2011-08-25 Murata Mfg Co Ltd Lc filter
CN111800096A (en) * 2019-04-05 2020-10-20 株式会社村田制作所 Power amplifying device
CN111800096B (en) * 2019-04-05 2023-10-10 株式会社村田制作所 Power amplifying device

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