JP2007087989A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which can reduce an opposing capacity accompanied between actual wirings formed in the same wiring layer while flattening among the wirings is realized. <P>SOLUTION: The semiconductor integrated circuit device has a multilayer wiring structure. Actual wirings L1 and L2 as a signal transmitting route, and linearly formed dummy patterns D1 and D2 non-parallel to the actual wirings L1 and L2, are formed in each of the wiring layers. The dummy patterns D1 and D2 of the respective layers that are respectively formed on the vertically adjoining wiring layers are non-parallel to each other. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device having a multilayer wiring structure, and more particularly to an arrangement layout of dummy patterns in each wiring layer.

  Conventionally, in each wiring layer of a semiconductor integrated circuit device having a multi-layered wiring structure, an actual wiring as a signal transmission path is formed, and a portion where the interval of the actual wiring is wide (a portion where the arrangement density is sparse) is In addition, a dummy pattern that is not electrically connected to the actual wiring (dummy wiring formed simultaneously with the actual wiring by the wiring layer forming process) is formed.

  FIG. 3 is a wiring layout diagram showing a conventional dummy pattern.

  As shown in FIG. 3 (a), the conventional dummy pattern D1 is generally formed in a line parallel to the actual wiring L1 adjacent thereto with a predetermined distance (see Patent Document 1). .

  Further, conventionally, as shown in FIG. 3B, a shape in which the facing capacitance between at least the adjacent actual wires L1 is reduced as compared with a rectangular parallelepiped having a parallel plane with the actual wires L1 (for example, A semiconductor integrated circuit device in which a dummy pattern D1 is formed having a polygonal column shape including a surface that is not parallel to the actual wiring L1 is also disclosed and proposed (see Patent Document 2).

JP 10-335326 A JP 2005-57003 A

  Certainly, if a dummy pattern is formed in a portion where the interval of the actual wiring is wide for each wiring layer, the density of the wiring density in the wiring layer can be reduced, and this can be flattened. It is possible to alleviate the generation of a step in the interlayer insulating film to be covered, and to improve the reliability of the wiring layer formed on the upper part (avoidance of disconnection of the actual wiring).

  However, in the conventional configuration (FIG. 3A) in which the dummy pattern is formed in a line parallel to the actual wiring adjacent thereto, the dummy pattern is interposed between the actual wiring adjacent to both sides of the dummy pattern. A large counter capacitance (parasitic capacitance) is likely to accompany, and there is a possibility that circuit characteristics such as signal delay and noise increase may be deteriorated.

  The simplest method for solving the above problem is to make a large distance between the actual signal wiring and the dummy pattern. However, this method is not a constructive solution because it causes a decrease in the dummy pattern insertion rate (and hence a decrease in the flatness of the interlayer insulating film).

  On the other hand, with the conventional technique of FIG. 3 (FIG. 3B), it is possible to reduce the counter capacitance and suppress deterioration of circuit characteristics without incurring a decrease in dummy pattern insertion rate. .

  However, although the conventional technique aims to reduce the opposing capacitance between the actual wirings formed in the same wiring layer while flattening between the wiring layers, the plurality of wirings No consideration is given to the relative layout of each layer dummy pattern formed for each layer, and when the dummy pattern disclosed in the related art is simply applied across a plurality of wiring layers, There are not a few cases in which the dummy patterns of both layers are overlapped and stacked with the end surfaces of the wiring patterns adjacent to each other between the upper and lower wiring layers.

  FIG. 4 is a schematic longitudinal sectional view for explaining a state in which dummy patterns of upper and lower layers are overlapped and stacked. As shown in this figure, when the dummy patterns D1 and D2 of both layers are overlapped with each other between the upper and lower wiring layers, the flatness of the interlayer insulating films ILD1 and ILD2 is increased. The presence of the dummy patterns D1 and D2 inserted into the back of the film may cause a large difference in level d on the interlayer insulating films ILD1 and ILD2.

  For this reason, when adopting the prior art of Patent Document 1, it is necessary to individually examine the position of each layer dummy pattern D1, D2 individually in order to avoid overlapping lamination of each layer dummy pattern D1, D2. There is a concern that the layout work of each wiring layer becomes very complicated.

  Alternatively, as described in Patent Document 1, the interlayer insulating films ILD1 and ILD2 are multi-layered and flattened (for example, CMP [Chemical Mechanical Polish] processing), so that the interdependency between the upper and lower adjacent wiring layers is increased. Although a method of eliminating it is conceivable, when such a method is adopted, there is a concern about an increase in the number of manufacturing steps and a cost increase associated therewith, and the significance of inserting the dummy pattern itself is slightly or dilute.

  In addition, since the level difference d increases as the number of stacked layers of the semiconductor integrated circuit device increases, it is considered extremely important to avoid the overlapping stacking of the dummy patterns in each layer in order to increase the integration and the number of layers. .

  In view of the above problems, the present invention provides a semiconductor integrated circuit device capable of reducing the opposing capacitance between real wirings formed in the same wiring layer while flattening the wiring layers. The purpose is to do.

  In order to achieve the above object, a semiconductor integrated circuit device according to the present invention has a multilayer wiring structure, and each wiring layer has an actual wiring as a signal transmission path and a non-connection to the actual wiring. Dummy patterns formed in parallel lines are formed, and the extending directions of the dummy patterns in the respective layers formed in the wiring layers adjacent to each other are made non-parallel to each other.

  In the semiconductor integrated circuit device according to the present invention, it is possible to reduce the case where the dummy patterns of both layers are overlapped and stacked with the end surfaces of the wiring layers adjacent to each other between upper and lower adjacent wiring layers. It is possible to reduce the counter capacitance associated with the actual wirings formed in the same wiring layer.

  FIG. 1 is a wiring layout diagram (transparent top view) of a semiconductor integrated circuit device according to the present invention. In the following description, for the sake of convenience, the left-right direction of the paper surface is referred to as “X-axis direction”, and the vertical direction of the paper surface is referred to as “Y-axis direction”. These X-axis direction and Y-axis direction may be determined based on, for example, the orientation flat of the silicon wafer from which the semiconductor substrate is cut out.

  The semiconductor integrated circuit device according to the present invention has a two-layer wiring structure, and the first and second wiring layers have real wirings L1 and L2 as signal transmission paths and real wirings L1 and L2. Dummy patterns D1 and D2 formed in non-parallel lines are formed respectively.

  The actual wiring L1 of the first wiring layer is formed in a linear shape extending in the Y-axis direction. On the other hand, the actual wiring L2 of the second wiring layer is formed in a linear shape extending in a direction orthogonal to the actual wiring L1 (that is, the X-axis direction). Therefore, the signal transmission path can be routed two-dimensionally by connecting the actual wirings L1 and L2 with contact holes (not shown).

  The dummy patterns D1 and D2 of the first and second wiring layers are dummy wirings formed simultaneously with the actual wirings L1 and L2 by the first and second wiring layer forming processes (the actual wirings L1 and L2 are electrically connected to each other). Conductive wiring that is not electrically connected), and is formed so as to compensate for a portion where the spacing between the actual wirings L1 and L2 is wide (portion where the arrangement density is sparse).

  In this way, if the dummy patterns D1 and D2 are formed in a portion where the distance between the actual wirings L1 and L2 is wide, the density of the wiring density in the wiring layer can be reduced and flattened. It is possible to alleviate the occurrence of a step in the interlayer insulating film covering the layer. In particular, by forming the dummy pattern D1, the interlayer insulating film immediately above the first wiring layer is flattened, thereby improving the reliability of the second wiring layer formed thereon (avoidance of disconnection of the actual wiring L2). It can be realized.

  Further, as described above, the dummy patterns D1 and D2 are formed in linear shapes that are not parallel to the actual wirings L1 and L2, respectively. More specifically, using the X axis as a reference axis (0 °), the dummy pattern D1 is formed in a linear shape that forms a first angle (+ 45 ° in the present embodiment) with respect to the X axis. The dummy pattern D2 is formed in a linear shape that forms a second angle (−45 ° in the present embodiment) with respect to the X axis.

  With this configuration, when compared with the conventional configuration in which the dummy pattern is parallel to the actual wiring (see FIG. 3A) for the first wiring layer, the actual wiring L1 and the dummy are compared. When the closest distance to the pattern D1 is set to the conventional value, the opposing capacitance (parasitic capacitance) accompanying the actual wiring L1 adjacent to both sides of the dummy pattern D1 is reduced, and deterioration of circuit characteristics is suppressed. It becomes possible. On the other hand, if the effect of reducing the counter capacitance is sufficient at the conventional level, the closest distance between the actual wiring L1 and the dummy pattern D1 is further shortened, and the insertion rate of the dummy pattern D1 is improved (and the flatness of the interlayer insulating film is extended). Degree of improvement) can be realized. The second wiring layer is the same as described above.

  Furthermore, in the semiconductor integrated circuit device according to the present invention, the extending directions of the dummy patterns D1 and D2 of the respective layers formed in the first and second wiring layers adjacent to each other in the vertical direction are not parallel to each other (in this embodiment, orthogonal to each other). ).

  With such a configuration, unlike the configuration in which the respective layer dummy patterns D1 and D2 are made parallel to each other, as shown in FIG. It is possible to greatly reduce the number of cases in which the end surfaces are overlapped and stacked. Therefore, as shown in FIG. 2, it is possible to alleviate the overlapping lamination of the respective layer dummy patterns D1, D2, and to increase the flatness of the interlayer insulating films ILD1, ILD2.

  In the above embodiment, the case where the present invention is applied to a semiconductor integrated circuit device having a two-layer wiring structure has been described as an example for convenience of explanation, but the scope of application of the present invention is not limited to this. Of course, the present invention can also be applied to a semiconductor integrated circuit device having a multilayer wiring structure of three or more layers.

  The configuration of the present invention can be variously modified within the scope of the present invention in addition to the above embodiment.

  For example, the inclination angles of the dummy patterns D1 and D2 are not limited to the setting values (± 45 °) of the above embodiment, and can be set as appropriate during the wiring layout work. Also, the width and length of the dummy patterns D1 and D2 can be set as appropriate during the wiring layout operation as described above.

  The present invention is a useful technique for advancing high integration and multi-layered semiconductor integrated circuit devices.

These are wiring layout diagrams of the semiconductor integrated circuit device according to the present invention. These are typical longitudinal cross-sectional views for demonstrating the state by which the overlapping lamination | stacking of each layer dummy pattern was eased. These are the wiring layout figures which showed the conventional dummy pattern. These are the typical longitudinal cross-sectional views for demonstrating the state by which each layer dummy pattern was laminated | stacked in an overlapping manner.

Explanation of symbols

L1 Real signal wiring (first wiring layer)
L2 Real signal wiring (second wiring layer)
D1 dummy pattern (first wiring layer)
D2 dummy pattern (second wiring layer)
ILD1 interlayer insulating film (on the first wiring layer)
ILD2 interlayer insulating film (on the second wiring layer)

Claims (1)

  Each wiring layer is formed with a real wiring as a signal transmission path and a dummy pattern formed in a line shape that is non-parallel to the real wiring. A semiconductor integrated circuit device, characterized in that the extending directions of the dummy patterns of the respective layers formed in the upper and lower adjacent wiring layers are non-parallel to each other.

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