JP2007082239A - Liquid crystal display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To ensure suitable circuit operation by correcting an input signal appropriately depending on the relationship of the power supply voltage, the amplitude of an input signal, and the threshold voltage of a transistor in a digital circuit having a switch circuit employing a transistor. <P>SOLUTION: A digital circuit (30) comprises a switch circuit (31) having first transistors (32, 33) supplied with power supply potentials (VDD, VSS), correction circuits (34, 36) connected between an input end (IN) applied with an input signal and the control terminal (gate) of the first transistor, capacitors (C2, C3) connected between the control terminal and the input end, second transistors (35, 37) in diode connection provided between the nodes (N5, N6) of the capacitor and the control terminal and having a threshold substantially equal to that of the first transistor, and switches (SW2, SW3) connected in series with the second transistor. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

    The present invention relates to a digital circuit using a transistor. In particular, when the amplitude of the input signal is smaller than the power supply voltage or when the power supply voltage is not sufficiently large with respect to the threshold voltage of the transistor being used, the DC level of the input signal is corrected to perform a suitable circuit operation. The present invention relates to a digital circuit including a correction circuit for realizing.

Conventionally, inverter circuits using transistors such as bipolar transistors and field effect transistors (FETs) have been widely used. FIG. 36a shows a typical example of a conventional CMOS inverter circuit using MOSFET as a transistor. The CMOS inverter circuit 200 includes a P-type MOSFET 201 having a threshold voltage V _THP and an N-type MOSFET 202 having a threshold voltage V _THN connected in series between a high-level power supply potential VDD and a low-level power supply potential VSS. (Usually V _THP is negative and V _THN is positive). The source of the P-type MOSFET 201 is connected to the high-level power supply potential VDD, and the source of the N-type MOSFET 202 is connected to the low-level power supply potential VSS. The drains of both MOSFETs 201 and 202 are connected to each other, and the connection point N (node) is connected to the output terminal OUT. The gates of the MOSFETs 201 and 202 are both connected to an input terminal IN to which an input signal that swings between a high level input potential _VINH and a low level input potential _VINL is applied. In this specification, unless otherwise specified, “connection” of circuit elements means “electrical connection”.

The normal operation of the CMOS inverter circuit 200 having such a configuration is shown in FIGS. 36b and 36c. In FIGS. 36b and 36c, the MOSFETs 201 and 202 are indicated by switch symbols in order to show the on / off states of the MOSFETs 201 and 202. As shown in FIG. 36b, a high level input potential V _INH equal to or higher than the value obtained by subtracting the absolute value | V _THP | of the threshold voltage of the P-type MOSFET from the high level power supply potential VDD is input to the input terminal IN. Then, the P-type MOSFET 201 is turned off, the N-type MOSFET 202 is turned on, and a potential substantially equal to the low-level power supply potential VSS is supplied to the output terminal OUT as an output signal. Further, as shown in FIG. 36c, the low level input potential V _INL equal to or lower than the value obtained by adding the absolute value | V _THN | of the threshold voltage of the N-type MOSFET to the low level power supply potential VSS is the input terminal IN. Is inputted, the P-type MOSFET 201 is turned on, the N-type MOSFET 202 is turned off, and a potential substantially equal to the high-level power supply potential VDD is supplied to the output terminal OUT as an output signal.

However, for example, when an input signal is supplied from an IC with a low operating voltage, the following problems may occur. As shown in FIG. 37a, when the high level input potential _VINH applied to the input terminal IN is lower than the value obtained by subtracting the absolute value | V _THP | of the threshold voltage of the P-type MOSFET 201 from the high level power supply potential VDD. In the type MOSFET 201, the gate-source voltage V _GS (= gate potential V _G −source potential V _S ) <− | V _THP |, and the P-type MOSFET 201 is not turned off. As a result, both MOSFETs 201 and 202 are turned on, A potential divided by the on-state resistance of the P-type MOSFET 201 and the N-type MOSFET 202 is output to the output terminal OUT, and the low-level power supply potential VSS is not output. Similarly, when the low-level input potential V _INL applied to the input terminal IN is higher than the value obtained by adding the absolute value | V _THN | of the threshold voltage of the N-type MOSFET 202 to the low-level power supply potential VSS, the N-type MOSFET 202 is turned off. Thus, both MOSFETs 201 and 202 are turned on, and the high-level power supply potential VDD is not output to the output terminal OUT. Input potential _V INH _{Thus, V INL} and the power supply potential VDD, no MOSFET201,202 reliably turned on and off level of the inverter circuit 200 by different between VSS, if the output is not a desired value, There arises a problem that a circuit subsequent to the inverter circuit 200 cannot be driven or the operation of such a circuit becomes uncertain. In addition, since both MOSFETs 201 and 202 are simultaneously turned on and a short current flows, there is a problem that power consumption increases.

  In order to solve the above-described problem, in a level shifter circuit having a first input inverter and a second output inverter, input from the first inverter to the second inverter by a capacitor (capacitor) and bias means. It has been proposed to convert the DC level of a signal to be transmitted (see Japanese Patent Application Laid-Open No. 9-172367). However, in this circuit, the DC level conversion capacitor connected between the gate of each transistor constituting the second inverter and the output of the first inverter always has a high level power supply potential or a low level power supply potential by the bias means. Therefore, the charging / discharging of these capacitors adversely affects the dynamic characteristics of the circuit (that is, the circuit operating speed is reduced), or the power consumption associated with charging / discharging of these capacitors cannot be ignored. May become a problem. In addition, when the threshold voltage of the transistor varies, it is difficult to match the capacitance of each capacitor to the corresponding transistor. For this reason, the voltage at both ends of the DC level conversion capacitor is not equal to that of the corresponding transistor. There is also a problem that the transistor cannot be accurately turned on / off without being matched with the threshold voltage.

In the inverter circuit 200 shown in FIG. 36A, for example, the power supply voltage (VDD-VSS) is small to suppress power consumption, and the power supply voltage is not sufficiently large with respect to the absolute value of the threshold voltage of the MOSFETs 201 and 202. Even if the amplitude of the input signal applied to the input terminal IN is the same as the power supply voltage, there may be a problem that a sufficient current cannot be supplied to the MOSFETs 201 and 202 to drive at high speed. This is because it is not the gate-source voltage V _GS but the V _GS −V _TH that contributes to the current flowing through the MOSFET. For example, in the inverter circuit 200 of FIG. 36a, VDD = 3.3V, VSS = 0V (ground), the threshold voltage V _THP = −2V of the P-type MOSFET 201, the threshold voltage V _THN = 3V of the N-type MOSFET 202, The high level input potential V _INH = VDD = 3.3V and the low level input potential V _INL = VSS = 0V. When the low-level input potential V _INL is applied to the input terminal IN, in the P-type MOSFET 201, V _GS −V _THP = −3.3 − (− 2) = − 1.3 V and the P-type MOSFET 201 is turned on, and the N-type MOSFET 202 Then, V _GS −V _THP = 0−3 = −3V, and the N-type MOSFET 202 is turned off. In this case, since the absolute value of the threshold voltage (−2V) of the P-type MOSFET is sufficiently small with respect to the power supply voltage (that is, the amplitude of the input signal), the absolute value of V _GS −V _THP is increased (1. 3V), and no problem arises. On the other hand, when the high-level input potential _VINH is applied to the input terminal IN, V _GS −V _THP = 0 − (− 2) = 2V in the P-type MOSFET 201 and the P-type MOSFET 201 is turned off, and in the N-type MOSFET 202, V _GS − V _THP = 3.3-3 = 0.3V and the N-type MOSFET 202 is turned on, but since V _GS -V _THP is very small at 0.3V, the flowing current becomes small and the N-type MOSFET 202 operates at high speed. Cannot be turned on. Of course, if the power supply voltage and the amplitude of the input signal are increased, it is possible to operate at high speed, but the power consumption increases.

  The present invention is for solving the above-described problems of the prior art, and a main object of the present invention is a digital circuit having a switch circuit using a transistor, which includes a power supply voltage and an amplitude of an input signal. Another object of the present invention is to provide a digital circuit capable of appropriately correcting an input signal in accordance with a relationship between threshold voltages of transistors and capable of performing a suitable circuit operation.

  A second object of the present invention is a digital circuit having a switch circuit using a transistor, and even when the amplitude of an input signal is smaller than a power supply voltage (difference between a high level power supply potential and a low level power supply potential), it is ensured. To provide a digital circuit capable of turning on and off a transistor.

  A third object of the present invention is a digital circuit having a switch circuit using a transistor, and reliably turns the transistor on and off without deteriorating dynamic characteristics even when the amplitude of the input signal is smaller than the power supply voltage. It is to provide a digital circuit capable of.

  A fourth object of the present invention is a digital circuit having a switch circuit using a transistor, and the DC level connected to the control terminal of the transistor included in the switch circuit even when the amplitude of the input signal is smaller than the power supply voltage. To provide a digital circuit capable of reliably operating a transistor by charging a conversion capacitor to an appropriate value according to the threshold voltage of the corresponding transistor.

  A fifth object of the present invention is a digital circuit having a switch circuit using a transistor, wherein a sufficient current is supplied to the transistor even when the power supply voltage is not sufficiently large with respect to the absolute value of the threshold voltage of the transistor. It is to provide a digital circuit that can be operated at high speed.

  In order to achieve the above object, according to the present invention, there is provided a switch circuit connected between an input terminal and an output terminal, the switch circuit comprising a first terminal, a second terminal, a control terminal, And a first transistor that can be turned on / off by changing a potential of the control terminal with respect to the first terminal, and the first terminal of the first transistor includes a first transistor at least in a normal operation. Is a digital circuit in which the ON / OFF state of the first transistor can affect the signal at the output terminal, and in a normal operation, a first circuit for turning off the first transistor An input signal that swings between an input potential and a second input potential for turning on the first transistor is applied to the input terminal, and the digital circuit is connected between the input terminal and the control terminal of the first transistor. Contact The correction circuit includes a) a capacitor having one terminal connected to the input terminal and the other terminal connected to the control terminal of the first transistor, and b) a setting prior to normal operation. In operation, at least one switch for defining a conductive path for setting the charge accumulated in the capacitor so that the voltage across the capacitor has a predetermined value, and in normal operation, at least one switch A digital circuit is provided wherein the state is set to preserve the voltage across the capacitor.

  With such a configuration, in the setting operation prior to the normal operation, the normal operation is performed by appropriately setting the voltage across the capacitor according to the power supply voltage, the amplitude of the input signal, the threshold voltage of the first transistor, and the like. The DC level of the input signal can be corrected and a suitable circuit operation can be realized. In normal operation, the switch is set so as to hold the voltage (or charge) across the set capacitance, so that the capacitance adversely affects the dynamic characteristics of the digital circuit (ie, reduces the operation speed). There is no worry. Rather, the capacitor is connected in series with the parasitic capacitance of the transistor and reduces the total capacitance, which can contribute to the improvement of dynamic characteristics. Further, since it is not necessary to frequently perform the setting operation, power consumption associated with the setting operation is small.

  Preferably, the correction circuit includes a first terminal, a second terminal, and a control terminal, and is capable of on / off control by changing a potential of the control terminal with respect to the first terminal. A second transistor having the same conductivity type and substantially the same threshold voltage as the first transistor, wherein the first terminal of the second transistor is connected to the first power supply potential, The second terminal and the control terminal further include a second transistor connected to each other and connected to a node between the capacitor and the control terminal of the first transistor, and the at least one switch includes a second transistor It includes a first switch connected in series with the transistor, and in normal operation the first switch is off.

  Typically, the first and second transistors are FETs, and the first terminal, the second terminal, and the control terminal of the first and second transistors are a source, a drain, and a gate, respectively. When the high-level power supply potential and the low-level power supply potential are supplied as the power supply potential and the input signal swings between the high-level input potential and the low-level input potential, for example, when the first transistor is a P-type MOSFET, The power supply potential can be a high level power supply potential, and the first input potential can be a high level input potential. When the first transistor is, for example, an N-type MOSFET, the first power supply potential can be a low level power supply potential and the first input potential can be a low level input potential.

  According to a preferred embodiment of the present invention, even when the amplitude of the input signal is smaller than the power supply voltage, the setting operation is performed to reliably turn on and off the first transistor. That is, in the setting operation, with the first switch turned on, a potential substantially equal to the first input potential is applied to one terminal of the capacitor until the second transistor is turned off. Here, when the second transistor is turned off, it means that the second transistor is substantially turned off, and it is not always necessary to completely turn off (that is, the current flowing through the second transistor is completely zero). It is sufficient that the current flowing through is sufficiently small. As described above, in the setting operation, the second terminal and the control terminal are connected to each other (that is, diode-connected) to the capacitor connected between the control terminal and the input terminal of the first transistor through the second transistor. Until the second transistor is turned off or the current value becomes very small, the voltage across the capacitor is the difference between the first power supply potential and the first input potential, and the first transistor The battery can be charged to an appropriate voltage reflecting the threshold voltage. Thus, in normal operation, the voltage of the charged capacitor is applied to the input signal and applied to the control terminal of the first transistor, so that the first transistor can be reliably turned on and off. The reason why the threshold voltage of the first transistor can be reflected in the capacitance voltage is that the threshold voltage of the first transistor and the threshold voltage of the second transistor are approximately equal. It is desirable that the threshold voltages of the first transistor and the second transistor are equal, but even if they are slightly different, the digital circuit operates normally by appropriately charging the input signal correcting capacitor in the setting operation. It only has to be made. Further, when an FET is used as the transistor, the threshold voltage is often positive for N-type and negative for P-type, but the present invention can be applied even if the threshold voltage is any other value. It is.

  Preferably, the rectifying element is connected in parallel with the second transistor so that the forward direction thereof is opposite to the forward direction of the second transistor. As a result, even when a charge that reversely biases the diode-connected first transistor is accumulated in the capacitor due to noise or the like, when the first switch is turned on in the setting operation, the current flows through the rectifier element. Can flow, and the voltage across the capacitor can be converged to an appropriate value. The rectifying element may be a diode-connected transistor having the same conductivity type as the second transistor, for example.

  Further, a node between the capacitor and the control terminal of the first transistor is connected to a potential different from the first power supply potential via a further switch, and the further switch is turned on before the setting operation. It is preferable that the potential of the node can be set to a predetermined potential. Here, the predetermined potential is the first power supply potential and the predetermined potential when the first switch is turned on in the setting operation performed after the node potential is set to the predetermined potential and the further switch is turned off. Is a potential at which the second transistor is turned on by the potential difference between the first transistor and the second transistor. In this way, even when charge is undesirably accumulated in the capacitor due to, for example, noise, the potential of the node between the capacitor and the control terminal of the first transistor is set to an appropriate value prior to the setting operation. Thus, the setting operation is performed reliably, and the voltage across the capacitor is converged to an appropriate value corresponding to the difference between the first power supply potential and the first input potential and the threshold voltage of the first transistor. be able to. It is preferable that the other potential be a second power supply potential different from the first power supply potential because the other potential can be easily provided.

  Furthermore, one terminal of the capacitor is connected to the input terminal via the second switch, and is connected to a potential substantially equal to the first input potential via the third switch. In normal operation, The second switch is on, the first and third switches are off, and in the setting operation, the second switch can be off and the first and third switches can be on. In this way, the setting operation can be easily performed only by switching the switch without controlling the input potential. For example, even when the first transistor includes two transistors having different polarities, the setting operation of these transistors can be performed simultaneously.

  According to another preferred embodiment of the present invention, for example, even when the power supply voltage is low and the power supply voltage is not sufficiently large with respect to the absolute value of the threshold voltage of the transistor, a sufficient current is supplied to the transistor so as to operate at high speed Accordingly, a digital circuit capable of setting operation is provided. In such a digital circuit, a node between the capacitor and the control terminal of the first transistor is connected to a predetermined potential via the second switch. The setting operation includes a first setting operation and a second setting operation. In the first setting operation, the second switch is turned on and a first input potential is applied to the input terminal to charge the capacitor. In the setting operation 2, the capacitor is discharged through the second transistor by turning off the second switch and turning on the first switch while applying the first input potential to the input terminal. The discharge of the capacitance through the second transistor is performed until the current through the second transistor is substantially zero, that is, until the voltage across the capacitance is approximately equal to the threshold voltage of the second transistor. The The predetermined potential is such a potential that the second transistor is turned on when the first switch is turned on in the second setting operation. For example, the second power supply potential is different from the first power supply potential. It can be. Typically, the first input potential is equal to the first power supply potential, and the second input potential is equal to the second power supply potential.

  By setting the voltage across the capacitor as described above, in normal operation, when the first input potential is applied to the input end, the potential difference between the control terminal of the first transistor and the first terminal is the first. The first transistor is turned off when the second input potential is applied, so that the voltage across the capacitor promotes the first transistor on when the second input potential is applied. Superposed on the potential, a sufficient current can be supplied to the first transistor to turn it on at high speed.

  In addition, one terminal of the capacitor is connected to the input terminal via the third switch, and is connected to a potential substantially equal to the first input potential via the fourth switch. In normal operation, The third switch is on, the first, second, and fourth switches are off. In the first setting operation, the second and fourth switches are on, and the third switch is off. In the second setting operation, the second and third switches can be turned off, and the first and fourth switches can be turned on. In this way, the setting operation can be easily performed only by switching the switch without controlling the input potential. For example, when two transistors having different polarities are used as the first transistor, the setting operation of these transistors can be performed simultaneously.

  The switch circuit can take various forms such as an inverter circuit, a clocked inverter circuit, a logic circuit such as NAND or NOR, a level shift circuit, or a transfer gate. In the case of an inverter circuit, a transistor and a resistor may be used, a transistor having the same polarity may be used as a resistor by connecting one of the diodes, or a CMOS using two MOSFETs having different polarities It can also be an inverter. In the case of a clocked inverter circuit, the transistor provided with the correction circuit may be a transistor constituting the inverter main body, a clock signal synchronizing transistor, or both transistors.

  The above-described switch (such as the first switch connected in series to the diode-connected second transistor) may be an electrical switch or a mechanical switch that can control the flow of current. It may be a transistor, a diode, or a logic circuit combining them. It is preferable that the switch is made of a semiconductor element such as a MOSFET because the entire digital circuit can be formed by a semiconductor process. Note that when the switch is formed of a transistor, the transistor is only used as a switch, and the conductivity type of the transistor is not limited. However, when it is desirable that the off-state current is small, it is desirable to use a transistor having a polarity with a small off-state current. As a transistor with low off-state current, there is a transistor provided with an LDD region. Further, when the transistor operated as a switch operates at a source terminal potential close to a low-potential power supply (Vss, Vgnd, OV, etc.), the n-channel type is used. When operating in a state close to a side power supply (Vdd or the like), it is desirable to use a p-channel type. This is because the absolute value of the gate-source voltage can be increased, so that it can easily operate as a switch. Note that a CMOS switch may be formed using both an n-channel type and a p-channel type.

  Further, a further switch may be connected in parallel with the capacitor in order to prevent undesired charges accumulated in the capacitor due to noise or the like from adversely affecting the setting operation. By turning on this switch prior to the setting operation, the charge accumulated in the capacitor can be discharged.

  Various semiconductor devices (or electronic devices) typified by an integrated circuit or a semiconductor display device can be preferably realized by using a digital circuit including a switch circuit including a transistor as described above. Such a semiconductor device includes, for example, a liquid crystal display device, a self-luminous display device having an organic EL display light-emitting element in each pixel, a DMD (Digital Micromirror Device), a PDP (Plasma Display Panel), and an FED (Field Emission Display). The digital circuit of the present invention can be used for such a drive circuit. By applying the digital circuit of the present invention to a semiconductor device formed using a glass substrate, it is not necessary to control the amplitude of a signal input from the IC with a booster circuit. Cost can be reduced.

  A digital circuit according to the present invention includes a switch circuit having a first transistor such as a MOSFET to which a power supply potential is supplied, and an input terminal to which an input signal is applied and a control terminal (gate) of the first transistor. A correction circuit connected to the capacitor; a) a capacitor connected between the control terminal and the input terminal of the first transistor; and b) storage in the capacitor in the setting operation prior to the normal operation. And at least one switch for defining a conductive path for setting the voltage to be charged at a predetermined value, and in normal operation, the state of the at least one switch is It was set to save voltage. As a result, there is a difference between the input potential level and the power supply potential level (for example, the high level input potential is lower than the high level power supply potential), and the switch circuit does not operate normally without the correction circuit, or the power supply voltage is a transistor. If the transistor is not sufficiently large (for example, the power supply voltage is 3.3 V and the transistor threshold voltage is 3 V), and high-speed operation of the transistor is difficult, the voltage across the capacitor is set appropriately in the setting operation. In addition, by maintaining the set voltage (or charge) in the normal operation, it is possible to appropriately correct the DC level of the input signal and realize a suitable circuit operation. Since the charge of the capacitor is held in normal operation, there is no concern that the capacitor adversely affects the dynamic characteristics of the digital circuit (that is, the operation speed is reduced). Rather, the capacitor is connected in series with the parasitic capacitance of the transistor and reduces the total capacitance, which can contribute to the improvement of dynamic characteristics. Further, since it is not necessary to frequently perform the setting operation, power consumption associated with the setting operation is small. Preferably, the correction circuit is provided between the node between the capacitor and the control terminal of the first transistor and the power supply potential so that the voltage of the capacitor can reflect the threshold voltage of the corresponding transistor. In addition, a diode-connected second transistor having substantially the same threshold voltage as the first transistor, and a switch connected in series to the diode-connected second transistor.

  The features, objects, and advantages of the present invention will become more apparent from the following description of preferred embodiments with reference to the accompanying drawings.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a schematic configuration of a digital circuit according to the present invention. As shown in the figure, the digital circuit 1 according to the present invention is connected between the input terminal IN and the output terminal OUT, and a different signal (for example, a high level) is applied to the output terminal according to the value of the input signal applied to the input terminal. A switch circuit 2 having a transistor such as a MOSFET that outputs a power supply potential VDD or a low-level power supply potential VSS) and a correction circuit 3 connected between the input terminal IN and the switch circuit 2.

FIG. 2 is a circuit diagram showing an embodiment of a digital circuit according to the present invention. The digital circuit 10 includes an inverter circuit 12 including a single P-type MOSFET 11 and a resistor R1 as a switch circuit. The P-type MOSFET 11 has a threshold voltage V _THP , its source is connected to the high level power supply potential VDD, and its drain is connected to the low level power supply potential VSS (for example, the ground potential V _GND ) via the resistor R1. . A gate serving as a control terminal of the P-type MOSFET 11 is connected to an input terminal IN to which an input signal having an amplitude between the high level input potential _VINH and the low level input potential _VINL is applied, and a node between the drain and the resistor R1. N1 is connected to the output terminal OUT.

A correction circuit 13 is connected between the gate of the P-type MOSFET 11 and the input terminal IN. The correction circuit 13 includes a capacitor C1 connected between the gate of the P-type MOSFET 11 and the input terminal IN, and a P for setting operation having the same threshold voltage V _THP as the P-type MOSFET 11 and P-type. A type MOSFET 14 and a switch SW1 are provided. The drain of the P-type MOSFET 14 is connected to the node N2 between the capacitor C1 and the gate of the P-type MOSFET 11, and the source is connected to the high level power supply potential VDD via the switch SW1. The switch SW1 may be provided between the drain of the P-type MOSFET 14 and the node N2, and may be connected to the P-type MOSFET 14 in series. Further, the gate and drain of the P-type MOSFET 14 are connected to form a so-called “diode connection”. Thereby, the gate-source voltage V _GS of the P-type MOSFET 14 becomes equal to the source-drain voltage V _DS .

The operation of the digital circuit 10 configured as described above will be described below. For the sake of explanation, in this embodiment, the high level input potential V _INH of the input signal applied to the input terminal IN is lower than the value obtained by subtracting the absolute value | V _THP | of the threshold voltage from the high level power supply potential VDD. (i.e., values such as P-type MOSFET11 is not turned off when the input signal is high-level input potential _{V INH} in the conventional circuit), a low-level input potential _{V INL} is equal to the ground potential _{V GND} (i.e., to turn on the P-type MOSFET11 Low enough).

First, in the setting operation, as shown in FIG. 3A, the switch SW1 is turned on, and in this state, the high level input potential _VINH is applied to the input terminal IN. As a result, a current flows through the P-type MOSFET 14 as indicated by an arrow in the figure, and the capacitor C1 is charged. When a sufficient time has elapsed, the voltage across the capacitor C1 rises, whereby the absolute value of the gate-source voltage V _GS of the P-type MOSFET 14 decreases, and finally the P-type MOSFET 14 turns off and the current stops. . At this time, the voltage across the capacitor C1 becomes VDD−V _INH − | V _THP |.

After the capacitor C1 is appropriately charged in the setting operation in this way, in the normal operation, as shown in FIG. 3b, the switch SW1 is turned off, and the input terminal IN is connected between the high level input potential _VINH and the low level input potential _VINL . Apply an amplitude input signal. At this time, since the switch SW1 is off, the electric charge accumulated in the capacitor C1 is stored, and the voltage across the capacitor C1 is kept constant. Therefore, when the high-level input potential _VINH is applied to the input terminal IN, the voltage VDD−V _INH − | V _THP | between both ends of the capacitor C1 is added thereto, and the potential of the gate of the P-type MOSFET 11 is VDD− | V. _{Since THP} | and the gate-source voltage V _GS = − | V _THP |, the P-type MOSFET 11 can be reliably turned off without leakage current. As a result, the ground potential V _GND is output to the output terminal OUT. It is not necessary to perform the setting operation until the P-type MOSFET 14 is completely turned off (that is, until the current flowing through the P-type MOSFET 14 is completely zero). Even if a small amount of current flows in the P-type MOSFET 14, if the capacitor C1 is sufficiently charged to properly correct the input signal in normal operation (that is, if the P-type MOSFET 14 is substantially turned off), at that time There is no problem in actual operation even if the setting operation is finished.

On the other hand, when the low-level input potential _VINL is applied to the input terminal IN, the gate potential of the P-type MOSFET 11 is lower than when the high-level input potential _VINH is applied to the input terminal IN, and V _GS = − | V _THP | − (V _INH −V _INL ), and therefore V _GS <− | V _THP |, the P-type MOSFET 11 is turned on, and the potential of the output terminal OUT is approximately the high-level power supply potential VDD. If the capacitance C1 is not sufficiently large with respect to the gate capacitance of the P-type MOSFET 11, the input voltage (V _INH , V _INL ) is _divided by the capacitance C1 and the gate capacitance, and a sufficient voltage is applied to the gate of the P-type MOSFET 11. Will disappear. Therefore, the size of the capacitor C1 is desirably determined in consideration of the gate capacitance of a transistor such as the P-type MOSFET 11 to which the capacitor C1 is connected. For example, it is desirable that the capacitance C1 be 5 times or more the gate capacitance of the P-type MOSFET 11.

As described above, in the above-described embodiment, even when the high-level input potential _VINH is lower than the high-level power supply potential VDD as the first power supply potential, the gate and the input terminal IN of the P-type MOSFET 11 constituting the inverter circuit 12 In the setting operation, the capacitor C1 connected between the P-type MOSFET 11 and the P-type MOSFET 11 is charged to an appropriate voltage through the diode-connected setting operation P-type MOSFET 14 having substantially the same threshold voltage. The type MOSFET 11 can be reliably turned off. According to the present invention, it is not necessary to provide a separate booster, which contributes to cost reduction and downsizing of the device. Even when a signal from an IC is input to a digital circuit formed on a glass substrate, the signal can be directly input to the digital circuit without using a booster circuit. In the above embodiment, when the high level input potential _VINH is equal to or higher than the high level power supply potential VDD, the capacitor C1 is not charged in the setting operation, and the normal operation can be normally performed.

  When a plurality of such digital circuits 10 are used, for example, in a driving device for a liquid crystal display or an organic EL display, a plurality of P-type MOSFETs 11 constituting each inverter circuit 12 are included. There are cases where variations occur in the threshold voltages due to different states or the like. However, according to the present invention, the threshold voltage of the diode-connected P-type MOSFET 14 included in the correction circuit 13 corresponding to each P-type MOSFET 11 is made substantially the same as that of the P-type MOSFET 11 constituting the inverter circuit 12. The DC level conversion capacitor C1 included in the correction circuit 13 can be charged so as to supply an appropriate voltage that matches the threshold voltage of the corresponding P-type MOSFET 11. As described above, the threshold voltages of the P-type MOSFET 11 and the setting operation P-type MOSFET 14 constituting the inverter circuit 12 are set to substantially the same value. In an actual semiconductor circuit, these P-type MOSFETs 11 and 14 are brought close to each other. It can be realized by providing and avoiding a difference in impurity concentration. Further, in the case of including a manufacturing process in which the channel portion is crystallized by laser irradiation, when the channel portions of the P-type MOSFET 11 and the P-type MOSFET 14 are crystallized by a laser beam spot having the same pulse, the threshold voltage is made closer. This is desirable because it is possible. In order to easily realize substantially the same threshold voltage, it is preferable that the P-type MOSFETs 11 and 14 have substantially the same channel length L, channel width W, etc., but the threshold voltages are substantially the same. If so, the sizes of the P-type MOSFET 11 and the P-type MOSFET 14 may be different. For example, in order to suppress the layout area, the channel length and / or the channel width W of the P-type MOSFET 14 can be reduced. Alternatively, the channel width W of the P-type MOSFET 14 may be increased so that the setting operation can be performed in a shorter time.

  In the above embodiment, since the switch SW1 connected in series to the diode-connected P-type MOSFET 14 in the normal operation is turned off, the charge accumulated in the capacitor C1 of the correction circuit 13 in the setting operation is stored. In operation, there is no concern that the capacitor C1 adversely affects the dynamic characteristics of the digital circuit 10 (that is, reduces the operation speed). Rather, the capacitance C1 is connected in series with the parasitic capacitance formed between the gate and drain or source of the P-type MOSFET 11 and reduces the total capacitance, which can contribute to improvement of dynamic characteristics. The setting operation may be performed before the charge accumulated in the capacitor C1 leaks and normal operation cannot be ensured. Therefore, it is not necessary to frequently perform the setting operation, so that power consumption associated with the setting operation is small. In the circuit connected to the input side of the digital circuit 10, the operating voltage (power supply voltage or signal voltage) can be lowered, which also contributes to power consumption suppression.

FIG. 4 is a circuit diagram showing another embodiment of the digital circuit according to the present invention including a level shift circuit using one P-type MOSFET as a switch circuit. In this figure, parts similar to those in FIG. The digital circuit 20 of FIG. 3 has substantially the same configuration as the digital circuit 10 shown in FIG. 2, but the drain of the P-type MOSFET 11 is connected to the ground potential V _GND as the low-level power supply potential VSS, and the source has the resistor R1. The output terminal OUT is connected to the node N3 between the source of the P-type MOSFET 11 and the resistor R1, thereby forming a level shift circuit 21 as a switch circuit. Although the description is omitted, in this embodiment as well, by performing the same setting operation as in the above embodiment and appropriately charging the capacitor C1, the P-type MOSFET 11 can be reliably turned on / off without malfunction in normal operation. Is possible. In this example, when the high-level input potential _VINH is applied to the input terminal IN, the P-type MOSFET 11 is turned off, the high-level power supply potential VDD is output to the output terminal OUT, and the low-level input potential _VINL is applied. And the P-type MOSFET 11 is turned on, and the low-level power supply potential VSS is output to the output terminal OUT. As described above, various types of switching circuits are conceivable in which different signals are supplied to the output terminal OUT in accordance with the on / off state of the transistors. However, the transistors included in the switching circuit are reliably turned on / off. Therefore, it should be understood that the present invention can be applied to them.

FIG. 5 is a circuit diagram showing an example in which the present invention is applied to a CMOS inverter circuit as still another embodiment of the digital circuit according to the present invention. The digital circuit 30 has a CMOS inverter circuit 31 as a switch circuit. As in the prior art, the CMOS inverter circuit 31 includes a P-type MOSFET 32 having a threshold voltage V _THP connected in series between a high-level power supply potential VDD as a power supply potential and a low-level power supply potential VSS, and a threshold value. And an N-type MOSFET 33 having a voltage V _THN . The source of the P-type MOSFET 32 is connected to the high level power supply potential VDD, and the source of the N-type MOSFET 33 is connected to the low level power supply potential VSS (in this example, the ground potential V _GND ). The drains of the MOSFETs 32 and 33 are connected to each other, and the connection point (node) N4 is connected to the output terminal OUT. The gates of these MOSFETs 32 and 33 are both connected to an input terminal IN to which an input signal that swings between a high level input potential _VINH and a low level input potential _VINL is applied.

In accordance with the present invention, a correction circuit 34 is connected between the gate of the P-type MOSFET 32 and the input terminal IN. Similar to the correction circuit 13 of the embodiment shown in FIG. 2, the correction circuit 34 has a capacitance C2 connected between the gate of the P-type MOSFET 32 and the input terminal IN, the same conductivity type as the P-type MOSFET 32, and A P-type MOSFET 35 for setting operation having substantially the same threshold voltage V _THP and a switch SW2 are provided. The drain of the P-type MOSFET 35 is connected to the node N5 between the capacitor C2 and the gate of the P-type MOSFET 32, and the source is connected to the high-level power supply potential VDD via the switch SW2. Further, the P-type MOSFET 35 has a gate and drain connected, and is diode-connected. The switch SW2 only needs to be connected in series with the P-type MOSFET 35 as in the case of FIG.

A correction circuit 36 is connected between the gate of the N-type MOSFET 33 and the input terminal IN. The correction circuit 36 has a capacitor C3 connected between the gate of the N-type MOSFET 33 and the input terminal IN, and an N-type for setting operation having the same conductivity type as the N-type MOSFET 33 and substantially the same threshold voltage V _THN. It has a MOSFET 37 and a switch SW3. The drain of the N-type MOSFET 37 is connected to a node N6 between the capacitor C3 and the gate of the N-type MOSFET 33, and the source is connected to the low level power supply potential VSS via the switch SW3. Further, the N-type MOSFET 37 has a gate and drain connected and is diode-connected. The switch SW3 may be provided between the N-type MOSFET 37 and the node N6.

The operation of the digital circuit 30 configured as described above will be described below with reference to FIG. For the sake of explanation, the high-level input potential V _INH of the input signal applied to the input terminal IN is lower than the value obtained by subtracting the absolute value | V _THP | of the threshold voltage of the P-type MOSFET 32 from VDD. The potential V _INL is higher than the value obtained by adding the absolute value | V _THL | of the threshold voltage of the N-type MOSFET 33 to the low-level power supply potential VSS (V _GND ).

As shown in FIG. 6a, when the switch SW2 is turned on and the switch SW3 is turned off and a high level input potential _VINH is applied to the input terminal IN, the current flows in the direction indicated by the arrow through the diode-connected P-type MOSFET 35. Flows, the capacitor C2 connected to the gate of the P-type MOSFET 32 is charged, and when the voltage across the capacitor C2 becomes VDD−V _INH − | V _THP |, the P-type MOSFET 35 is turned off and the current stops (P Channel setting operation). Subsequently, as shown in FIG. 6b, when the switch SW2 is turned off and the switch SW3 is turned on and the low-level input potential _VINL is applied to the input terminal IN, the direction indicated by the arrow through the diode-connected N-type MOSFET 37 When the capacitor C3 connected to the gate of the N-type MOSFET 33 is charged and the voltage across the capacitor C3 becomes VSS−V _INL + | V _THN |, the N-type MOSFET 37 is turned off and the current stops ( N channel setting operation).

After the capacitors C2 and C3 are appropriately charged in the setting operation in this way, in the normal operation, both the switches SW2 and SW3 are turned off, and the amplitude between the high level input potential _VINH and the low level input potential _VINL is applied to the input terminal IN. Apply a pulse input signal. At this time, since the switches SW2 and SW3 are turned off, the charges accumulated in the capacitors C2 and C3 are stored, and the voltages at both ends of the capacitors C2 and C3 are kept constant. When the high-level input potential V _INH is applied to the input terminal IN, the gate potential of the P-type MOSFET 32 becomes VDD− | V _THP | and the gate-source voltage V _GS = − | V _THP | The MOSFET 32 can be turned off. At this time, since the N-type MOSFET 33 is turned on, the low-level power supply potential VSS (ground potential V _GND ) is output to the output terminal OUT. On the other hand, when the low-level input potential V _INL is applied to the input terminal IN, the gate potential of the N-type MOSFET 33 becomes VSS + | V _THN |, and the gate-source voltage V _GS = | V _THN | The MOSFET 33 can be turned off. At this time, since the P-type MOSFET 32 is turned on, the high-level power supply potential VDD is output to the output terminal OUT. Even if the setting operation is not performed until the P-type MOSFET 35 and the N-type MOSFET 37 are completely turned off, the current flowing through the MOSFETs 35 and 37 becomes sufficiently small (that is, the MOSFETs 35 and 37 are substantially turned off). May be terminated). In the above embodiment, the setting operation of the N-type MOSFET 37 is performed after the setting operation of the P-type MOSFET 35. However, the order is not limited to this order, and the setting operation of the N-type MOSFET 37 may be performed first. .

Thus, when the present invention is applied to a pair of P-type MOSFET32 and N type MOSFET33 constituting the CMOS inverter circuit 31, the high-level input potential _{V INH} is lower than a high level power supply potential VDD, a low-level input potential _{V INL} is Even when the voltage is higher than the low level power supply potential VSS, the threshold voltages and the input potential V _INH of the MOSFETs 32 and 33 are set in the setting operation of the capacitors C2 and C3 connected between the gates of the P-type MOSFET 32 and the N-type MOSFET 33 and the input terminal IN. Thus, by charging to an appropriate voltage that matches the difference between _VINL and the power supply potentials VDD and VSS, the P-type and N-type MOSFETs 32 and 33 can be reliably turned on / off, and an accurate circuit operation can be realized.

FIG. 7 is a circuit diagram of a digital circuit 30 in which the switches SW2 and SW3 shown in FIG. 5 are implemented by a P-type MOSFET 38 and an N-type MOSFET 39, respectively. In this figure, the same parts as those in FIG. The gate of the P-type MOSFET 38 and the gate of the N-type MOSFET 39 are connected to the P-channel control signal line 40 and the N-channel control signal line 41, respectively. In the P channel setting operation, the potential of the control signal lines 40 and 41 is made equal to the low level power supply potential VSS, for example, and the low level power supply potential VSS is applied to the gates of the P type MOSFET 38 and the N type MOSFET 39, thereby the N-type MOSFET39 is turned off while the on state, applying a high-level input potential _{V INH} further input iN. In the N-channel setting operation, the potential of the control signal lines 40 and 41 is made equal to, for example, the high-level power supply potential VDD, the high-level power supply potential is applied to the gates of the P-type MOSFET 38 and N-type MOSFET 39, and the P-type MOSFET 38 is turned off. with the N-type MOSFET39 is turned on, adding a low-level input potential _{V INH} to the input terminal iN. With these setting operations, as described with reference to FIGS. 6a and 6b, charges are appropriately stored in the capacitors C2 and C3. In normal operation, the potential of the P-channel control signal line 40 is equal to the high-level power supply potential VDD, the potential of the N-channel control signal line 41 is equal to the low-level power supply potential VSS, and both the P-type MOSFET 38 and the N-type MOSFET 39 are turned off. State.

  Note that the capacitors C2 and C3 can be formed using a capacitor formed between the gate and source and / or drain of one or a plurality of MOSFETs, as shown in an enlarged view in FIG. When a MOSFET used as a capacitor is connected, it should be connected in such a direction that the MOSFET is turned on when charged (that is, a channel is formed). For example, when the capacitor C2 in FIG. 7 is connected by one P-type MOSFET, the gate side terminal may be connected to the input terminal IN and the source / drain side terminal may be connected to the gate of the P-type MOSFET 32. The conductivity type of the MOSFET used as the capacitor may be either N-type or P-type, but the threshold voltage is preferably close to 0.

  In the digital circuit 30 described above, it has been described that no charge is accumulated in the capacitors C2 and C3 before the setting operation. However, for example, charges may be accumulated in the capacitors C2 and C3 due to noise or the like. For example, when the capacitors C2 and C3 are excessively charged with the polarity shown in FIG. 6b prior to the setting operation due to such charges, even if the switches SW2 and SW3 are turned on in the setting operation, the diode-connected MOSFETs 35 and 37 are connected. Is not turned on, and the charges accumulated in the capacitors C2 and C3 (therefore, the voltages at both ends of the capacitors C2 and C3) are maintained as they are, and the voltages at both ends of the capacitors C2 and C3 (or the potentials of the gates of the MOSFETs 32 and 33) are maintained. It may not be possible to converge to an appropriate value. Therefore, even when such undesired charges are accumulated in the capacitors C2 and C3, it is desirable to take measures to set the voltages across the capacitors C2 and C3 to appropriate values.

FIG. 8 is a circuit diagram showing a modified embodiment of the digital circuit 30 shown in FIG. 5. In FIG. 8, the same parts as those in FIG. In this digital circuit 30 a, another diode-connected P-type MOSFET 42 is connected in parallel with the diode-connected P-type MOSFET 35 so that its forward direction is opposite to the forward direction of the P-type MOSFET 35. Similarly, another N-type MOSFET 43 diode-connected in parallel and in the opposite direction is connected to the diode-connected N-type MOSFET 37. Thus, for example, when charges that can reverse bias the diode-connected P-type and N-type MOSFETs 35 and 37 are accumulated in the capacitors C2 and C3 due to the influence of noise or the like before the setting operation, When the switches SW2 and SW3 are turned on, current can flow as shown by arrows in FIG. 8, and the voltages at both ends of the capacitors C2 and C3 can be converged to an appropriate value. When the threshold voltages of the diode-connected MOSFETs 42 and ₄₃ are equal to the threshold voltages V _THP and V _THN of the MOSFETs 32 and 33, respectively, the potential of the gate of the P-type MOSFET 32 (that is, the potential of the node N5) is VDD + | V _THP. |, The gate potential of the N-type MOSFET 33 (ie, the potential of the node N6) converges to VSS− | V _THN |. Instead of the diode-connected MOSFETs 42 and 43, another rectifying element such as a diode may be used. The diode-connected MOSFET 42 connected in parallel with the P-type MOSFET 35 may be an N-type. The diode-connected MOSFET 43 connected in parallel with the N-type MOSFET 37 may be P-type.

  FIG. 9 is a circuit diagram showing another modified embodiment of the digital circuit 30 shown in FIG. 5. In FIG. 9, the same parts as those in FIG. In the digital circuit 30b, switches SW4 and SW5 are provided in parallel with the capacitors C2 and C3, respectively. Accordingly, even if undesired charges are accumulated in the capacitors C2 and C3 due to, for example, noise, the switches SW4 and SW5 can be turned on before the setting operation to discharge the capacitors C2 and C3. Accordingly, when the switches SW2 and SW3 are turned on in the setting operation, the diode-connected MOSFETs 35 and 37 are surely turned on, and the capacitors C2 and C3 are appropriately charged.

  FIG. 10 is a circuit diagram showing still another modified embodiment of the digital circuit 30 shown in FIG. 5. In FIG. 10, the same parts as those in FIG. In the digital circuit 30c, a node N5 between the gate of the P-type MOSFET 32 and the capacitor C2 is connected to the low level power supply potential VSS via the switch SW6, and a node N6 between the gate of the N-type MOSFET 33 and the capacitor C3 is connected. The switch SW7 is connected to the high level power supply potential VDD.

  As shown in FIG. 11a, when the switch SW6 is turned on in the initialization operation before the setting operation (P channel setting operation) of the capacitor C2 connected to the gate of the P-type MOSFET 32, the capacitor C2 is unnecessary due to noise or the like. Even if charges accumulate and the potential of the node N5 between the gate of the P-type MOSFET 32 and the capacitor C2 becomes undesirably high, the potential of the node N5 can be lowered to the low-level power supply potential VSS. At this time, the potential of the input terminal IN is preferably a high level input potential, but may be a low level input potential. In addition, the switch SW2 may be in an on state or an off state. However, in the on state, a current flows as shown by a dotted arrow in the drawing, and it is difficult to lower the potential of the node N5 to a sufficiently low potential. Is more desirable.

  Similarly, as shown in FIG. 11b, when the switch SW7 is turned on in the initialization operation before the setting operation (N-channel setting operation) of the capacitor C3 connected to the gate of the N-type MOSFET 33, the capacitance C3 is changed to, for example, noise. Even if unnecessary charges accumulate and the potential of the node N6 between the gate of the N-type MOSFET 33 and the capacitor C3 is undesirably lowered, the potential of the node N6 can be raised to the high level power supply potential VDD. At this time, the potential of the input terminal IN is preferably a low level input potential, but may be a high level input potential. Further, the switch SW3 may be in an on state or an off state, but in the on state, a current flows as shown by a dotted arrow in the figure, and it is difficult to raise the potential of the node N6 to a sufficiently high potential. Is more desirable.

  In the setting operation, the switches SW6 and SW7 are turned off, and the switch SW2 or SW3 is turned on as described with reference to FIGS. 6a and 6b. By setting the potentials of the nodes N5 and N6 to appropriate values prior to the setting operation by the initialization operation as described above, when the switches SW2 and SW3 are turned on in the setting operation, the diode-connected MOSFETs 35 and 37 are sequentially switched. The capacitors C2 and C3 can be appropriately charged by biasing in the direction and turning on with certainty and allowing current to flow through the MOSFETs 35 and 37. 10 and 11, the node N5 is connected to the low-level power supply potential VSS and the node N6 is connected to the high-level power supply potential VDD in the initialization operation. However, the node N6 is diode-connected in the setting operation after the initialization operation. As long as the MOSFETs 35 and 37 are forward biased and turned on, they may be connected to another potential other than the power supply potential. However, it is preferable to use a power supply potential because such a potential can be easily secured. In the above embodiment, the P-channel initialization operation and the N-channel initialization operation are performed separately, but can also be performed at once by simultaneously turning on the switches SW6 and SW7.

  FIG. 12 is a circuit diagram showing a digital circuit 30c in which the switches SW2, SW3, SW6, SW7 shown in FIG. 10 are implemented as MOSFETs 44, 45, 46, 47. The MOSFET 44 is a P-type MOSFET, and its gate is connected to a P-channel control signal line 48. The MOSFET 45 is an N-type MOSFET, and its gate is connected to an N-channel control signal line 49. The MOSFET 46 is an N-type MOSFET, and its gate is connected to the P-channel initialization signal line 50. The MOSFET 47 is a P-type MOSFET, and its gate is connected to the N-channel initialization signal line 51. By appropriately controlling the potentials of the control signal lines 48 and 49 and the initialization signal lines 50 and 51, the MOSFETs 44 to 47 can be appropriately turned on and off to perform the initialization, setting, and normal operation as described above. Is possible. Thus, each switch can be realized by an appropriate semiconductor element.

FIG. 13 is a circuit diagram showing still another modified embodiment of the digital circuit 30 shown in FIG. In this figure, the same parts as those shown in FIG. In the digital circuit 30d, a terminal on the opposite side to that connected to the gate of the P-type MOSFET 32 of the capacitor C2 is connected to the input terminal IN via the switch SW8 and input in normal operation via the switch SW9. It is generally connected to the same potential V _H and the high level input potential V _INH input signal applied to the end iN. Similarly, the terminal on the opposite side of the capacitor C3 connected to the gate of the N-type MOSFET 33 is connected to the input terminal IN through the switch SW10, and in addition to the input terminal IN in the normal operation through the switch SW11. _Is connected to the same potential V _L as the low level input potential V _INL of the input signal.

In this embodiment, the switches SW2, SW3, SW9, and SW11 are turned on and the switches SW8 and SW10 are turned off, so that the setting operations of the capacitors C2 and C3 are performed simultaneously and without depending on the potential of the input terminal IN. be able to. In normal operation, the switches SW2, SW3, SW9, and SW11 are turned off, the switches SW8 and SW10 are turned on, and an input signal that swings between the high level / low level input potentials _VINH and _VINL is applied to the input terminal IN. .

  By the way, in a CMOS inverter, MOSFETs are connected in series to P-type and N-type MOSFETs constituting the inverter, and these MOSFETs are turned on / off by a clock signal (or a synchronous signal such as a clock bar signal having a phase opposite to that). It is known that the output of an inverter is synchronized with a synchronization signal such as a clock signal. Such an inverter is called a clocked inverter. The present invention can also be applied to a clock signal synchronization MOSFET connected in series to P-type and N-type MOSFETs constituting a CMOS inverter in a clocked inverter. Such an embodiment is shown in FIG. Show.

The clocked inverter circuit (digital circuit) 60 shown in FIG. 14 has P-type and N-type MOSFETs 61 and 62 constituting a CMOS inverter, and the gates of these MOSFETs 61 and 62 are connected to the input terminal IN and are common. The output terminal OUT is connected to the drain. The source of the P-type MOSFET 61 is connected to the high-level power supply potential VDD through the clock synchronization P-type MOSFET 63, and the source of the N-type MOSFET 62 is connected to the low-level power supply potential VSS through the clock synchronization N-type MOSFET 64 (this In the example, it is connected to the ground potential V _GND ). The gate of the P-type MOSFET 63 is connected to a clock bar signal line 65 that supplies a clock bar signal, and the gate of the N-type MOSFET 64 is connected to a clock signal line 66 that supplies a clock signal. Clock signal and the clock bar signal shall be amplitude between a high level power supply potential VDD lower than the high level potential V _CH, the low-level power supply potential VSS higher than the low level potential V _CL. In this embodiment, the input signal applied to the input terminal IN has an amplitude between the high-level power supply potential VDD and the low-level power supply potential VSS. However, when the amplitude of the input signal is small, the above-described embodiment Similarly to the above, it is possible to provide a correction circuit for the MOSFETs 61 and 62 constituting the inverter. The P-type MOSFET 61 may be connected between the P-type MOSFET 63 and the power supply potential VDD, and the N-type MOSFET 62 may be connected between the N-type MOSFET 64 and the power supply potential VSS.
In accordance with the present invention, a correction circuit 67 is connected between the gate of the P-type MOSFET 63 and the clock bar signal line 65. The correction circuit 67 includes a capacitor C4 connected between the gate of the P-type MOSFET 63 and the clock bar signal line 65, a diode-connected P-type MOSFET 68 having substantially the same threshold voltage as the P-type MOSFET 63, a switch The drain of the P-type MOSFET 68 is connected to the node N7 between the capacitor C4 and the gate of the P-type MOSFET 63, and the source is connected to the high level power supply potential VDD via the switch SW12.

  Similarly, a correction circuit 69 is connected between the gate of the N-type MOSFET 64 and the clock signal line 66. The correction circuit 69 includes a capacitor C5 connected between the gate of the N-type MOSFET 64 and the clock signal line 66, a diode-connected N-type MOSFET 70 having substantially the same threshold voltage as the N-type MOSFET 64, and a switch SW13. The drain of the N-type MOSFET 70 is connected to the node N8 between the capacitor C5 and the gate of the N-type MOSFET 64, and the source is connected to the low-level power supply potential VSS via the switch SW13.

  In this embodiment, the clock signal and the clock bar signal can be said to be input signals in the present invention when viewed from the target MOSFETs 63 and 64. Further, it can be said that the digital circuit of the present invention is formed by the P-type MOSFET 63 and the correction circuit 67 or by the N-type MOSFET 64 and the correction circuit 69. In this case, the drains of the P-type MOSFET 63 and the N-type MOSFET 64 are output. It can be regarded as an end.

In the setting operation, first, the switch SW12 and the switch SW13 are both turned on, and the high level potential _VCH is applied as the clock bar signal (at this time, the clock signal becomes the low level potential _VCL ). Since the high-level potential V _CH is lower than a high level power supply potential VDD, it turns on P-type MOSFET68 the diode-connected is forward biased, the capacitor C4 is charged current flows. The current flows until the voltage across the capacitor C4 is large enough to turn off the P-type MOSFET 68. At this time, since a low level potential V _CL higher than the low level power supply potential VSS is applied as a clock signal, the diode-connected N-type MOSFET 70 is forward biased and turned on, and a current flows to charge the capacitor C5. Is done. When the voltage across the capacitor C5 becomes sufficiently large, the N-type MOSFET 70 is turned off and the current stops. Thus, in this embodiment, the setting operations of the capacitors C4 and C5 in the two correction circuits 67 and 69 can be performed simultaneously.

  In normal operation, both the switches SW12 and SW13 are turned off, and the clock signal, clock bar signal, and input signal are applied. Also in this case, the capacitors C4 and C5 are charged to an appropriate voltage that matches the threshold voltage of the P-type MOSFET 63 and the N-type MOSFET 64, and the clock signal and the clock bar signal are appropriately biased so that the P-type MOSFET 63 and the N-type MOSFET 64 Since it is added to the gate, the P-type MOSFET 63 and the M-type MOSFET 64 can be reliably turned on / off to synchronize the output signal with the clock signal.

  FIG. 15 is a circuit diagram showing a modified embodiment of the clocked inverter circuit 60 shown in FIG. In this figure, parts similar to those in FIG. As in the embodiment of FIG. 10, the clocked inverter circuit 60a of FIG. 15 uses nodes N7 and N8 between the capacitors C4 and C5 and the gates of the corresponding MOSFETs 63 and 64 as the low level power supply potential VSS and the high level power supply potential. Switches SW14 and SW15 for selectively connecting to VDD are provided. Thus, the correction capacitors C4 and C5 can be initialized by turning on the switches SW14 and SW15 prior to the setting operation, and even if undesired charges are accumulated in the capacitors C4 and C5 due to noise or the like. This prevents the MOSFETs 68 and 70 from being adversely affected.

FIG. 16 is a circuit diagram showing another modified embodiment of the clocked inverter circuit 60 according to the present invention shown in FIG. In this figure, parts similar to those in FIG. In the clocked inverter circuit 60b of FIG. 16, as in the embodiment of FIG. 13, the terminal on the opposite side to that connected to the gate of the P-type MOSFET 63 of the capacitor C4 is connected to the clock bar signal line 65 via the switch SW16. In addition, they are connected to the same potential V _H ′ as the high level potential V _CH of the clock bar signal through the switch SW17. Similarly, the terminal on the opposite side of the capacitor C5 connected to the gate of the N-type MOSFET 64 is connected to the clock signal line 66 via the switch SW18, and the low level potential V of the clock signal via the switch SW19. _{The CL} is connected to the substantially same potential V _L ′.

In this embodiment, the switches SW12, SW13, SW17, and SW19 are turned on and the switches SW16 and SW18 are turned off, so that the setting operation of the capacitors C4 and C5 can be performed simultaneously and the potentials of the clock signal and the clock bar signal can be obtained. Can be done without depending on. In normal operation, with the switches SW12, SW13, SW17, and SW19 turned off and the switches SW16 and SW18 turned on, the clock signal and the clock bar signal are applied to the gates of the P-type MOSFET 63 and the N-type MOSFET 64 through the capacitors C4 and C5. At the same time, an input signal having an amplitude between the high level input potential _VINH and the low level input potential _VINL is applied to the input terminal IN.

FIG. 17 schematically shows a main part of a driver circuit of an active matrix device used in, for example, a liquid crystal display or an organic EL display, and shows a typical unit circuit in a shift register of the driver circuit. The driver circuit 80 includes a shift register 81 for sequentially outputting a selection signal in synchronization with the clock signal and the clock bar signal, a first latch circuit 82 for latching the video signal based on the selection signal from the shift register 81, and a first And a second latch circuit 83 that latches data transferred from the latch circuit 82. The shift register 81 has a plurality of unit circuits 84, and each unit circuit 84 has two clocked inverters 85 and 86 and one inverter 87. For example, when the clock signal becomes the high level potential _VCH , the input is made. When the signal is taken in (the output signal can change at this time) and the clock signal becomes low level, the output signal is held. Since the clock signal and the clock bar signal are reversed in one unit circuit 84 and the adjacent unit circuit 84, when an input signal is captured by a certain unit circuit 84, the adjacent unit circuit 84 holds the output signal. When a unit circuit 84 holds an output signal, the adjacent unit circuit 84 takes in the input signal. Such a configuration and operation of the shift register 81 are well known in this field. It is assumed that the amplitude of the clock signal (or clock bar signal) applied to the clocked inverters 85 and 86 of the shift register 81 is smaller than the power supply voltage (high level power supply potential VDD−low level power supply potential VSS). In that case, it is preferable to take measures for reliably turning off these clocked inverters 85 and 86 without malfunction. By applying the present invention to these clocked inverters 85 and 86, such an object can be suitably achieved without reducing the operating speed.

  FIG. 18 is a circuit diagram showing an embodiment in which the present invention is applied to the left clocked inverter 85 in the unit circuit 84 of the shift register 81 shown in FIG. In the figure, the other clocked inverter 86 and inverter 87 are not shown.

The clocked inverter 85a on the left side of FIG. 18 (corresponding to the clocked inverter 85 in the unit circuit 84 on the left side in FIG. 17) includes a P-type MOSFET 91 connected in series with drains connected to form a CMOS inverter, and An N-type MOSFET 92 is provided, the P-type MOSFET 91 is connected to the high-level power supply potential VDD via the clock synchronization P-type MOSFET 93, and the N-type MOSFET 92 is connected to the low-level power supply potential VSS (for example, V-type) via the clock synchronization N-type MOSFET 94. _GND ).

  The gate of the P-type MOSFET 93 is connected to the clock bar signal line 95 via the correction circuit 97, and the gate of the N-type MOSFET 94 is connected to the clock signal line 96 via the correction circuit 98. The correction circuit 97 includes a capacitor C6 connected between the gate of the P-type MOSFET 93 and the clock bar signal line 95, a diode-connected P-type MOSFET 99 having substantially the same threshold voltage as the P-type MOSFET 93, and a selective circuit 97. P-type MOSFET 100 that functions as a switch for performing a setting operation at the same time. P-type MOSFET 99 and P-type MOSFET 100 are connected between node N9 between capacitor C6 and the gate of P-type MOSFET 93 and high-level power supply potential VDD. Connected in series. Similarly, the correction circuit 98 includes a capacitor C7 connected between the gate of the N-type MOSFET 94 and the clock signal line 96, a diode-connected N-type MOSFET 101 having substantially the same threshold voltage as the N-type MOSFET 94, The N-type MOSFET 101 and the N-type MOSFET 102 function as a switch for selectively performing the setting operation. The N-type MOSFET 101 and the N-type MOSFET 102 are connected to the node N10 between the capacitor C7 and the gate of the N-type MOSFET 94, and the low-level power supply potential VSS. Are connected in series. The gate of the P-type MOSFET 100 is connected to the first control signal line 104 via the inverter 103, and the gate of the N-type MOSFET 102 is directly connected to the first control signal line 104.

  Further, the node N9 between the capacitor C6 and the gate of the P-type MOSFET 93 is connected to the low level power supply potential VSS via the N-type MOSFET 106, and the node N10 between the capacitor C7 and the gate of the N-type MOSFET 94 is connected to P The capacitors C6 and C7 can be initialized by selectively turning on and off the N-type MOSFET 106 and the P-type MOSFET 107. The gate of the N-type MOSFET 106 is directly connected to the initialization signal line 108, the gate of the P-type MOSFET 107 is connected to the initialization signal line 108 via the inverter 109, and signals of opposite polarities are sent to the gates of these MOSFETs 106 and 107. It is designed to be entered.

  The right clocked inverter 85b in FIG. 18 (corresponding to the clocked inverter 85 in the right unit circuit 84 in FIG. 17) has the same structure as the left clocked inverter 85a, but the gate of the P-type MOSFET 93 has a capacitance. The gate of the N-type MOSFET 94 is connected to the clock bar signal line 95 via the capacitor C7, and the gates of the P-type MOSFET 100 and the N-type MOSFET 102 are connected to the second control signal line 105 via the C6. Is different. FIG. 18 shows only two clocked inverters 85a and 85b, but it should be understood that a plurality of them are alternately arranged in an actual circuit.

  A suitable signal (potential) change in each part in the initialization, setting operation, and normal operation of the clocked inverters 85a and 85b of the shift register 81 configured as described above is shown in the timing chart of FIG.

In the initialization operation, the potential of the clock signal line 96 is high, the potential of the clock bar signal line 95 is low, and the potentials of the first control signal line 104 and the second control signal line 105 are low. The potential of the activating signal line 108 becomes high level. As a result, the N-type MOSFET 106 and the P-type MOSFET 107 of each clocked inverter 85a, 85b are turned on, and the capacitors C6, C7 in the correction circuits 97, 98 are initialized. When the potential of the initialization signal line 108 becomes low level, the initialization operation ends. In this embodiment, the initialization operation is performed simultaneously for the left and right clocked inverters 85a and 85b. Therefore, in one initialization operation (right side in this example), the P-type MOSFET 93 is used in one clocked inverter 85b. can be applied to a capacitor connected C7 to the low level potential V _CL to the gate of the N type MOSFET94 applies a high level potential V _CH to capacitor C6 which is connected to the gate, the other (in this example the left ) in the clocked inverter 85a, the low-level potential _{V CL} is applied to the capacitor C6 which is connected to the gate of the P-type MOSFET 93, the high-level potential _{V CH} is applied to the capacitor C7 connected to the gate of the N-type MOSFET 94.

  In the setting operation, the first setting operation for accumulating charges in the capacitors C6 and C7 of the left clocked inverter 85a in FIG. 18 and the charge accumulation in the capacitors C6 and C7 in the right clocked inverter 85b in FIG. It consists of a second setting operation. In the first setting operation, in phase I, the potentials of the first control signal line 104 and the clock bar signal line 95 are at a high level, and the potentials of the second control signal line 105 and the clock signal line 96 are at a low level. Thereby, in the clocked inverter 85a on the left side, the P-type MOSFET 100 and the N-type MOSFET 102 are turned on, the setting operation of the capacitors C6 and C7 is performed, and the capacitors C6 and C7 are appropriately charged. In the right-side clocked inverter 85b, the P-type MOSFET 100 and the N-type MOSFET 102 are in the off state, so that the setting operation is not performed. In phase II, the potential of the first control signal line 104 becomes low level, and the MOSFETs 100 and 102 are turned off, so that the setting operation in the left clocked inverter 85a is completed.

  Subsequently, in the second setting operation, in the phase I, the potentials of the second control signal line 105 and the clock signal line 96 become high level, and the potential of the clock bar signal line 95 becomes low level. As a result, the P-type MOSFET 100 and the N-type MOSFET 102 of the right-side clocked inverter 85b are turned on, and the setting operations of the capacitors C6 and C7 are performed. In phase II, the potential of the second control signal line 105 becomes low level, and the setting operation in the right clocked inverter 85b is completed. Thus, in the normal operation, the clocks are stored in the state where the electric charges accumulated in the capacitors C6 and C7 of the clocked inverters 85a and 85b are stored by keeping the potentials of the first and second control signal lines 104 and 105 at a low level. A clock signal is supplied to the signal and clock bar signal lines 96,95.

  FIG. 20 is a circuit diagram showing a modified embodiment of the shift register 81 including the clocked inverters 85a and 85b shown in FIG. In this figure, the same reference numerals are given to the same portions as in FIG. In the embodiment shown in FIG. 20, a second initialization signal line 108a is provided in addition to the initialization signal line 108 (referred to as the first initialization signal line), and the gates of the initialization MOSFETs 106 and 107 of the right clocked inverter 85b. Is connected to the second initialization signal line 108a, and the initialization operation in the left clocked inverter 85a and the right clocked inverter 85b can be performed separately from the embodiment of FIG.

  FIG. 21 is a timing chart showing a preferred signal (potential) change of each part in the initialization, setting operation, and normal operation in the embodiment of FIG. As shown, in this embodiment, the first initialization operation is performed before the first setting operation for accumulating charges in the capacitors C6 and C7 of the left clocked inverter 85a in FIG. A second initialization operation is performed before the second setting operation for accumulating charges in the capacitors C6 and C7 of the clocked inverter 85b.

  In the first initialization operation, the potential of the clock signal line 96 is low, the potential of the clock bar signal line 95 is high, and the potentials of the first control signal line 104 and the second control signal line 105 are low. The potential of the first initialization signal line 108 becomes high level. As a result, the N-type MOSFET 106 and the P-type MOSFET 107 of the clocked inverter 85a are turned on, and the capacitors C6 and C7 in the correction circuits 97 and 98 are initialized. Since the first setting operation has been described with reference to FIG. 19, the description thereof is omitted here.

  In the second initialization operation, the potential of the clock signal line 96 is high, the potential of the clock bar signal line 95 is low, and the potentials of the first control signal line 104 and the second control signal line 105 are low. The potential of the second initialization signal line 108a becomes high level. As a result, the N-type MOSFET 106 and the P-type MOSFET 107 of the clocked inverter 85b are turned on, and the capacitors C6 and C7 in the correction circuits 97 and 98 are initialized. Since the second setting operation has been described with reference to FIG. 19, the description thereof is omitted here.

In the above embodiment, the initialization operation is divided into the first initialization operation and the second initialization operation. Therefore, in each initialization operation, the potentials of the clock signal line 96 and the clock bar signal line 95 are appropriately set. By controlling, a high level potential V _CH can be applied to the capacitor C 6 connected to the gate of the P-type MOSFET 93, and a low level potential V _CL can be applied to the capacitor C 7 connected to the gate of the N-type MOSFET 94.

FIG. 22 is a circuit diagram showing another embodiment of the clocked inverter 85a (85b) shown in FIG. In this figure, parts similar to those in FIG. In this clocked inverter 85c, a terminal on the opposite side to that connected to the gate of the P-type MOSFET 93 of the capacitor C6 is connected to the clock bar signal line 95 via the P-type MOSFET 110, and also connected to the clock via the P-type MOSFET 111. The bar signal is connected to the same potential V _H ′ as the high level potential V _CH of the bar signal. Similarly, a terminal on the opposite side of the capacitor C7 connected to the gate of the N-type MOSFET 94 is connected to the clock signal line 96 via the N-type MOSFET 112, and the low-level potential of the clock signal via the N-type MOSFET 113. It is connected to the same potential V _L ′ as V _CL . The gates of the MOSFETs 100, 111 and 112 are connected to the control signal line 115 via the inverter 114, and the gates of the MOSFETs 102, 110 and 113 are directly connected to the control signal line 115. Accordingly, when the potential of the control signal line 115 becomes high level, the MOSFETs 100, 111, 102, and 113 are turned on, the MOSFETs 110 and 112 are turned off, and charge is stored in the capacitors C6 and C7 (setting operation). Is made. On the other hand, when the potential of the control signal line 115 is at a low level, the MOSFETs 100, 111, 102, and 113 are turned off, the MOSFETs 110 and 112 are turned on, and the capacitors C6 and C7 charged with the clock bar signal and the clock signal. To the gates of the P-type MOSFET 93 and the N-type MOSFET 94. 22 can be said to be implemented by the MOSFETs 100, 102, 110-113 of the switches SW12, SW13, SW16-SW19 of the clocked inverter circuit 60b shown in FIG. Although this embodiment does not include the MOSFETs 106 and 107 for initializing the capacitors C6 and C7 as shown in FIG. 18, it is needless to say that they may be provided if necessary.

  FIG. 23 is a circuit diagram showing a typical unit circuit in the first latch circuit 82 shown in FIG. The unit circuit 120 includes two inverters 121 and 122 and two clocked inverters 123 and 124, and functions to latch a digitized video signal in response to a selection signal from the shift register 81. When the high level potential of the video signal is lower than the high level power supply potential VDD and / or when the low level potential of the video signal is higher than the low level power supply potential VSS, the present invention is applied to the clocked inverter 123 supplied with the video signal as an input signal. Should be applied.

FIG. 24 is a circuit diagram showing an embodiment in which the present invention is applied to the clocked inverter 123 of the first latch circuit 32 shown in FIG. 22 shows the clocked inverter 85c using a correction circuit for the MOSFET for clock signal synchronization, but FIG. 24 shows a clocked inverter using a correction circuit for the MOSFET to which an input signal is input. This clocked inverter 123 includes a P-type MOSFET 131 and an N-type MOSFET 132 connected in series with each other connected to the output terminal OUT to form a CMOS inverter, and the gates of these MOSFETs 131 and 132 are both video signals as input signals. It is connected to an input terminal IN to which a signal is input. The source of the P-type MOSFET 131 is connected to the high-level power supply potential VDD via the P-type MOSFET 133, and the source of the N-type MOSFET 132 is connected to the low-level power supply potential VSS (V _{GND in} this example) via the N-type MOSFET 134. . A selection signal from the shift register is input to the gates of the P-type MOSFET 133 and the N-type MOSFET 134, but since the inverter 135 is provided at the gate of the P-type MOSFET 133, the signals input to these MOSFETs 133 and 134 are polar Is the opposite.

  Correction circuits 136 and 137 are connected between the gates of the P-type MOSFET 131 and the N-type MOSFET 132 and the input terminal IN, respectively. The correction circuit 136 selectively sets a capacitor C8 connected between the gate of the P-type MOSFET 131 and the input terminal IN, and a diode-connected P-type MOSFET 138 having substantially the same threshold voltage as the P-type MOSFET 131. A P-type MOSFET 139 acting as a switch for performing the operation, and the P-type MOSFET 138 and the P-type MOSFET 139 are connected in series between the node N11 between the capacitor C8 and the gate of the P-type MOSFET 131 and the high-level power supply potential VDD. It is connected to the. Similarly, the correction circuit 137 includes a capacitor C9 connected between the gate of the N-type MOSFET 132 and the input terminal IN, a diode-connected N-type MOSFET 140 having substantially the same threshold voltage as the N-type MOSFET 132, and a selection circuit. N-type MOSFET 141 that acts as a switch for performing a setting operation in an automatic manner. N-type MOSFET 140 and N-type MOSFET 141 are connected to node N12 between capacitance C9 and the gate of N-type MOSFET 132 and low-level power supply potential VSS. They are connected in series. In this embodiment, the gate of the P-type MOSFET 139 is connected to the P-channel control signal line 142, and the gate of the N-type MOSFET 141 is connected to the N-channel control signal line 143. However, as shown in FIGS. When the setting operation can be performed in parallel with the N-type MOSFET, similarly to the embodiment shown in FIG. 18, by providing an inverter at either the gate of the P-type MOSFET 139 or the gate of the N-type MOSFET 141, a common 1 It is also possible to use only one control signal line.

  Further, the node N11 between the capacitor C8 and the gate of the P-type MOSFET 131 is connected to the low level power supply potential VSS via the N-type MOSFET 144, and the node N12 between the capacitor C9 and the gate of the N-type MOSFET 132 is P It is connected to the high level power supply potential VDD via the type MOSFET 145. The N-type MOSFET 144 is directly connected to the initialization signal line 146, the gate of the P-type MOSFET 145 is connected to the initialization signal line 146 via the inverter 147, and signals having opposite phases are input to the gates of these MOSFETs 144 and 145. It has become so. As shown in FIG. 12, the initialization signal lines may be arranged separately.

  A suitable signal (potential) change in each part in the initialization, setting operation, and normal operation of the clocked inverter 123 of the latch circuit configured as described above is shown in the timing chart of FIG. As illustrated, the initialization operation, the N channel setting operation (capacitance C9 setting operation), the P channel setting operation (capacitance C8 setting operation), and the normal operation are executed in this order, and the N channel setting operation and the P channel setting are performed. Each operation consists of two phases. Of course, the order of the N channel setting operation and the P channel setting operation may be interchanged.

  In the initialization operation, the input signal (video signal), the selection signal, the N channel control signal (143) are at the low level, the P channel control signal (142) is at the high level, and the initialization signal (146) is at the high level. Become. Since the P-channel control signal is at the high level and the N-channel control signal is at the low level, the P-type MOSFET 139 and the N-type MOSFET 141 are off. When the initialization signal becomes high level, the MOSFETs 144 and 145 are turned on to initialize the capacitors C8 and C9 (that is, the potential of the node N11 is lowered to the low level power supply potential VSS and the potential of the node N12 is high). Level power supply potential VDD). When the initialization signal becomes low level, the initialization operation ends.

  In the N-channel setting operation for accumulating charges in the capacitor C9 connected to the gate of the N-channel MOSFET 132, in the phase I, the video signal (IN) remains low and the N-channel control signal (143) becomes high. As a result, the N-type MOSFET 141 is turned on, a current flows from the input terminal IN to the low-level power supply potential VSS, and the capacitor C9 is charged. The N-channel control signal is kept at a high level for a time sufficient for the voltage across the capacitor C9 to have an appropriate value and the N-type MOSFET 141 to be turned off. In phase II, the N channel control signal goes low, and the N channel setting operation ends.

  In the P-channel setting operation for accumulating charges in the capacitor C8 connected to the gate of the P-channel MOSFET 131, the video signal (IN) becomes high level and the P-channel control signal (142) becomes low level in phase I. . As a result, the P-type MOSFET 139 is turned on, a current flows from the high-level power supply potential VDD to the input terminal IN, and the capacitor C8 is charged. The P channel control signal returns to the high level in the phase II after maintaining the low level for a time sufficient for the voltage across the capacitor C8 to have an appropriate value and the P-type MOSFET 139 to be turned off. Thus, when the video signal becomes low level, normal operation can be started. As shown in the figure, in normal operation, the video signal and the selection signal are applied while the P channel control signal is at a high level and the N channel control signal is at a low level. As described above, there are a type in which the capacitance is directly connected to the input terminal IN as shown in FIGS. 5 and 7, and a type in which the capacitor is connected via a switch as shown in FIGS. Various circuits can be configured by combining these two types. The timing of the setting operation can be changed as appropriate according to the configuration of each circuit.

  In the various embodiments according to the present invention described above, the principle is that the switch connected between the capacitor and the power supply potential (VDD or VSS) is turned off after performing the setting operation of the capacitor included in the correction circuit. Although the electric charge stored in the capacitor is stored in reality, it is preferable to perform the setting operation at an appropriate interval because there is actually some leakage current. For example, when the present invention is applied to a transistor in a shift register of an active matrix circuit of a liquid crystal display, the shift register does not operate during a blanking period of an input video signal, and thus a setting operation may be performed during that period (see FIG. 26a).

  Further, a plurality of different light emission periods E1, E2, E3. . . There is known a time gradation type display that obtains gradation by selectively changing the total period of light emission in each frame of each pixel to obtain gradation (for example, in the case of 4 bits, the minimum light emission) When the period is E1, E2 = 2 × E1, E3 = 4 × E1, and E4 = 8 × E1 so that 16 gradations can be obtained by combining E1 to E4). In such a time gray scale display, for example, information indicating whether or not to emit light during the light emission period E3 is written in the memory until the same writing for the light emission period E4 is started. There is a period during which the driver circuit is not operating, such as after the writing of information indicating whether or not to perform light emission during the light emission period E4 to the memory is completed (see FIG. 26b). It is also possible to perform the setting operation of the correction circuit described above during such a stop period of the driver circuit. The setting operation does not have to be performed for all the correction circuits at the same time, and may be performed at different timings for each correction circuit. In the shift register as shown in FIGS. 17 and 18, signals are sequentially shifted and transferred. Therefore, the setting operation of the correction circuit of the own stage may be performed using the signal several stages before.

  The present invention can also be used for logic circuits such as NAND circuits, NOR circuits, transfer gates, and the like. FIG. 27 is a circuit diagram showing an embodiment in which the present invention is applied to a transistor constituting a NAND circuit, and FIG. 28 is a circuit diagram showing an embodiment in which the present invention is applied to a transistor constituting a NOR circuit. is there.

The digital circuit 150 shown in FIG. 27 has two P-type MOSFETs 151 and 152 connected in parallel and two N-type MOSFETs 153 and 154 connected in series, and a NAND circuit is formed by these four MOSFETs 151 to 154. ing. More specifically, the gates of the P-type MOSFET 151 and the N-type MOSFET 153 are connected to the first input terminal IN1, and the gates of the P-type MOSFET 152 and the N-type MOSFET 154 are connected to the second input terminal IN2. The sources of the P-type MOSFETs 151 and 152 are both connected to the high level power supply potential VDD, and the drains are both connected to the drain of the N-type MOSFET 154 and connected to the output terminal OUT. The source of the N-type MOSFET 154 is connected to the drain of the N-type MOSFET 153, and the source of the N-type MOSFET 153 is connected to the low level power supply potential VSS (in this example, the ground potential V _GND ). Such NAND circuits are well known in the art.

  In accordance with the present invention, correction circuits 155-158 are provided for MOSFETs 151-154, respectively. Similar to the embodiment described above, each correction circuit 155-158 has a capacitance connected to the gate of the corresponding MOSFET, a diode-connected MOSFET having the same polarity as the corresponding MOSFET and having substantially the same threshold voltage, And a switch connected in series to the diode-connected MOSFET. Since the operations and effects of the correction circuits 155 to 158 are the same as those described in the above embodiment, the description thereof is omitted.

The digital circuit shown in FIG. 28 has two P-type MOSFETs 161 and 162 connected in series and two N-type MOSFETs 163 and 164 connected in parallel, and these four MOSFETs 161 to 164 form a NOR circuit. . More specifically, the gates of the P-type MOSFET 161 and the N-type MOSFET 163 are connected to the first input terminal IN1, and the gates of the P-type MOSFET 162 and the N-type MOSFET 164 are connected to the second input terminal IN2. The source of the P-type MOSFET 161 is connected to the high-level power supply potential VDD, and the drain is connected to the source of the P-type MOSFET 162. The drain of the P-type MOSFET 162 is connected to the drains of the N-type MOSFETs 163 and 164 and to the output terminal OUT. The sources of the N-type MOSFETs 163 and 164 are both connected to the low-level power supply potential VSS (in this example, the ground potential V _GND ). Such NOR circuits are well known in the art.

  In accordance with the present invention, correction circuits 165-168 are provided for MOSFETs 161-164, respectively. Similar to the embodiment described above, each correction circuit 165-168 has a capacitance connected to the gate of the corresponding MOSFET, a diode-connected MOSFET having the same polarity as the corresponding MOSFET and having substantially the same threshold voltage, And a switch connected in series to the diode-connected MOSFET. Since the operations and effects of the correction circuits 165 to 168 are the same as those described in the above embodiment, the description thereof is omitted.

  In the above, a digital circuit having a switch circuit using a transistor that can reliably turn on and off the transistor even when the amplitude of the input signal is smaller than the power supply voltage (difference between the high-level power supply potential and the low-level power supply potential). Although the preferred embodiment has been described, the above embodiment improves the operation speed of the transistor when the power supply voltage is not sufficiently large with respect to the absolute value of the threshold voltage of the transistor by appropriately changing the setting operation. It is possible to cope with the case where it is desired to do so. FIG. 29 shows another modified embodiment of the digital circuit capable of such setting operation. In this embodiment, the same parts as those in the embodiment of FIG.

In the digital circuit (inverter circuit) 30e of FIG. 29, the node N5 between the gate of the P-type MOSFET 32 and the capacitor C2 is connected to the low level potential V _L ″ via the switch SW20, and the gate of the N-type MOSFET 33 and the capacitor C3. Is connected to the high level potential V _H ″ via the switch SW21. The low level potential V _L ″ can be equal to the low level power supply potential VSS, and the high level potential V _H ″ can be equal to, for example, the high level power supply potential VDD. This is the same as the digital circuit 30c shown in FIG.

The setting and normal operation of the digital circuit 30e configured as described above will be described below. Here, it is assumed that the low level input potential V _INL is equal to the low level power supply potential VSS (V _{GND in} this example), and the high level input potential V _INH is equal to the high level power supply potential VDD.

As shown in FIG. 30a, in the first setting operation for the capacitor C2, when the switches SW2, SW3, and SW21 are turned off and the SW 20 is turned on and the high-level input potential _VINH is applied to the input terminal IN, the arrow in the figure. The capacitor C2 is charged in such a direction that the input terminal IN side is high and the gate side of the P-type MOSFET 32 is low. Subsequently, as shown in FIG. 30b, in the second setting operation, when the switch SW20 is turned off while the high level input potential _VINH is applied to the input terminal IN and the switch SW2 is turned on, the capacitor C2 is discharged. As shown by the arrow, current flows, and when the voltage across the capacitor C2 becomes equal to the threshold voltage V _THP of the P-type MOSFET 35, the current stops. Note that the switch SW2 may be turned on in the first setting operation. Further, the low level potential V _L ″ may be a value that allows the capacitor C2 to be charged with a voltage larger than the threshold voltage V _THP of the P-type MOSFET 35 (that is, the P-type MOSFET 32) in the first setting operation. The first setting operation may be referred to as an initialization operation.

Similarly, as shown in FIG. 31a, in the first setting operation for the capacitor C3, when the switches SW2, SW3, and SW20 are in the off state, the SW21 is turned on and the low level input potential _VINL is applied to the input terminal IN. A current flows in the direction of the arrow in the figure, and the capacitor C3 is charged in such a direction that the input terminal IN side is low and the gate side of the N-type MOSFET 33 is high. Subsequently, in the second setting operation, when the switch SW21 is turned off while the low-level input potential _VINL is applied to the input terminal IN and the switch SW3 is turned on, the capacitor C3 is discharged, as shown by an arrow in FIG. 31b. When current flows and the voltage across the capacitor C3 becomes equal to the threshold voltage V _THN of the P-type MOSFET 37, the current stops. Note that the switch SW3 may be turned on in the first setting operation. Further, the high level potential V _L ″ may be a value that allows the capacitor C3 to be charged with a voltage larger than the threshold voltage V _THN of the N-type MOSFET 37 (that is, the N-type MOSFET 33) in the first setting operation. It does not have to be equal to VDD.

After charging in this way the capacitance C2, C3, in normal operation, and turns off the switch SW2, SW3, SW20 and SW21, swinging between the high-level input potential _{V INH} and a low level input potential _{V INL} to the input terminal IN Input signal to be applied. When the high level input potential V _INH is applied, the gate potential of the P-type MOSFET 32 becomes V _INH − | V _THP | = VDD− | V _THP | as shown in FIG. The source-to-source voltage V _GS = − | V _THP |, and the P-type MOSFET 32 is turned off. On the other hand, the gate potential of the N-type MOSFET 33 is V _INH + | V _THN | = VDD + | V _THN |. Therefore, the voltage obtained by subtracting V _THN from the gate-source voltage V _{GS of the} N-type MOSFET 33 is equal to VDD, and the N-type MOSFET 33 It is possible to secure a voltage sufficient to flow a large current through the MOSFET 33 and turn it on at high speed.

Similarly, when the low-level input potential V _INL is applied to the input terminal IN, the gate potential of the N-type MOSFET 33 becomes V _INL + | V _THN | = VGND + | V _THN | as shown in FIG. The gate-source voltage V _{GS of} the N-type MOSFET 33 becomes V _GS = | V _THN |, and the N-type MOSFET 33 is turned off. On the other hand, the gate potential of the P-type MOSFET 32 is V _INL − | V _THP | = V _GND − | V _THP |. Therefore, the voltage obtained by subtracting V _THP from the gate-source voltage V _{GS of the} P-type MOSFET 32 is equal to −VDD. A voltage (absolute value) sufficient to flow a large current through the P-type MOSFET 32 and turn it on at high speed can be secured.

As described above, in the embodiment described with reference to FIGS. 29 to 32, in the setting operation, the capacitances C2 and C3 of the correction circuit are set so that the DC level of the input signal is increased in order to increase the ON operation speed of the corresponding MOSFETs 32 and 33. It is possible to charge to correct. Therefore, power consumption can be reduced by reducing the power supply voltage without reducing the operation speed of the circuit. In the above description, the low level input potential V _INL is equal to the low level power supply potential VSS (V _{GND in} this example) and the high level input potential V _INH is equal to the high level power supply potential VDD. It is not limited. In the above circuit, in general, the absolute value of the voltage of the capacitor C2 after the setting operation is | V _THP | − (VDD−V _INH ), and the absolute value of the voltage of the capacitor C3 after the setting operation is | V _THN | − (V _INL −VSS), and in the off state, V _GS = threshold voltage in both the P-type MOSFET 32 and the N-type MOSFET 33 is turned off, but in the on state, | V _GS | = | threshold voltage | + V _INH −V It will be understood that it becomes _INL .

  In the digital circuit 30e of FIG. 29, the setting operation of the capacitor C2 connected to the gate of the P-type MOSFET 32 and the capacitor C3 connected to the gate of the N-type MOSFET 33 is performed separately by changing the potential of the input signal applied to the input terminal IN. However, it is preferable that these can be performed simultaneously. Such a digital circuit is shown in FIG. In this embodiment, the digital circuit 30d shown in FIG. 13 is applied. In this figure, the same parts as those shown in FIGS. To do.

  In the digital circuit 30f of FIG. 33, a terminal on the opposite side to that connected to the gate of the P-type MOSFET 32 of the capacitor C2 is connected to the input terminal IN via the switch SW8 and is at a high level via the switch SW9. It is connected to the power supply potential VDD. Similarly, the terminal on the opposite side of the capacitor C3 connected to the gate of the N-type MOSFET 33 is connected to the input terminal IN via the switch SW10 and to the low-level power supply potential VSS via the switch SW11. ing.

The setting and normal operation of the digital circuit 30f configured as described above will be described below. Here, similarly to the description of the operation of the digital circuit 30e, the low level input potential V _INL is equal to the low level power supply potential VSS (V _{GND in} this example), and the high level input potential V _INH is equal to the high level power supply potential VDD. Shall.

  As shown in FIG. 34a, in the first setting operation, the switches SW2, SW3, SW8, and SW10 are turned off, and the switches SW9, SW11, SW20, and SW21 are turned on. Then, current flows in the direction of the arrow in the figure, and the capacitor C2 is high on the input terminal IN side, the gate side of the P-type MOSFET 32 is low, and the capacitor C3 is low on the input terminal IN side, and the gate side of the N-type MOSFET 33 is high. Charged in the direction. The first setting operation can also be called an initialization operation.

  As shown in FIG. 34b, in the second setting operation, the switches SW2, SW3, SW9 and SW11 are turned on, and the switches SW8, SW10, SW20 and 21 are turned off. As a result, the capacitors C2 and C3 are discharged, current flows in the direction indicated by the arrow in the figure, the voltage across the capacitor C2 becomes equal to the threshold voltage of the P-type MOSFET 35, and the voltage across the capacitor C3 is N-type. Each current stops when it becomes equal to the threshold voltage of the MOSFET 37.

After the setting of the capacitors C2 and C3 is completed, in normal operation, as shown in FIG. 35, the switches SW2, SW3, SW9, SW11, SW20 and SW21 are turned off, the switches SW8 and SW10 are turned on, and input to the input terminal IN. Add a signal. In this case, the operation of the MOSFETs 32 and 33 is the same as that described with reference to FIGS. 32a and 32b, and thus description thereof is omitted here. In this embodiment, since the low level input potential _VINL is equal to the low level power supply potential VSS and the high level input potential _VINH is equal to the high level power supply potential VDD, the capacitors C2 and C3 are respectively connected to the switches SW9 and SW11. high level power supply potential VDD via, it is assumed to be connected to a low level power supply potential VSS, and otherwise, the capacitance C2, C3 are generally at a high level input potential _{V INH} respectively via the switches SW9, SW11 It can be connected to an equal potential and a potential approximately equal to the low level input potential _VINL .

  As mentioned above, although this invention was demonstrated in detail based on the Example, these Examples are an illustration to the last and this invention is not limited by an Example. It goes without saying that those skilled in the art can make various modifications or changes without departing from the technical idea of the present invention defined by the claims.

For example, in the above embodiment, the low level power supply potential VSS is set to the ground potential V _GND and the high level power supply potential VDD is set to a potential higher than V _GND . However, for example, the high level power supply potential VDD is set to the ground potential V _GND and the low level power supply potential VDD is set. Other potentials can be used so that VSS is lower than the ground potential V _GND . In the above embodiment, the MOSFET has been described as the transistor. However, another transistor such as a bipolar transistor or another type of FET can be used. The transistor may have any structure, material, or manufacturing method. A normal single crystal substrate may be used, or an SOI (silicon on insulator) substrate may be used. Further, it may be a thin film transistor (TFT) using amorphous silicon or polysilicon, a transistor using an organic semiconductor, or a transistor using carbon nanotubes. The transistor may be formed over a glass substrate, a quartz substrate, a plastic substrate, or another substrate.

  Electronic devices to which the present invention can be applied include desktop, floor-standing, or wall-mounted displays, video cameras, digital cameras, goggles-type displays (head-mounted displays), navigation systems, sound playback devices (car audio, audio components, etc.), Recording of notebook personal computers, game machines, portable information terminals (mobile computers, cellular phones, portable game machines, electronic books, etc.), and image playback devices (specifically Digital Versatile Disc (DVD)) equipped with recording media A device equipped with a display capable of reproducing and displaying video and still images recorded on a medium). Specific examples of these electronic devices are shown in FIGS. 38a to 38h.

  FIG. 38A shows a desktop, floor-standing, or wall-mounted display, which includes a housing 13001, a support base 13002, a display portion 13003, a speaker portion 13004, a video input terminal 13005, and the like. The present invention can be used for an electric circuit included in the display portion 13003. Such a display can be used as an arbitrary information display device such as a personal computer, a TV broadcast receiver, and an advertisement display.

  FIG. 38B shows a digital still camera, which includes a main body 13101, a display unit 13102, an image receiving unit 13103, operation keys 13104, an external connection port 13105, a shutter 13106, and the like. The present invention can be used for an electric circuit included in the display portion 13102.

  FIG. 38c shows a notebook personal computer, which includes a main body 13201, a housing 13202, a display portion 13203, a keyboard 13204, an external connection port 13205, a pointing mouse 13206, and the like. The present invention can be used for an electric circuit included in the display portion 13203.

  FIG. 38d shows a mobile computer, which includes a main body 13301, a display portion 13302, a switch 13303, operation keys 13304, an infrared port 13305, and the like. The present invention can be used for an electric circuit included in the display portion 13302.

  FIG. 38e shows a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 13401, a housing 13402, a first display portion 13403, a second display portion 13404, a recording medium (DVD or the like). ) A reading unit 13405, an operation key 13406, a speaker unit 13407, and the like are included. Although the first display portion 13403 mainly displays image information and the second display portion B 13404 mainly displays character information, the present invention is used for an electric circuit constituting the first and second display portions 13403 and 13404. it can. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.

  FIG. 38F shows a goggle type display (head mounted display), which includes a main body 13501, a display portion 13502, and an arm portion 13503. The present invention can be used for an electric circuit included in the display portion 13502.

  FIG. 38g shows a video camera, which includes a main body 13601, a display unit 13602, a housing 13603, an external connection port 13604, a remote control receiving unit 13605, an image receiving unit 13606, a battery 13607, an audio input unit 13608, operation keys 13609, and the like. The present invention can be used for an electric circuit included in the display portion 13602.

  FIG. 38h shows a mobile phone, which includes a main body 13701, a housing 13702, a display portion 13703, an audio input portion 13704, an audio output portion 13705, operation keys 13706, an external connection port 13707, an antenna 13708, and the like. The present invention can be used for an electric circuit included in the display portion 13703.

  The display unit of the electronic device as described above may be a self-luminous type using a light emitting element such as an LED or an organic EL for each pixel, or may use another light source such as a backlight like a liquid crystal display. However, in the case of a self-luminous type, a backlight is not necessary and a display portion thinner than a liquid crystal display can be obtained.

  In addition, the electronic devices often display information distributed through electronic communication lines such as the Internet and CATV (cable television), and in particular, opportunities to display moving image information are increasing. When the display unit is a self-luminous type, the response speed of a light emitting material such as an organic EL is much faster than that of liquid crystal, which is suitable for such moving image display. If the light emission luminance of the light emitting material is increased in the future, the light including the output image information can be enlarged and projected by a lens or the like and used for a front type or rear type projector.

  In the self-luminous display unit, the light emitting part consumes power, and thus it is desirable to display information so that the light emitting part is minimized. Therefore, when a display unit mainly including character information such as a portable information terminal, particularly a mobile phone or a sound reproducing device is a self-luminous type, the character information is formed by the light emitting part with the non-light emitting part as the background. It is desirable to drive.

  As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields.

1 is a block diagram showing a schematic configuration of the present invention. FIG. 2 is a circuit diagram showing an embodiment of a digital circuit according to the present invention. 3a shows the setting operation of the digital circuit shown in FIG. 2, and FIG. 3b shows the normal operation. FIG. 4 is a circuit diagram showing another embodiment of a digital circuit according to the present invention. FIG. 5 is a circuit diagram showing another embodiment of a digital circuit according to the present invention formed by applying the present invention to a CMOS inverter circuit. 6a and 6b show the setting operation of the digital circuit shown in FIG. FIG. 7 is a circuit diagram of a digital circuit in which the switches SW2 and SW3 shown in FIG. 5 are implemented by a P-type MOSFET 38 and an N-type MOSFET 39, respectively. FIG. 8 is a circuit diagram showing a modified embodiment of the digital circuit shown in FIG. FIG. 9 is a circuit diagram showing another modified embodiment of the digital circuit shown in FIG. FIG. 10 is a circuit diagram showing still another modified embodiment of the digital circuit shown in FIG. 11a and 11b show an initialization operation in the digital circuit shown in FIG. FIG. 12 is a circuit diagram showing a digital circuit in which the switch shown in FIG. 10 is implemented as a MOSFET. FIG. 13 is a circuit diagram showing still another modified embodiment of the digital circuit shown in FIG. FIG. 14 is a circuit diagram showing an embodiment of a clocked inverter circuit to which the present invention is applied. FIG. 15 is a circuit diagram showing a modified embodiment of the clocked inverter circuit shown in FIG. FIG. 16 is a circuit diagram showing another modified embodiment of the clocked inverter circuit according to the present invention shown in FIG. FIG. 17 is a diagram schematically showing a main part of a driver circuit of an active matrix device used in a liquid crystal display or the like and a typical unit circuit in a shift register of the driver circuit. FIG. 18 is a circuit diagram showing an embodiment in which the present invention is applied to the left clocked inverter in the unit circuit of the shift register shown in FIG. FIG. 19 is a timing chart showing signals (potentials) at various parts in the initialization, setting operation, and normal operation of the shift register including the clocked inverter circuit shown in FIG. FIG. 20 is a circuit diagram showing a modification of the embodiment shown in FIG. FIG. 21 is a timing chart showing signals (potentials) of respective units in the initialization, setting operation, and normal operation of the shift register including the clocked inverter circuit shown in FIG. FIG. 22 is a circuit diagram showing another embodiment of the clocked inverter shown in FIG. FIG. 23 is a circuit diagram showing a typical unit circuit in the first latch circuit shown in FIG. 24 is a circuit diagram showing an embodiment in which the present invention is applied to the clocked inverter of the first latch circuit shown in FIG. FIG. 25 is a timing chart showing signals (potentials) at various parts in the initialization operation, setting operation, and normal operation of the clocked inverter shown in FIG. FIG. 26 a schematically shows a blanking period, and FIG. 26 b schematically shows a driver stop period. FIG. 27 is a circuit diagram showing an embodiment in which the present invention is applied to a transistor constituting a NAND circuit. FIG. 28 is a circuit diagram showing an embodiment in which the present invention is applied to a transistor constituting a NOR circuit. FIG. 29 is a circuit diagram showing still another modified embodiment of the digital circuit according to the present invention. 30a and 30b show a setting operation of the digital circuit shown in FIG. 31a and 31b show the setting operation of the digital circuit shown in FIG. 32a and 32b show the normal operation of the digital circuit shown in FIG. FIG. 33 is a circuit diagram showing still another modified embodiment of the digital circuit according to the present invention. 34a and 34b show the setting operation of the digital circuit shown in FIG. FIG. 35 is a circuit diagram showing a normal operation of the digital circuit shown in FIG. 36A is a circuit diagram showing a typical example of a conventional CMOS inverter circuit, and FIGS. 36B and 36C show a normal operation of the CMOS inverter circuit shown in FIG. 36A. 37a and 37b are diagrams for explaining the problems of the CMOS inverter circuit shown in FIG. 38a to 38h are diagrams of electronic devices to which the present invention is applied.

Claims (13)

A first transistor, a second transistor, a third transistor, and a capacitor;
In the first transistor, one of a source and a drain and a gate are electrically connected,
The first transistor and the third transistor are electrically connected in series between a first wiring and a gate of the second transistor,
One of the pair of terminals of the capacitive element is electrically connected to the first terminal,
A gate of the second transistor is electrically connected to the other of the pair of terminals of the capacitor;
One of a source and a drain of the second transistor is electrically connected to a second terminal, and the other is electrically connected to the first wiring. A first transistor, a second transistor, a third transistor, a fourth transistor, and a capacitor;
In the first transistor, one of a source and a drain and a gate are electrically connected,
The first transistor and the third transistor are electrically connected in series between a first wiring and a gate of the second transistor,
One of the pair of terminals of the capacitive element is electrically connected to the first terminal,
A gate of the second transistor is electrically connected to the other of the pair of terminals of the capacitor;
One of a source and a drain of the second transistor is electrically connected to a second terminal, and the other is electrically connected to the first wiring;
One of a source and a drain of the fourth transistor is electrically connected to a gate of the second transistor, and the other is electrically connected to a second wiring. A first transistor, a second transistor, a third transistor, a fourth transistor, and a capacitor;
In the first transistor, one of a source and a drain and a gate are electrically connected,
In the fourth transistor, one of a source and a drain and a gate are electrically connected,
The first transistor and the third transistor are electrically connected in series between a first wiring and a gate of the second transistor,
The gate of the first transistor is electrically connected to the other of the source and the drain of the fourth transistor;
One of the pair of terminals of the capacitive element is electrically connected to the first terminal,
A gate of the second transistor is electrically connected to the other of the pair of terminals of the capacitor;
One of a source and a drain of the second transistor is electrically connected to a second terminal, and the other is electrically connected to the first wiring. In claim 3,
The liquid crystal display device, wherein the first transistor and the fourth transistor have the same polarity. In claim 1,
The liquid crystal display device, wherein the first transistor, the second transistor, and the third transistor are thin film transistors. In any one of Claims 2 thru | or 4,
The liquid crystal display device, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are thin film transistors. In any one of Claims 1 thru | or 6,
The liquid crystal display device, wherein the first transistor and the second transistor have the same polarity. A first N-type transistor, a first P-type transistor, a second N-type transistor, a second P-type transistor, a third N-type transistor, a third P-type transistor, A capacitive element and a second capacitive element,
In the first N-type transistor, one of a source or a drain and a gate are electrically connected,
The first N-type transistor and the third N-type transistor are electrically connected in series between a first wiring and a gate of the second N-type transistor,
One of the pair of terminals of the first capacitive element is electrically connected to the first terminal,
A gate of the second N-type transistor is electrically connected to the other of the pair of terminals of the first capacitor;
One of a source and a drain of the second N-type transistor is electrically connected to a second terminal, and the other is electrically connected to the first wiring;
In the first P-type transistor, one of a source and a drain and a gate are electrically connected,
The first P-type transistor and the third P-type transistor are electrically connected in series between a second wiring and the gate of the second P-type transistor,
One of the pair of terminals of the second capacitive element is electrically connected to the first terminal,
A gate of the second P-type transistor is electrically connected to the other of the pair of terminals of the second capacitor;
One of the source and the drain of the second P-type transistor is electrically connected to the second terminal, and the other is electrically connected to the second wiring. A first N-type transistor, a first P-type transistor, a second N-type transistor, a second P-type transistor, a third N-type transistor, a third P-type transistor, and a fourth N-type transistor, fourth P-type transistor, first capacitor element, and second capacitor element,
In the first N-type transistor, one of a source or a drain and a gate are electrically connected,
The first N-type transistor and the third N-type transistor are electrically connected in series between a first wiring and a gate of the second N-type transistor,
One of the pair of terminals of the first capacitive element is electrically connected to the first terminal,
A gate of the second N-type transistor is electrically connected to the other of the pair of terminals of the first capacitor;
One of a source and a drain of the second N-type transistor is electrically connected to a second terminal, and the other is electrically connected to the first wiring;
One of a source and a drain of the fourth P-type transistor is electrically connected to a gate of the second N-type transistor, and the other is electrically connected to a second wiring;
In the first P-type transistor, one of a source and a drain and a gate are electrically connected,
The first P-type transistor and the third P-type transistor are electrically connected in series between a third wiring and the gate of the second P-type transistor,
One of the pair of terminals of the second capacitive element is electrically connected to the first terminal,
A gate of the second P-type transistor is electrically connected to the other of the pair of terminals of the second capacitor;
One of a source and a drain of the second P-type transistor is electrically connected to the second terminal, and the other is electrically connected to the third wiring;
One of a source and a drain of the fourth N-type transistor is electrically connected to a gate of the second P-type transistor, and the other is electrically connected to a fourth wiring. Liquid crystal display device. In claim 8,
The first N-type transistor, the second N-type transistor, the third N-type transistor, the first P-type transistor, the second P-type transistor, and the third P-type transistor are thin film transistors. A liquid crystal display device characterized by the above. In claim 9,
The first N-type transistor; the second N-type transistor; the third N-type transistor; the fourth N-type transistor; the first P-type transistor; the second P-type transistor; 3. The liquid crystal display device according to claim 3, wherein the third P-type transistor and the fourth P-type transistor are thin film transistors. In any one of Claims 1 thru | or 7,
The liquid crystal display device, wherein the capacitor element is a MOS capacitor. In any one of Claims 8 thru | or 11,
The liquid crystal display device, wherein the first capacitor element and the second capacitor element are MOS capacitors.

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