JP2007081939A - Data smoothing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data smoothing circuit which can obtain an image of higher quality without increase the circuit size, even when the head has further higher resolution in an image recording device, such as an ink jet printer. <P>SOLUTION: The circuit can obtain the image of higher quality without increase of the circuit size adding smoothing dots of 4 times resolution of the original image, by twice repeating the processing of the circuit by using a data smoothing circuit which adds the smoothing dot of 2 times resolution, as compared to the resolution of the original image data. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data smoothing circuit, and more particularly to an image output apparatus that performs smoothing on data sent at a low resolution and performs high-quality output.

  With respect to a printer that outputs high-quality images, the resolution of print data to be transferred from the host side is reduced by a factor of two to reduce the transfer data when printing text mainly composed of characters at high speed. The low-resolution data is subjected to resolution conversion processing inside the printer. At this time, the data is smoothed and high-resolution smoothing dots are added.

  A conventional data smoothing circuit is configured to add smoothing dots having a resolution twice that of input print data, and a printer mainly for high-quality output for photographic image quality is a printer mainly for character output. Therefore, the input data of a printer mainly for high-quality output for photographic image quality requires data with a resolution twice that of a printer mainly for character output.

  In view of this, there has conventionally been an object in which the contour of an image is extracted, the image is converted as vector data, and subjected to a smoothing process by scaling to an arbitrary magnification (for example, see Patent Document 1).

In addition, there is an object that has a function of thinning an image that has become thicker by removing the edge of the added image when smoothing dots are added by pattern matching (see, for example, Patent Document 2).
Japanese Patent Laid-Open No. 5-211602 (page 12, FIG. 1) JP-A-6-245056 (page 10, FIG. 12)

  A conventional data smoothing circuit based on pattern matching is configured to add smoothing dots having a resolution twice that of the input print data. When the output resolution of the printer increases, the original image also has a higher resolution. As a result, the amount of data to be transferred increases.

  In addition, a circuit that extracts and scales an image contour and performs smoothing processing has a complicated contour detection algorithm and a large circuit scale.

  In order to add a smoothing dot having a resolution four times that of the original image, pattern matching for adding a smoothing dot having a resolution twice that of the original image needs to be repeated twice. To complete the process, the number of internal shift registers is double that of the prior art.

  Further, if too much smoothing dots are added, the original image tends to swell. Conventionally, there is a circuit that has the function of thinning a thickened image by deleting the edges of the image added by smoothing. However, since edge judgment is performed simultaneously with smoothing pattern matching, the image to be referenced is smoothed. It is a low resolution before conversion, and edge detection cannot be performed at the final resolution.

  The present invention has been made paying attention to the above points. A data smoothing circuit that adds smoothing dots having a resolution twice that of the original image data is used to repeat one circuit twice. An object of the present invention is to provide a data smoothing circuit that can add smoothing dots having a resolution four times that of the original image by processing and obtain a higher quality image without increasing the circuit scale.

  The present invention uses a data smoothing circuit that adds smoothing dots of twice the resolution from the resolution of the original image data, and repeatedly processes one circuit twice so that the resolution of the original image is four times that of the original image. Add smoothing dots. Further, edge detection processing is performed on the final output high-resolution data on the image expanded by adding smoothing dots, and the expanded edge is deleted.

  That is, the technical contents of the present invention can solve the above-described problems by including the following configuration.

  (1) A data smoothing circuit having a function of adding smoothed data whose resolution is expanded in two stages from an original image by performing processing by repeating one smoothing circuit twice.

  According to the present invention, using a smoothing circuit that adds twice as many smoothed dots from a conventional original image, the original processing is written back to the original storage memory, and then four times the original image. Since reprocessing for adding smoothing dots is performed, a high-quality image can be obtained without an increase in circuit scale.

  Further, by performing edge detection processing and deleting the expanded edges by adding smoothing dots, the original image can be naturally smoothed.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to examples.

(First embodiment)
In FIG. 1, a data smoothing circuit having a function of the present invention includes a DMA interface block 101 for reading data from a memory, a register 102 for latching read data, a shift register 103 for storing read original data, and an input image. A circuit 104 that converts the resolution to a quarter resolution, a circuit 105 that converts the input image to a half resolution, a shift register 106 that stores the output of the resolution conversion circuits 104 and 105, and a smoothing dot are added. A pattern matching circuit 107 for determining a pattern to be performed, a circuit 108 for combining the original data and the smoothed dots, a shift register 109 for storing the combined data, a circuit 110 for deleting the edge portion from the smoothed dots, and the original Remove edge from data and smoothed dots A register 111 for latching the data of the data obtained by adding, and a DMA interface block 112 for writing data to the memory.

  In FIG. 2, the raster data stored in the main memory 201 is transferred to the intermediate buffer 203 using the memory controller 202. The data stored in the intermediate buffer 203 is processed by the raster / column conversion circuit 204, the smoothing circuit 205, and the other image processing circuit 206 via the memory controller 202, and every time the processing is completed. The data is again stored in the intermediate buffer 203. Therefore, the processing circuit for the data stored in the intermediate buffer 203, that is, the other image processing circuit 206 described above can be provided with a plurality of circuits.

  FIG. 3 shows the relationship between the image data size stored in the intermediate buffer 203 and the effective processing range.

  In the intermediate buffer, the horizontal size 301 and the vertical size 302 have the number of pixels of K × L, and the horizontal size 303 and the vertical size 304 of the effective processing area correspond to the number of pixels of M × N. Thus, it has a surplus size I in the horizontal direction and a surplus size J in the vertical direction. Therefore, the number of pixels in the intermediate buffer is determined by the relationship of K = M + 2 × I and L = N + 2 × J. For the target pixel 305 in the effective processing range in the intermediate buffer, the smoothing circuit performs pattern matching with the horizontal size 306 and the vertical size 307 of the peripheral region.

  The extra size I in the horizontal direction outside the effective processing area of the intermediate buffer is greater than or equal to one half that is four times the horizontal size 306 of the smoothing circuit when the resolution of the matching pattern is 1/4 of the final output resolution. The extra size J in the vertical direction needs to be at least half that obtained by quadrupling the vertical size 307 of the smoothing circuit. In the intermediate buffer, the vertical and horizontal surplus sizes are determined depending on how many peripheral pixels refer to the target pixel in the effective processing area by other image processing circuits.

  After a part of the raster image in the main memory 201 is transferred to the intermediate buffer using the memory controller 202, it is stored as a column image in the intermediate buffer using the raster / column conversion circuit 204. When the smoothing circuit processes the image in the intermediate buffer, the image is read for each column row.

  In FIG. 4, the column data size 401 in the intermediate buffer is composed of data for the area to be referred to by the number of effective processing columns + smoothing circuit pattern matching, and is latched in the read data register 102 of the smoothing circuit. The data is stored in the shift register 106 through the matching resolution conversion circuits 104 and 105.

  The state of smoothing will be described with reference to FIG. The data stored in the intermediate buffer is composed of the final output resolution, and the image data at this time has a pixel in a grid unit having a resolution of 1/4 of the final output resolution (501). Data is read from the intermediate buffer in units of columns, resolution conversion is performed, and a plurality of columns are stored in the internal shift register of the smoothing circuit (502). Since the resolution conversion of the first stage converts the resolution to a quarter of the resolution, the dots constituting each 4 × 4 grid unit of the pixel data stored in the intermediate buffer are counted. Based on the threshold value set in the smoothing circuit, the area exceeding the threshold value from the number of dots existing in the 4 × 4 grid is set to the maximum value “1”, and the object below the threshold value is set to the minimum value “0”. Store in the shift register as a one-quarter binary image.

  Next, smoothing pattern matching is performed on all pixels in the column using the central column of the shift register composed of a plurality of columns as the target pixel, and smoothing dots having a resolution twice that of the shift register are added (503). ).

  Next, the resolution of the image is converted to the original resolution and stored in the intermediate buffer. The image originally stored in the intermediate buffer is stored as it is in the original shift register without performing resolution conversion in a shift register different from the shift register for smoothing when the smoothing circuit reads it out. . The pixels of the original image are replaced with this original data, and the pixels added as smoothing dots are converted to double resolution (dots that fill a 2 × 2 grid) and stored in the intermediate buffer together with the original data (504) ).

  After smoothing all the columns in the effective processing area in the intermediate buffer, the image is read again from the first column. The image data at this time has a pixel in a grid unit having a resolution half the final output resolution (505). Data is read from the intermediate buffer in units of columns, resolution conversion is performed, and a plurality of columns are stored in the internal shift register of the smoothing circuit (506). Since the resolution conversion in the second stage converts the resolution to half, the dots that are configured for each 2 × 2 grid unit of the pixel data stored in the intermediate buffer are counted. Based on the threshold value set in the smoothing circuit, the area exceeding the threshold value from the number of dots existing in the 2 × 2 grid is set to the maximum value “1”, and the object below the threshold value is set to the minimum value “0”. Store in the shift register as a half binary image.

  Next, smoothing pattern matching is performed on all pixels in the target column of the shift register, and smoothing dots having a resolution twice that of the shift register are added (507). The two-step smoothing process so far is performed, and the resolution of the image is converted to the original resolution and stored in the intermediate buffer. As with the first stage smoothing, the image is replaced with the original image data stored in the shift register different from the smoothing shift register without performing resolution conversion. Since the resolution is the same as that of the original image data, the dot at the added location is synthesized with the original data and written back to the intermediate buffer. This completes the smoothing with two-stage resolution conversion.

(Second embodiment)
When the smoothing circuit reads the image data from the intermediate buffer and performs resolution conversion, the number of dots existing in the grid of the resolution to be reduced (for example, the 4 × 4 grid area performed at the time of the first stage smoothing) When different in each region, a value larger than the set threshold value is stored in the shift register as a maximum value “11”, a value smaller than the threshold value is “01”, and a dot-free object is “00”. To do. FIG. 6 shows the state of conversion into multi-value data. Reference numeral 601 denotes data read from the intermediate buffer, and reference numeral 602 denotes data stored in the smoothing shift register. A method for performing pattern matching from multi-value data is the same as that disclosed in Japanese Patent Laid-Open No. 2002-240365. Further, the configuration in which smoothing dots are added, converted to the original resolution, and returned to the intermediate buffer is the same as in the first embodiment.

(Third embodiment)
In the first and second embodiments, the original data and the smoothed dots are synthesized by performing two-stage smoothing, and then the data is stored in another shift register. Edge extraction is performed on the pixels in the center column of the shift register. When two or more blanks are in contact with the four directions of the pixel of interest, the processing is considered as an edge (509). Only the edge of the added smoothing dot is further extracted from the extracted edge, and the edge of the added smoothing dot is deleted from the image obtained by combining the original data and the smoothing dot (510). By writing the deleted image back to the intermediate buffer, the process of deleting the smoothed and expanded edges is completed.

  As described above, according to the first embodiment of the present invention, smoothing processing with a resolution four times the original resolution is performed by performing the processing twice using the same circuit. Is possible.

  Further, according to the second embodiment, it is possible to perform pattern matching by converting into multi-valued image data in resolution conversion when storing from the intermediate buffer to the shift register in the smoothing circuit. This is smoothing when the image data input to the recording device is multi-valued low-resolution data and the image data stored in the intermediate buffer is developed as binary pixels based on the multi-valued information. Conversion that is performed at a low resolution in the circuit can be converted back to multi-value data.

  Further, according to the third embodiment, only the edge of the added smoothed dot is extracted and deleted at the final output resolution, so that the image that has been expanded by adding the dot is smoothed more naturally. The effect to do.

Block diagram of a data smoothing circuit embodying the present invention FIG. 1 is a block diagram of an image recording apparatus including a data smoothing circuit that implements the present invention. The figure which shows the state which read the area | region which a data smoothing circuit processes from the main memory of an image recording device Diagram showing the relationship between the effective processing area of the intermediate buffer and the surrounding reference area The figure which shows the mode of a process of the data smoothing circuit which implements this invention The figure which shows a mode that it converts into multi-value data when performing resolution conversion of the image containing halftone data

Explanation of symbols

101 image data transfer circuit 102 column data latch circuit 103 original data storage shift register 104 quarter resolution conversion circuit 105 half resolution conversion circuit 106 pattern matching shift register 107 matching pattern 108 smoothed data, original data synthesis circuit 109 Smoothing dot addition data storage shift register 110 Smoothing dot addition data edge part deletion circuit 111 Smoothing processing end column storage register 112 Image data transfer circuit 201 Main memory 202 of image recording apparatus Data between blocks of image recording apparatus Memory controller 203 for controlling transmission / reception Intermediate buffer memory 204 used by each image processing block Raster / column conversion block 205 for image data Data plane for carrying out the present invention Generalization circuit 206 Other image processing circuit 207 Print buffer memory 301 for storing data processed into a format to be transferred to the printhead circuit Intermediate buffer read raster width 302 Intermediate buffer read column number 303 Intermediate buffer effective processing raster width 304 Number of effective processing columns 305 of the intermediate buffer Pattern matching target pixel 306 of the smoothing circuit Pattern matching region width 307 of the smoothing circuit Pattern matching region length 401 of the smoothing circuit Unit of one column from which the smoothing circuit reads out from the intermediate buffer 402 Area 501 where the main memory overlaps the intermediate buffer for reading 501 Original image data 502 before smoothing Image data 503 that has undergone resolution conversion for the first stage pattern matching 503 First stage pattern Smoothed data 504 added by the matching process Image data 505 converted to the original resolution including the smoothed data 505 Data that has been subjected to the smoothing process in the first stage 506 Data for the second stage pattern matching The image data 507 having undergone resolution conversion 507 Smoothed data 508 added by the second-stage pattern matching Image data 509 converted to the original resolution including the smoothed data 509 The matrix pattern 510 for extracting the edges of the image Smoothing processing Image data with dot edges added by removing

Claims (9)

  A data smoothing circuit having a function of adding smoothed data whose resolution is expanded in two stages from an original image by performing processing by repeating one smoothing circuit twice.   The data smoothing circuit according to claim 1, wherein the data smoothing circuit has a function of performing pattern matching of binary data in which pixel data includes a maximum value and a minimum value.   2. The data smoothing circuit according to claim 1, wherein the data smoothing circuit has a function of performing pattern matching of multi-value data composed of intermediate values not applicable to the maximum value, the minimum value, or both of the pixel data. Smoothing circuit.   The data smoothing circuit according to claim 1, wherein the original image data has multi-value information per pixel, and when the original image data is input to the smoothing circuit, the multi-value data is a binary high An intermediate value that does not apply to the maximum and minimum values per grid unit of the original resolution, or both, based on the number of binary data existing in the grid area of the original resolution when expanded into resolution data A data smoothing circuit having a function of determining   The data smoothing circuit according to claim 1, when the maximum value is determined from the number of binary data existing in the grid area of the resolution of the original image data, the threshold value of the number of pixel data in the grid area is arbitrarily set A data smoothing circuit having a function of setting to   The data smoothing circuit according to claim 1, when the maximum value is determined from the number of binary data existing in the grid area of the resolution of the original image data, the maximum value is greater than the set threshold value, and the minimum value is less than the threshold value A data smoothing circuit having a function of value.   The data smoothing circuit according to claim 1, when the maximum value is determined from the number of binary data existing in the grid area of the resolution of the original image data, the maximum value is greater than the set threshold value, and the intermediate value is less than the threshold value. A data smoothing circuit having a function of minimizing an area where no value or pixel data exists.   The data smoothing circuit according to claim 1, wherein the data smoothing circuit has a function of detecting and deleting an edge portion of the image from the image data to which the smoothed data is added.   The data smoothing circuit according to claim 1 has a function of detecting an edge portion of an image with respect to image data to which smoothed data is added and deleting only the edge portion of the added smoothed data. Data smoothing circuit.