JP2007081808A - Data sink and data transmission method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately discriminate the multivalued logic of a multivalued-logic signal. <P>SOLUTION: In a data transmission system 1, a data sink 300 follows the amplitude fluctuation of the multivalued-logic signal on the basis of a received reference clock. In the system 1, the data sink 300 has an amplitude detector 310 generating a threshold signal discriminating an amplitude value, a signal amplifier 320 amplifying the multivalued-logic signal, and a comparator 330 used for discriminating the multivalued-logic signal while using the threshold signal as the voltage offset of a comparator. In the system 1, the data sink 300 further has a decoder 340 generating a receiving bit clock as a trigger for discriminating data in each symbol by multiplying the frequency of a receiving word clock by K, and converting receiving serial data into receiving parallel data in response to the receiving bit clock and the receiving data clock. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data receiving apparatus and a data transmission system, and more particularly to a data receiving apparatus and a data transmission system that receive a reference clock.

  In the transmission of digital data, there are many industrial applications that require multi-bit digital transmission. However, multi-pole cables and connectors often cannot be used for transmission due to distance or mounting area / volume restrictions, and various multiplexing methods are used.

  For example, a technique for multiplexing and transmitting two or more types of data such as data and word clock as a multi-level logic signal, particularly a transmission technique using a differential multi-level logic signal is known (for example, see Patent Document 1). ).

  According to such a data transmission system, a multi-level logic signal is generated based on the data to be transmitted and the value of the word clock, and the data and the word clock are separated and demodulated by the receiving circuit.

  By the way, in recent years, it has been required to reduce the amplitude of a multi-level logic signal in order to save power and reduce radiation. As the amplitude of the multi-level logic signal is reduced, the demand for the accuracy of the threshold voltage for identifying the multi-level logic signal is increased, which imposes strong restrictions on the circuit manufacture of the transmission / reception circuit.

  As one method for avoiding this problem, a method is known in which a peak hold circuit detects the maximum amplitude from a multi-value logic signal sequence and generates an offset based on the maximum amplitude (see, for example, Patent Document 2).

However, the peak hold has a problem in accuracy such as a slow return response after erroneously recognizing the maximum amplitude to a large extent due to mixed noise. In addition, the detection circuit needs to operate within the range of the minimum pulse width of the multi-level logic signal, and thus has a problem that it is not suitable for high-speed transmission.
JP 2005-142872 A JP 2000-349605 A

In Patent Document 1 described above, three comparators are used as a method of discriminating one data from the other data (word clock).
An absolute offset (threshold voltage) is not required for the comparator for identifying one data, and the data is identified from the multi-value transmission signal by determining which of the positive and negative signals has a relatively high potential. If the comparator offset is sufficiently small compared to the signal amplitude generated by the transmission circuit, this identification is always stable without being affected by the current output from the transmission circuit or the absolute value fluctuation of the termination resistance of the reception circuit. To do.

On the other hand, the comparator that demodulates the other data needs to accurately identify the threshold voltage of each multi-level logic signal. For example, assuming that the voltage difference between the levels is V ₀ , two comparators are prepared to identify four-value (−3 / 2V ₀ , −1 / 2V ₀ , 1 / 2V ₀ , 3 / 2V ₀ ) signals. ing. At this time, one comparator needs to have an offset voltage for accurately identifying an intermediate potential between the voltage −3 / 2V ₀ and the voltage −1 / 2V ₀ , that is, the −V ₀ level, and the other comparator has a voltage 3 It is necessary to have an offset voltage that accurately identifies the intermediate potential between / 2V ₀ and 1 / 2V ₀ , that is, the V ₀ level.

However, since the multi-level logic signal actually transmitted from the transmission side to the reception side varies in amplitude due to the influence of various fluctuation factors and becomes a voltage V ₀ ± α, which differs from the amplitude at the time of transmission. If fixed threshold voltages (−V ₀ and V ₀ ) are used on the receiving side, the probability of misidentification in the comparator increases.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a data receiving apparatus and a data transmission system that can accurately identify the multi-level logic of a multi-level logic signal.

  In the present invention, in order to solve the above problem, in a data receiving device that receives a multilevel logic signal having a plurality of amplitude values and a reference clock having an amplitude corresponding to the amplitude value of the multilevel logic signal, the reference clock Is provided to generate a threshold signal that can follow the amplitude fluctuation of the multi-level logic signal and identify the amplitude value.

  According to such a data receiving apparatus, a threshold signal based on the reference clock can be generated, so that an accurate threshold signal for identifying the multi-value logic signal can be obtained even when the multi-value logic signal fluctuates. it can.

  Further, in a data transmission system for transmitting a plurality of bits of data, a multi-value logic signal having a plurality of amplitude values and a reference clock having an amplitude corresponding to the amplitude value of the multi-value logic signal are generated and transmitted to the transmission line. A threshold value signal that receives the multi-valued logic signal via the transmission path and follows the amplitude fluctuation of the multi-valued logic signal and identifies the amplitude value based on the reference clock And a data receiving device that extracts an individual signal from the multilevel logic signal by comparing the threshold signal and the received multilevel logic signal. Is done.

  According to such a data transmission system, the data receiving device can generate a threshold signal based on the reference clock, and can accurately extract individual data by comparing the threshold signal with the multi-level logic signal. .

  According to the present invention, since a threshold signal based on a reference clock can be generated, an accurate threshold signal for identifying a multi-level logic signal can be obtained even when the multi-level logic signal fluctuates.

As a result, the detection accuracy of the threshold signal is improved, so that it is possible to improve the degree of design freedom on the data transmission side, increase the transmission path speed, and the like.
In particular, when the threshold signal is controlled by generating a comparison signal based on the reference clock and comparing the comparison signal with the reference signal, an identification signal for more accurately identifying the multilevel logic signal is obtained. Can do.

  Hereinafter, embodiments of a data receiving device and a data transmission system of the present invention will be described in detail with reference to the drawings. In the following, word clock and serial data are used as data to be transmitted to the data receiving device, but the data used in the data transmission system of the present invention is not limited to this. For example, two or three or more serial data Needless to say, the present invention can also be applied.

FIG. 1 is a configuration diagram illustrating a data transmission system according to the first embodiment.
The data transmission system according to the first embodiment converts a plurality of bits of transmission parallel data to be transmitted into transmission serial data, and adds a transmission word clock indicating a word delimiter in the transmission serial data as 1-bit information. A data transmission device 100 that generates a differential multilevel logic signal (hereinafter simply referred to as a multilevel logic signal) that represents bit information in one symbol and a reference clock and sends the reference clock to the differential transmission path 200, and a differential transmission path 200 Multi-level logic signal and reference clock are received, the same received serial data as the transmission serial data and the same reception reference clock as the transmission reference clock are extracted, and the same reception parallel as the transmission parallel data based on the extracted word clock And a data receiving device 300 for reproducing data.

The multilevel logic signal and the reference clock will be described later in detail.
The data transmission device 100 includes a reference voltage (current) generation circuit 110, a multi-value logic signal generation circuit 120, and a threshold signal generation circuit 130. The multi-value logic signal generation circuit 120 and the threshold signal generation circuit 130 are Are controlled by a common reference voltage (or current) generation circuit 110.

The multi-level logic signal generation circuit 120 converts transmission parallel data of a plurality of bits (K × N bits) to be transmitted into N-bit transmission serial data, and transmits a transmission bit clock necessary for parallel-serial conversion. A transmission data clock that is synchronized with data is generated by multiplying (frequency multiplied by K), and a transmission word clock that indicates a word delimiter in the transmission serial data is generated based on the transmission data clock. Further, a multilevel logic signal having an inter-level voltage V ₀ that represents N + 1-bit information, which is a combination of N-bit transmission serial data and a transmission word clock that is a 1-bit signal, is generated.

Here, one symbol means a time for holding one value. For example, when converting to N = 1-bit transmission serial data, 1 symbol holds N + 1 = 2-bit information, that is, 2 ^{(N + 1)} = 4-value information.

The threshold signal generation circuit 130 generates a differential reference clock having an amplitude proportional to the inter-level voltage V ₀ of the multilevel logic signal. The frequency of the reference clock is not particularly limited.

  Thus, since the multi-value logic signal generation circuit 120 and the threshold signal generation circuit 130 are controlled by the common reference voltage (or current) generation circuit 110, the reference has an amplitude proportional to the voltage of the quaternary logic signal. A clock can be easily generated.

  The multilevel logic signal and the reference clock (two pairs of differential signals) output from the multilevel logic signal generation circuit 120 and the threshold signal generation circuit 130 are received by the data reception device 300 through the differential transmission path 200. .

The differential transmission line 200 is a differential signal transmission line having a finite amount of attenuation, and it is desirable that there be little difference in properties such as characteristic impedance, attenuation, skew, and load impedance.
The data receiving apparatus 300 follows an amplitude variation of the multilevel logic signal based on the received reference clock, generates an amplitude detection circuit 310 that generates a threshold signal that identifies the amplitude value, and a signal that amplifies the multilevel logic signal The amplifier circuit 320, the comparator unit 330 used for identifying the multilevel logic signal using the threshold signal as a voltage offset of the comparator, and the reception bit clock that is a trigger for identifying the data in each symbol are generated. A decoder 340 is provided for converting received serial data into received parallel data in accordance with the data clock.

Hereinafter, the operation of the data transmission system 1 will be briefly described.
In the data transmission device 100, the multi-value logic signal generation circuit 120 converts transmission parallel data of a plurality of bits (K × N bits) to be transmitted into N-bit transmission serial data, and is necessary for parallel / serial conversion. The transmission bit clock is generated by multiplying the transmission data clock (frequency multiplied by K) that the transmission parallel data was synchronized with, and the transmission word clock indicating the word delimiter in the transmission serial data is generated based on the transmission data clock. To do. Furthermore, a multi-level logic signal having an inter-level voltage V ₀ that represents N + 1 bit information, which is a combination of N-bit transmission serial data and a transmission word clock that is a 1-bit signal, is generated by one symbol, and the differential transmission line 200 Send it out.

The threshold signal generation circuit 130 generates a reference clock whose amplitude is proportional to the inter-level voltage V ₀ of the multilevel logic signal and sends it to the differential transmission line 200.
When the data reception device 300 receives the multilevel logic signal and the reference clock from the data transmission device 100 via the differential transmission line 200, the amplitude detection circuit 310 receives the multilevel logic signal based on the received reference clock. A threshold signal that follows the amplitude variation and identifies the amplitude value is generated. The signal amplifying circuit 320 amplifies the multilevel logic signal and outputs it to the comparator unit 330. The comparator unit 330 quantizes the level of the multilevel logic signal by comparing it with the threshold signal of the amplitude detection circuit 310, and extracts the received serial data and the received word clock equal to the transmitted serial data and the transmitted bit clock.

  The decoder 340 generates a reception bit clock obtained by multiplying the frequency of the reception word clock by K and a reception data clock equivalent to the reception word clock to which the reception parallel data is synchronized, and N bits according to the reception bit clock and the reception data clock. The received serial data of K × N bits is generated and output.

Next, details of the first embodiment will be described for the case of transmitting 4-bit data.
FIG. 2 is a principle diagram showing the principle of the multi-value logic signal generation circuit.

The multi-valued logic signal generation circuit 120 outputs 1-bit transmission serial data and 1-bit transmission word clock among all the above-described functions to 4 levels per symbol. is converted into multi-value logic signal has the function of transmitting the differential transmission line 200 having, resistors constituting the load resistance of the data transmitting apparatus 100 R121, and R122, a current source that outputs a constant current I ₀ and the constant current It has a current source that outputs 2I ₀ .

Since the number of differential amplifiers corresponds to a logic bit of multi-value logic, in the case of 4 (2 ⁿ ) value logic, it is composed of 2 (n) differential amplifier pairs.
In the multilevel logic signal generation circuit 120, the transmission word clock is input to the base of the npn bipolar transistor 145, and the data obtained by inverting the logic of the data input to the base of the npn bipolar transistor 145 is the npn bipolar transistor 143. Is entered into the base of The emitter sides of npn-type bipolar transistors 143 and 145 are connected to a current source through which current I ₀ flows.

The collectors of the npn bipolar transistors 143 and 145 are connected to the power supply VDD via resistors R121 and R122, respectively.
Transmission serial data is input to the base of the npn bipolar transistor 152, and data obtained by inverting the logic of the data input to the base of the npn bipolar transistor 152 is input to the base of the npn bipolar transistor 150. Each emitter side of the npn-type bipolar transistors 150 and 152 is connected to a current source through which a current 2I ₀ flows.

  The collector of the npn bipolar transistor 143 and the collector of the npn bipolar transistor 150 are connected to a POS terminal (not shown) that transmits a POS signal of a four-value differential signal. The collector of npn-type bipolar transistor 145 and the collector of npn-type bipolar transistor 152 are connected to a NEG terminal (not shown) for sending a four-value differential signal NEG signal.

  With such a circuit configuration, a multi-level logic signal is generated that has correspondence between transmission serial data and 2-bit (ie, four-value) information of the transmission word clock in one symbol in the relationship shown in the following figure. .

FIG. 3 is a diagram illustrating correspondence between transmission data, four-valued logic, and a reference clock.
Here, correspondence between input signals and output signals of the multi-level logic signal generation circuit 120 and the threshold signal generation circuit 130 of the data transmission apparatus 100 shown in FIG. 2 will be described. The receiving side will be described later.

As shown in this figure, the POS terminal voltage and the NEG terminal voltage each have four values depending on the values of the transmission serial data 2P and 2N and the transmission word clocks 1P and 1N input to the multilevel logic signal generation circuit 120. For example, assuming that the resistance values of the resistors R121 and R122 are R, when both the transmission serial data 2P and the transmission word clock 1P are “1”, the POS terminal voltage is VDD and the NEG terminal voltage is VDD-3I ₀ R. When the transmission serial data 2P is “1” and the transmission word clock 1P is “0”, the POS terminal voltage is VDD−I ₀ R and the NEG terminal voltage is VDD−2I ₀ R. When the transmission serial data 2P and the transmission word clock 1P are both “0”, the POS terminal voltage is VDD-3I ₀ R, the NEG terminal voltage is VDD, the transmission serial data 2P is “0”, and the transmission word clock. When 1P is “1”, the POS terminal voltage is VDD-2I ₀ R, and the NEG terminal voltage is VDD−I ₀ R.

In this case, the voltage V ₀ between levels is equal to the voltage difference I ₀ R between each voltage level.
The threshold signal generation circuit 130 generates a reference clock whose amplitude is equal to an integer multiple of the inter-level voltage V ₀ of the multilevel logic signal.

In this figure, a four-value differential signal shown by the POS signal -NEG signal, the differential reference clock signal _RC + -RC _- are indicated by. When the POS-NEG voltage is 3I ₀ R, the transmission serial data 2P is “1” and the transmission word clock 1P is “1”. When the POS-NEG signal is I ₀ R, the transmission serial data 2P is “1”. "When the transmission word clock 1P is" 0 "and the POS-NEG signal is -I ₀ R, the transmission serial data 2P is" 0 ", the transmission word clock 1P is" 1 ", and the POS-NEG signal is- In the case of 3I ₀ R, both the transmission serial data 2P and the transmission word clock 1P are “0”, which means that one symbol holds 2-bit quaternary information.

Considering such a voltage difference between the differential signal pairs, the voltage 2V ₀ between levels is equal to the voltage difference 2I ₀ R between the voltage levels. The threshold signal generation circuit 130 generates a differential signal of a reference clock whose differential amplitude is equal to the inter-level voltage 4V ₀ of the multilevel logic signal.

The amplitude detection circuit 310 generates a threshold signal from the received reference clock, and outputs the obtained threshold signal to the comparator unit 330.
FIG. 4 is a circuit diagram illustrating the data receiving apparatus according to the first embodiment.

  The amplitude detection circuit 310 includes a pair of NPN transistors (hereinafter simply referred to as transistors) Tr1 and Tr2 that constitute a differential amplifier circuit, one of which is connected to the power supply VDD, and the other at a connection point Y1 with the emitters of the transistors Tr1 and Tr2. A capacitor C1 and a base to be connected are connected to a connection point Y1, and a threshold generation circuit 311 including a PNP transistor Tr3 that forms an emitter follower, and a pair of PNP transistors (hereinafter simply referred to as transistors) forming a differential amplifier circuit. Tr4, Tr5 and one of them are connected to the power supply VDD, and the other is connected to the connection point Y2 between the emitters of the transistors Tr4 and Tr5. The capacitor C2 and the base are connected to the connection point Y1, and an NPN transistor constituting an emitter follower. A threshold value generation circuit 312 composed of Tr6 It is.

  Differential reference clocks RC + and RC− are input to the bases of the transistors Tr1 and Tr2, respectively. Similarly, differential reference clocks RC + and RC− are input to the bases of the transistors Tr4 and Tr5, respectively.

  Thus, the threshold generation circuit 311 detects the maximum value of the reference clock and generates a voltage Vtp (threshold signal) having a time constant proportional to the capacitor C1, and the threshold generation circuit 312 determines the minimum value of the reference clock. A voltage Vtm (threshold signal) having a time constant proportional to the capacitor C2 is detected.

  By the way, for example, if the level of the quaternary logic signal is 2.5V, 2.575V, 2.65V, 2.725V, Vtm = 2.5375V and Vtp = 2.875V are optimum threshold signals. In this case, (Vtp−Vtm) = 150 mV.

  The signal amplifying circuit 320 includes an amplifying circuit 321 in which a grounded-emitter amplifying circuit composed of an NPN transistor Tr7 and an emitter-follower circuit composed of a PNP transistor Tr8 are combined, and a PNP transistor Tr9. A grounded-emitter amplifier circuit that is configured and an amplifier circuit 322 that is provided in a subsequent stage of the transistor Tr9 and is combined with an emitter-follower circuit that is configured by the NPN transistor Tr10.

When the POS signal is input, the amplifier circuit 321 outputs an amplified signal Vp obtained by amplifying the POS signal to the comparator unit 330.
When the NEG signal is input, the amplifier circuit 322 outputs an amplified signal Vm obtained by amplifying the NEG signal to the comparator unit 330.

  The comparator unit 330 includes three comparators 331, 332, and 333 that are used to identify a four-value differential signal. Among these, the comparator 331 is a comparator for identifying zero offset, and the signal input to the inverting input terminal can be substituted by the determination of the differential positive / negative polarity, so that it is not necessary to set a threshold separately. Therefore, the comparator 331 receives the amplified signal Vp at the non-inverting input terminal and the amplified signal Vm at the inverting input terminal.

  In the comparator 332, the amplified signal Vp is input to the non-inverting input terminal, and the voltage Vtp is input to the inverting input terminal. In the comparator 333, the amplified signal Vm is input to the non-inverting input terminal, and the voltage Vtm is input to the inverting input terminal. Comparators 331, 332, and 333 compare the magnitudes of the input values, respectively, and output the result to decoder 340.

  The decoder 340 multiplies the frequency of the reception word clock from the output from the comparator unit 330 and the reference clock RC- by K, and generates a reception bit clock that serves as a trigger for identifying data in each symbol. The received serial data is converted into received parallel data in accordance with the clock and the received data clock.

Next, the operation of the data transmission system 1 will be described.
First, the data transmitting apparatus 100 generates a quaternary differential signal and reference clocks RC + and RC− and transmits them to the data receiving apparatus 300 via the differential transmission path 200.

  Next, the amplitude detection circuit 310 of the data receiving apparatus 300 detects the maximum and minimum values from the reference clocks RC + and RC−, and outputs voltages Vtp and Vtm having time constants proportional to the capacitors C1 and C2. . The signal amplifier circuit 320 receives the POS signal and the NEG signal and outputs amplified signals Vp and Vm.

  The comparator unit 330 uses the comparator 331 to determine the zero offset and reproduce the received serial data. The comparators 332 and 333 regenerate the received word clock.

  The decoder 340 multiplies the frequency of the reception word clock by K, generates a reception bit clock that serves as a trigger for identifying data in each symbol, and receives reception serial data according to the reception bit clock and the reception data clock. Convert to parallel data.

  As described above, according to the data transmission system 1 of the first embodiment, the threshold signals used for identification in the data reception device 300, that is, the voltages Vtp and Vtm, are generated from the transmitted quaternary differential signals. Instead, the threshold voltage is generated by detecting the maximum voltage value and the minimum voltage value of the reference clocks RC + and RC−, so that an accurate threshold signal can be obtained even when the quaternary differential signal fluctuates.

As a result, the detection accuracy of the threshold signal is improved, and the design flexibility of the data transmission device 100 can be improved and the transmission speed can be increased.
Furthermore, since the data transmitting apparatus 100 transmits the reference clocks RC + and RC− together with the quaternary differential signal, the fluctuation effect received by the quaternary differential signal is reflected to the reference clocks RC + and RC− to the same extent. It is possible to generate a threshold signal that follows the fluctuation of the quaternary differential signal. Therefore, not only variations in manufacturing characteristics of the data transmission device 100 and the data reception device 300 itself, but also an operation margin against external fluctuations such as the characteristics and temperature of the differential transmission path 200 is widened.

  In addition, by increasing the pulse width of the threshold signal and obtaining an averaging effect, it is possible to ensure the maximum value detection accuracy even if sudden noise superimposition occurs. This makes it possible to identify a quaternary differential signal with high reliability.

In the present embodiment, the entire reference clock is sent to the data receiving apparatus 300, but the present invention is not limited to this, and a reference clock at any limited timing may be sent.
Next, a second embodiment of the data transmission system will be described.

FIG. 5 is a configuration diagram illustrating a data transmission system according to the second embodiment.
Hereinafter, the data transmission system 1a according to the second embodiment will be described with a focus on the differences from the data transmission system 1 according to the first embodiment described above, and description of similar matters will be omitted.

The data transmission system 1a of the second embodiment is different in the configuration of the data receiving device.
The data receiving device 300a receives an N-value logic signal (log ₂ N bits) in which the voltage difference between the signal voltage levels is V ₀ and the threshold signal amplitude is (N−2) V ₀ from the data transmitting device 100. The threshold value output circuit 350 provided in the subsequent stage of the amplitude detection circuit 310 and the comparator unit 330a.

FIG. 6 is a circuit diagram illustrating a data receiving apparatus according to the second embodiment.
The threshold output circuit 350 includes (N−2) resistors R1, R2,..., R (N−3), R (N−2) connected in series.

Further, the voltage Vtp is input to the side of the resistor R1 opposite to the resistor R2, and the voltage Vtm is input to the side of the resistor R (N-2) opposite to the resistor R (N-3).
As a result, a potential difference of (Vtp−Vtm) / (N−2) is formed at both ends of each resistor. The voltage at the connection point of each resistor becomes a threshold signal and is output to the comparator unit 330a.

The comparator unit 330a includes (N−1) comparators 331a, 332a,.
33 (N-2) a, 33 (N-1) a.
The amplified voltage Vp is input to the non-inverting input terminal of the comparator 332a, and the voltage Vtp is input to the inverting input terminal. In addition, the amplified voltage Vp is input to the non-inverting input terminal of the comparator 333a, and the voltage Vtp − ((Vtp−Vtm) / (N−2)) is input to the inverting input terminal. Similarly, the amplified voltage Vp is input to the non-inverting input terminal of the comparator that detects the positive threshold voltage, and the voltage Vtp− (J−1) ((Vtp−Vtm) / (N-2)) (J ≧ 2) is input.

  The amplified voltage Vm is input to the non-inverting input terminal of the comparator that detects the negative threshold voltage, and Vtm + (J−1) ((Vtp−Vtm) / (N−2)) is input to the inverting input terminal. Is entered. Finally, the amplified voltage Vm is input to the non-inverting input terminal of the comparator 33 (N-1) a, and the voltage Vtm is input to the inverting input terminal. Thus, the voltages Vtp, Vtp − ((Vtp−Vtm) / (N−2)),..., Vtm are the threshold signals of N−2 comparators excluding the comparator (zero offset comparator) 331a. Used.

Next, the operation of the data transmission system 1a will be described.
The data transmitting apparatus 100 generates an N-value logic signal in which the voltage difference between the signal voltage levels is V ₀ and the amplitude of the threshold signal is (N−2) V ₀ , and data is transmitted via the differential transmission path 200. The data is output to the receiving device 300a. Next, the amplitude detection circuit 310 detects the maximum value and the minimum value voltage of the reference clocks RC + and RC−, and outputs voltages Vtp and Vtm having time constants proportional to the capacitors C1 and C2. Next, the threshold output circuit 350 generates a threshold signal that identifies the N-value logic signal. The comparator unit 330a uses the comparator 331a to determine the zero offset and reproduce the received serial data. The comparators 332a, 333a,..., 33 (N-2) a, 33 (N-1) a regenerate the received word clock. The decoder 340 receives the output from the comparator unit 330a and the reference clock RC +, and thereafter performs the same operation as in the first embodiment.

Next, a description will be given using a specific example.
For example, in the case of N = 8, if the 8-level level is 2.5V, 2.575V, 2.65V, 2.725V, 2.8V, 2.875V, 2.95V, 3.025V, Vtm = 2.5375V and Vtp = 2.9875V.

In this case, (Vtp−Vtm) = 450 mV.
At this time, since a voltage drop of (Vtp−Vtm) / (N−2) = 75 mV occurs across each resistor, the identification signals are Vtp = 2.9875 V and Vtp−75 mV = 2.9125 V from above, respectively. Vtp−150 mV = 2.8375V, Vtm + 150 mV = 2.6875V, Vtm + 75 mV = 2.6125V, Vtm = 2.5375V (N−2).

According to the data transmission system 1a of the second embodiment, the same effect as the data transmission system 1 of the first embodiment can be obtained.
Next, a third embodiment of the data transmission system will be described.

FIG. 7 is a configuration diagram illustrating a data transmission system according to the third embodiment.
Hereinafter, the data transmission system 1b according to the third embodiment will be described with a focus on differences from the data transmission system 1a according to the second embodiment described above, and description of similar matters will be omitted.

The data transmission system 1b according to the third embodiment is a system that can be applied to a single multilevel signal that is not differential.
The data transmission device 100b includes a multi-value logic signal generation circuit 120a that generates a single multi-value signal that is not differential, and a threshold signal generation circuit 130a that generates a single reference clock that is not differential.

The single multilevel signal is transmitted to the data receiving device 300b via the transmission path 200a.
The data reception device 300b includes an amplitude detection circuit 310b, a signal amplification circuit 320b, and a threshold output circuit 350b.

FIG. 8 is a circuit diagram illustrating a data receiving apparatus according to the third embodiment.
The amplitude detection circuit 310b includes an amplifier circuit 311b that is provided in a subsequent stage of the transistor Tr11 and a emitter-follower circuit that is configured by the PNP transistor Tr12, and a PNP transistor Tr13. The amplifier has a grounded-emitter amplifier circuit that is configured and an amplifier circuit 312b that is provided after the transistor Tr13 and is combined with an emitter-follower circuit that is configured by the NPN transistor Tr14. A capacitor C11 is provided between the collector and emitter of the transistor Tr11, and a capacitor C12 is provided between the collector and emitter of the transistor Tr12.

Reference clocks RX are input to the bases of the transistors Tr11 and Tr13, respectively.
Here, in the amplifier circuit 311b, the reference clock RX is amplified and has a time constant proportional to the capacitor C11, and the voltage Vtp1 corresponding to the positive reference clock is output. In the amplifier circuit 312b, the reference clock RX is amplified. The voltage Vtm1 having a time constant proportional to the capacitor C12 and corresponding to the negative reference clock is output.

  The amplitude detection circuit 310b is configured by combining a grounded-emitter amplifier circuit composed of a single multi-value signal NPN transistor Tr15 and an emitter follower circuit composed of a PNP transistor Tr16, which is provided at a subsequent stage of the transistor Tr15. ing. When a single multi-level signal is input, the amplitude detection circuit 310b outputs an amplified voltage VX1 obtained by amplifying the value to the comparator unit 330b.

  The threshold output circuit 350b has N-2 voltage dividing resistors (R1a, R2a,..., R (N-2) a). Further, the voltage Vtp1 is input to the side of the resistor R1a opposite to the resistor R2a, and the voltage Vtm1 is input to the side of the resistor R (N-2) a opposite to the resistor R (N-3) a.

The comparator unit 330b includes (N-1) comparators 331b, 332b, ..., 33 (N-2) b, 33 (N-1) b.
The amplified voltage VX1 is input to the non-inverting input terminal of the comparator 331b, and the voltage Vtp1 is input to the inverting input terminal. The amplified voltage VX1 is input to the non-inverting input terminal of the comparator 332b, and the voltage Vtp1-((Vtp1-Vtm1) / (N-2)) is input to the inverting input terminal. Similarly, the amplified voltage VX1 is input to the non-inverting input terminal of each comparator, and the m-th resistor Rma and (m + 1) are input to the inverting input terminal of the m-th (2 ≦ m ≦ N−2) comparator. A voltage between the second resistor R (m + 1) a is input.

The voltage Vtm1 is input to the inverting input terminal of the (N-1) th comparator.
Since the voltages Vtp1 and Vtm1 are single multi-value signals that are not differential, the voltage (Vtp1−Vtm1) / outputted between the resistor R (N−2) / 2a and the resistor R (N) / 2a. 2 is the midpoint voltage corresponding to the zero offset voltage.

According to the data transmission system 1b of the third embodiment, the same effect as the data transmission system 1a of the second embodiment can be obtained.
Next, a fourth embodiment of the data transmission system will be described.

FIG. 9 is a configuration diagram illustrating a data transmission system according to the fourth embodiment.
Hereinafter, the data transmission system 1c according to the fourth embodiment will be described with a focus on the differences from the data transmission system 1 according to the first embodiment described above, and description of similar matters will be omitted.

The data transmission system 1c according to the fourth embodiment is the same as the first embodiment except for the configuration of the data receiving apparatus.
The data receiving apparatus 300c includes an amplitude detection circuit 310c, a signal amplification circuit / threshold output circuit 360, and a comparator unit 330c.

The data receiving device 300c uses the difference between the maximum voltage value and the average voltage value of the reference clock as a threshold signal.
FIG. 10 is a circuit diagram illustrating a data receiving apparatus according to the fourth embodiment.

The amplitude detection circuit 310c is provided between the NPN transistors Tr21 and Tr22 to which the reference clock RC− is input, the NPN transistors Tr23 and Tr24 to which the reference clock RC + is input, and the emitter of the transistor Tr21 and the emitter of the transistor Tr23. The resistors R21 and R22 having the same resistance value, the NPN transistor Tr25 whose collector is connected to the emitter of the transistor Tr21, and the NPN transistor Tr26 whose collector is connected to the connection point of the emitters of the transistors Tr22 and Tr24 via the resistor R23 an NPN transistor Tr27 whose collector is connected to the emitter of the transistor Tr23, which is connected to the emitter of the transistor Tr25, the resistor constituting the current source current _I 0/2 flows R2 When connected to the emitter of the transistor Tr26, a resistor R25 which constitute a current source current _{I 0} flows, it is connected to the emitter of the transistor Tr27, a resistor R26 which constitute a current source current _I 0/2 flows, the non-inverting The comparator 311c has an input terminal connected to a connection point between the resistor R21 and the resistor R22, and an inverting input terminal connected between the resistor R23 and the collector of the transistor Tr26.

The transistors Tr22 and Tr24 constitute a differential amplifier circuit, and the maximum voltage Vtop corresponding to the amplitude of the reference clock RC + and the amplitude of the reference clock RC− is output from the emitters of the transistors Tr22 and 24. Therefore, the resistance value of the resistor R23 When _{R 0,} and an inverting input terminal of the comparator 311c voltage _{Vtop-I 0 R} 0 is input.

  The transistors Tr21 and Tr23 constitute a differential amplifier circuit. The reference clock RC + and the reference clock RC are connected from the connection point between the resistors R21 and R22 by the emitter voltage VP of the transistor Tr23 and the emitter voltage VN of the transistor Tr21. An average voltage Vave corresponding to − is output. Therefore, the average voltage Vave is input to the inverting input terminal of the comparator 311c.

FIG. 11 is a graph showing voltage waveforms at various parts of the amplitude amplifier circuit.
As shown in FIG. 11, the voltage difference Vtop−Vave between the maximum voltage Vtop and the average voltage Vave corresponds to half V _0a of the amplitude of the received threshold signal.

Returning again to FIG.
The bases of the transistors Tr25, Tr26, Tr27 are connected to the output terminal of the comparator 311c. Thus, the transistor Tr25, Tr26, the emitter current _{I 0/2} of Tr27, I _0, the magnitude of _I 0/2 is increased or decreased in accordance with the output voltage output from the comparator 311 c.

Here, the transistor Tr26 and the resistor R25 constitute a main part of the threshold control unit.
The signal amplifier / threshold output circuit 360 is composed of two emitter follower circuits forming a differential pair. A POS signal and a NEG signal are input to the bases of the NPN transistors Tr31 and Tr32, respectively.

Resistors R23a and R23b having the same resistance value as that of the resistor R23 are connected in series to the emitters of the transistors Tr31 and 32, respectively.
The bases of the transistors Tr25 to Tr27 and the bases of the transistors Tr26a and Tr26b are connected to each other, and the transistor Tr26a and the resistor R25a, and the transistor Tr26b and the resistor R25b constitute a current mirror circuit between the transistor Tr26 and the resistor R25, respectively. ing.

Thus, resistor R25a, in R25b same current flows _{I 0} an amplitude detection circuit 310c. The resistance R23a, potential difference R23b is equivalent to _{V 0a.}
The comparator unit 330c includes comparators 331c, 332c, and 333c. The non-inverting input terminal of the comparator 331c is connected to the emitter of the transistor Tr31, and the inverting input terminal is connected to the emitter of the transistor Tr32.

  The non-inverting input terminal of the comparator 332c is connected to the transistor Tr31 side of the resistor R23a, and the inverting input terminal of the comparator 332c is connected to the transistor Tr26b side of the resistor R23b. The non-inverting input terminal of the comparator 333c is connected to the transistor Tr32 side of the resistor R23b, and the inverting input terminal of the comparator 333c is connected to the transistor Tr26a side of the resistor R23a.

Next, the operation of the data transmission system 1c will be described.
First, the data transmitting apparatus 100 transmits a quaternary logic signal having a voltage difference V ₀ between the voltage levels of the quaternary signal and a threshold signal having an amplitude of 2V ₀ to the data receiving apparatus 300c via the differential transmission path 200. To transmit.

The amplitude detection circuit 310c of the data receiving device 300c generates the maximum voltage Vtop and the average voltage Vave of the threshold signal from the reference clocks RC + and RC−.
The comparator 311c compares the voltage Vtop-I ₀ R ₀ with the average voltage Vave, amplifies the signal error, and outputs the amplified error to the transistors Tr25, 26, and 27.

Based on the output of this error signal, the transistors Tr25, 26, 27 operate so as to cancel the error. Specifically, when Vtop−I ₀ R ₀ > Vave, the base voltages of the transistors Tr25, 26, and 27 increase, and the value of the current I ₀ increases. As a result, Vtop-I ₀ R ₀ becomes smaller and moves to the voltage Vave side. On the other hand, _{Vtop-I 0} R 0 <When Vave, the base voltage of the transistor Tr25,26,27 decreases, the value of the current _{I 0} is small. As a result, Vtop-I ₀ R ₀ increases and moves to the average voltage Vave side.

In this way, the comparator 311c operates so as to reduce the magnitude of the error signal, and the voltage Vtop-I ₀ R ₀ converges in the vicinity of the average voltage Vave. That is, Vtop−I ₀ R ₀ ≈Vave.

Therefore, an offset equal to the amplitude of the received multilevel logic signal can be obtained by setting the I ₀ R ₀ at this time to the amplitude V _0a .
Since the same circuit as the amplitude detection circuit 310c, the resistor R23a, the transistor Tr26a, the resistor R25a and the resistor R23b, the transistor Tr26b, and the resistor R25b are used in the signal amplifier / threshold output circuit 360, the comparators 332c and 333c It operates as an ideal discriminator for a multi-valued logic signal having an offset voltage V _0a , the comparator 332c accurately discriminates the positive binary value of the quaternary differential signal, and the comparator 333c is negative 2 Identify values accurately.

According to the data transmission system 1c of the fourth embodiment, the same effect as that of the data transmission system 1 of the first embodiment can be obtained.
According to this data transmission system 1c, since the amplitude detection circuit 310c and the signal amplification circuit / threshold output circuit 360 are provided, the offset used to identify the quaternary differential signal is the reference clock that is actually received. (Automatically) so that the maximum value is always set regardless of the individual difference between the data transmitting device 100 side and the data receiving device 300c side, fluctuations due to changes in operating temperature, operating voltage, etc. Identification is possible with a noise margin, and transmission reliability is improved.

  In addition, since the multilevel logic signal can be identified stably even when the amplitude of the transmission signal is relatively small, it is possible to reduce the power consumption of the transmitter by reducing the amplitude of the signal. Unwanted radiation from the transmission line 200 can be suppressed.

  In addition, in order to obtain the maximum amplitude value of the quaternary signal, for example, there is a decrease in the maximum value detection accuracy due to sudden noise superposition compared to a case where a circuit for generating an identification offset using a peak hold is separately provided. Therefore, a stable offset can always be generated. As a result, four-value identification with high reliability becomes possible.

  Further, in this case, the circuit manufacturing of the data transmission device 100 and the data reception device 300c is remarkably facilitated, so that the data transmission device 100 and the data reception device 300c with high productivity can be manufactured.

Next, a fifth embodiment of the data transmission system will be described.
FIG. 12 is a configuration diagram illustrating a data transmission system according to the fifth embodiment.
Hereinafter, the data transmission system 1d according to the fifth embodiment will be described focusing on the differences from the data transmission system 1c according to the fourth embodiment described above, and the description of the same matters will be omitted.

The data transmission system 1d of the fifth embodiment is the same as the fourth embodiment except for the configuration of the data receiving device.
The data receiving device 300d receives an N-value logic signal (log ₂ N bits) in which the voltage difference between the signal voltage levels is V ₀ and the threshold signal amplitude is (N−2) V ₀ from the data transmitting device 100. The apparatus includes an amplitude detection circuit 310c, a signal amplification circuit / threshold output circuit 360d, and a comparator unit 330d.

FIG. 13 is a circuit diagram illustrating a data receiving apparatus according to the fifth embodiment.
The signal amplification circuit / threshold output circuit 360d has (N−3) resistors R31, R32,..., R3 (N−4) connected in series between the emitter of the transistor Tr31 and the collector of the transistor Tr33. , R3 (N-3) and (N-3) resistors R41, R42,..., R4 (N-4) connected in series between the emitter of the transistor Tr32 and the collector of the transistor Tr34, R4 (N-3).

When the maximum voltage corresponding to the reference clock RC + amplitude and the reference clock RC- amplitude of this embodiment, it is Vtop1, the threshold signal amplitude than (N-2) _{V 0,} obtained by the data receiving apparatus 300d It was with _Vtop1-I 0 amplitude _I 0 _{R 0} when the _{R 0 ≒ Vave (N / 2-1} ) V 0a, equal offsets obtained to an integral multiple of the amplitude of the received multi-value logic signals.

As a result, the resistance values of these resistors become R ₀ / (N / 2-1), and a potential difference of V _0a is formed at both ends of each resistor.
The comparator unit 330d includes (N−1) comparators 331d, 332d,.
33 (N-2) d, 33 (N-1) d.

  The potential differences at both ends of the resistors R41, R42,..., R4 (N-4), R4 (N-3) are used as thresholds for the comparators 332d, 333d,. .

According to the data transmission system 1d of the fifth embodiment, the same effect as the data transmission system 1c of the fourth embodiment can be obtained.
Next, a sixth embodiment of the data transmission system will be described.

FIG. 14 is a configuration diagram illustrating a data transmission system according to the sixth embodiment.
Hereinafter, the data transmission system 1e according to the sixth embodiment will be described with a focus on the differences from the data transmission system 1c according to the fourth embodiment described above, and description of similar matters will be omitted.

The data transmission system 1e of the sixth embodiment is the same as the fourth embodiment except for the configuration of the data receiving device.
The data reception device 300e includes an equalization shaping circuit 370 in the previous stage of the amplitude detection circuit 310c and the signal amplification circuit / threshold output circuit 360.

FIG. 15 is a circuit diagram illustrating a data receiving apparatus according to the sixth embodiment.
The equalization shaping circuit 370 includes variable-gain high-pass filter circuits 371 and 372 for equalizing and shaping a signal deteriorated in transmission, and the high-pass filter circuit 371 so that the output signal level becomes constant even when the input signal level changes. An AGC (Auto Gain Control) circuit 373 that variably controls the gain of 372 and a comparator 374 are included.

  The high pass filter circuit 371 is provided before the transistors Tr31 and Tr32. The high pass filter circuit 372 is provided before the transistors Tr21, Tr22, Tr23, and Tr24.

  The AGC circuit 373 detects the reference clock and performs automatic adjustment together with the data signal (POG signal, NEG signal) so that the gain characteristic is optimized. In other words, the AGC circuit 373 controls the high-pass filter circuits 371 and 372 so as to perform the same gain equalization on the multi-valued logic signal and the threshold signal that have been subject to amplitude fluctuation.

The comparator 374 compares the value of the reference clock output from the high pass filter circuit 372 and outputs it to the decoder 340.
According to the data transmission system 1e of the sixth embodiment, the same effect as that of the data transmission system 1c of the fourth embodiment can be obtained.

According to the data transmission system 1e of the sixth embodiment, a threshold signal with higher reliability can be obtained.
The data transmission system of the present invention has been described based on the illustrated embodiment. However, the present invention is not limited to this, and the configuration of each unit is an arbitrary configuration having the same function. Can be replaced. Moreover, other arbitrary structures and processes may be added to the present invention.

  Further, the present invention may be a combination of any two or more configurations (features) of the above-described embodiments.

It is a block diagram which shows the data transmission system of 1st Embodiment. It is a principle figure which shows the principle of a multi-value logic signal generation circuit. It is a figure which shows a response | compatibility with transmission data, 4 value logic, and a reference clock. 1 is a circuit diagram illustrating a data receiving apparatus according to a first embodiment. It is a block diagram which shows the data transmission system of 2nd Embodiment. It is a circuit diagram which shows the data receiver of 2nd Embodiment. It is a block diagram which shows the data transmission system of 3rd Embodiment. It is a circuit diagram which shows the data receiver of 3rd Embodiment. It is a block diagram which shows the data transmission system of 4th Embodiment. It is a circuit diagram which shows the data receiver of 4th Embodiment. It is a graph which shows the voltage waveform of each part of an amplitude amplifier circuit. It is a block diagram which shows the data transmission system of 5th Embodiment. It is a circuit diagram which shows the data receiver of 5th Embodiment. It is a block diagram which shows the data transmission system of 6th Embodiment. It is a circuit diagram which shows the data receiver of 6th Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Data transmission system, 100 ... Data transmission apparatus, 110 ... Reference voltage (current) generation circuit, 120, 120a ... Multi-value logic signal generation circuit, 130, 130a ... Threshold signal generation Circuit 200 ... Differential transmission path 200a Transmission path 310, 310a, 310b, 310c Amplitude detection circuit 320, 320b Signal amplification circuit 330, 330a, 330c, 330d ..Comparator unit, 340... Decoder, 350... Threshold output circuit, 360... Signal amplification circuit / threshold output circuit, 373.

Claims (9)

In a data receiving device that receives a reference clock having an amplitude corresponding to the amplitude value of the multi-value logic signal together with a multi-value logic signal having a plurality of amplitude values
A data receiving apparatus that generates a threshold signal capable of following the amplitude variation of the multi-level logic signal and identifying the amplitude value based on the reference clock.   The data receiving apparatus according to claim 1, wherein the multi-level logic signal and the reference clock are differential signals.   The data receiving apparatus according to claim 1, wherein the threshold signal is generated by detecting a maximum value and a minimum value of the reference clock. A threshold signal generation unit that generates a comparison signal based on the reference clock;
A comparison unit for comparing the comparison signal and a reference signal;
A threshold control unit that controls the comparison signal so that the comparison signal and the reference signal are equal based on the output of the comparison unit;
A threshold signal output unit that outputs a difference between the comparison signal and the reference signal as the threshold signal;
A comparator for comparing the threshold signal and the multi-value logic signal;
The data receiving apparatus according to claim 1, further comprising: The comparison signal is a signal obtained by dropping the maximum amplitude value of the reference clock by a predetermined voltage using a fixed resistor,
The data receiving apparatus according to claim 4, wherein the threshold control unit controls a current flowing through the fixed resistor.   5. The data receiving apparatus according to claim 4, wherein the reference signal is an average voltage value of the reference clock. The threshold control unit includes a current determining resistor that determines an output current value, and includes a current source circuit that outputs a current corresponding to the resistance value of the current determining resistor.
5. The threshold signal output unit constitutes the current source circuit and a current mirror circuit, and inputs the threshold signal to the comparator unit based on a current value flowing through the current mirror circuit. Data receiver.   2. The data receiving apparatus according to claim 1, further comprising an AGC circuit that performs gain equalization on each of the multilevel logic signal and the threshold signal. In a data transmission system that transmits multi-bit data,
A data transmission device that generates a multi-value logic signal having a plurality of amplitude values, and a reference clock having an amplitude corresponding to the amplitude value of the multi-value logic signal, and sends the reference clock to a transmission line;
Receiving the multi-level logic signal via the transmission line, and generating a threshold signal that can follow the amplitude variation of the multi-level logic signal and identify the amplitude value based on the reference clock; A data receiving device that extracts individual signals from the multi-valued logic signal by comparing the received multi-valued logic signal with
A data transmission system comprising:

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