JP2007081694A - Differential amplifier circuit, receiver circuit, oscillation circuit, and driver circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a differential amplifier circuit capable of reducing a difference between a delay time during rising and that of during falling, and a receiver circuit, an oscillation circuit, and a driver circuit using the same. <P>SOLUTION: Bias voltages generated in nodes N31, N32b become almost constant even if the polarity of a differential input signal is changed to either of a positive polarity and a negative polarity. Thus, there is generated a state that currents are always made to flow in N channel-side load transistors (MN21, MN22, MN21b, and MN22b) at each cascode. By this, it is possible to extremely reduce a time required for charging and discharging the nodes N31, N32b. Therefore, it is possible to make almost equal the delay time during the rising and that of during the falling of a non-inverting output signal O(+) and an inverting output signal O(-). Consequently, the differential amplifier circuit is applicable to a high-speed circuit since the pulse width of an input signal and that of an output signal become almost identical. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a differential amplifier circuit and a receiver circuit, an oscillation circuit, and a driver circuit using the differential amplifier circuit, for example, a folded cascode differential amplifier circuit for a small amplitude differential signal.

  The low-amplitude differential signal interface represented by LVDS (low voltage differential signaling) transfers image data generated by the image sensor to other signal processing chips at high speed, for example, in an imaging device such as a digital camera or a mobile phone with a camera. Used to transfer a large amount of image data to a thin display panel mounted on a portable device such as a notebook personal computer or PDA (personal digital assistant). This is an important technology for reducing the number of units to reduce the size and weight of the system and to reduce unnecessary electromagnetic radiation that affects image quality.

  In order to receive a small-amplitude differential signal, a differential amplifier circuit is generally used as a circuit on the receiver side. The differential signal common is used in the LVDS standard so that the differential signal can be normally transmitted even when the GND potential on the driver side and the GND potential on the receiver side are separately varied or when crosstalk occurs between the signal lines. The fluctuation range of the mode voltage is specified. As a circuit on the receiver side, a CMOS differential amplifier circuit that can operate on “rail to rail” (registered trademark) is often used.

  In an analog circuit configured in a CMOS semiconductor integrated circuit, a voltage is applied so that a MOS transistor configuring the circuit is in an operating state. Therefore, the power supply voltage of the analog circuit is higher than the power supply voltage for the digital circuit. For example, it is set to 3V-5V. However, in recent years, with the miniaturization of semiconductor processes, analog circuits are also required to operate with a low power supply voltage of about 1.5 V to 2.5 V, for example. For example, in a low power supply voltage LVDS (sub_LVDS), an operation speed of several hundred MHz is required at a power supply voltage as low as ‘2 × Vth’ (where ‘Vth’ represents a threshold value of a MOS transistor). In portable devices, in order to extend the battery usage time as much as possible, low power consumption of the circuit is required.

Japanese Patent Laid-Open No. 9-74340 (Patent Document 1) discloses a first comparator circuit having a hysteresis function for receiving a differential input signal by a P-channel FET and a hysteresis function for receiving a differential input signal by an N-channel FET. A circuit having a second comparator circuit with a delay, a delay circuit that adjusts the skew of the output signal of each comparator circuit, and a logic gate that performs a logical operation on the output signal of each delay circuit is disclosed.
However, this circuit is not suitable for high-speed operation of several hundred MHz because of the hysteresis characteristics of the two comparator circuits and the delay characteristics of the delay circuit.

Japanese Patent No. 3629898 (Patent Document 2) includes a circuit in which an inverter whose input and output are short-circuited by a transistor is combined in a subsequent stage of a folded cascode differential amplifier circuit having an N-channel input differential input circuit. It is disclosed.
However, this circuit does not operate when the voltage of the input signal deviates below the threshold value 'Vth' of the NMOS transistor because the differential input circuit is composed of only N-channel inputs.

Japanese Patent No. 3202196 (Patent Document 3) discloses an N-channel input differential input circuit having two differential input pairs, and a P-channel input differential input circuit having two differential input pairs. A circuit is disclosed that includes a first-stage circuit that includes the differential-amplifier circuit having a normal configuration that amplifies a differential signal output from the first-stage circuit. Complementary outputs of the two differential input circuits provided in the first stage circuit are connected to each other, and a pair of differential signals are output from the node at this connection point.
At first glance, the first stage circuit seems to operate rail-to-rail (registered trademark), but the input voltage range of the first stage circuit is higher than ground by 'Vth' and lower than power supply voltage VDD by 'Vth'. Range up to voltage. When the input voltage is lower than “GND + Vth” or higher than “VDD−Vth”, the first stage circuit does not operate. In addition, the output voltage range of the first stage circuit is 'input voltage ± Vth', and the full swing does not occur in the power supply voltage range. .

Japanese Patent Laid-Open No. 2000-138573 (Patent Document 4) discloses a circuit in which the output of an N-channel input differential input circuit and the output of a P-channel input differential input circuit are connected.
However, the input voltage range of this circuit is from “GND + Vth” to “VDD−Vth”, and may not operate when the input voltage is lower than “GND + Vth” or higher than “VDD−Vth”.

Japanese Patent Laid-Open No. 2002-319854 (Patent Document 5) describes an N-channel input differential input circuit and a P-channel input differential input circuit to which a common input signal is applied, and the input signal voltage and reference voltage. A circuit is disclosed that includes a comparator that compares and outputs a selection signal according to the comparison result, and a selector that selects an output of one of the two differential input circuits based on the selection signal. Yes.
In the circuit of Patent Document 5, even if there is no problem in the input voltage range of the differential circuit used for the comparator, the delay time from input to output is the difference between the N-channel input differential input circuit or the P-channel input. The delay time of the selector is added to the delay time of the circuit selected from either of the differential input circuits. In an N-channel input differential input circuit, when the gate voltage of the PMOS transistor constituting the current mirror type load is stuck near 'VDD-Vth' and when it falls near 'input voltage -Vth', Since the currents flowing through the PMOS transistors are greatly different, the delay time at the output rise time and the delay time at the output fall time are different. The same applies to the differential input circuit of the P channel input, and the delay time at the rise of the output is different from the delay time at the fall of the output. Therefore, the circuit of Patent Document 5 is different from the pulse width of the input signal and the pulse width of the output signal, and is not suitable for high-speed operation of several hundred MHz.

  Japanese Patent Application Laid-Open No. 2004-112424 (Patent Document 6) combines a P-channel input differential input stage operating at a power supply voltage VDD1 with an N-channel input differential output stage of a current mirror load operating at a power supply voltage VDD2. A circuit is disclosed. When the power supply voltage is lowered as a whole, the circuit partially does not operate. Therefore, in the circuit of Patent Document 6, a high power supply voltage is supplied only to a necessary part. This is a method that can be applied when lowering the voltage of the power supply is not very important.

  In Japanese Patent Application Laid-Open No. 2003-249829 (Patent Document 7), a general folded cascode differential amplifier circuit and a self-bias differential amplifier disclosed in US Pat. No. 4,958,133 are disclosed. A circuit and a differential amplifier circuit proposed by the inventor of Patent Document 7 have been compared and studied. These are all differential amplifier circuits capable of Rail-to-Rail (registered trademark) operation.

FIG. 16 is a diagram illustrating a first example of a general folded cascode differential amplifier circuit operating on rail-to-rail (registered trademark).
The differential amplifier circuit 151 shown in FIG. 16 includes NMOS transistors MN31, MN32, MN41 to MN44, PMOS transistors MP31, MP32, MP41 to MP44, and constant current sources ISN2 and ISP2.

A common source terminal of the NMOS transistors MN31 and MN32 is connected to a power supply line of the ground potential GND (hereinafter referred to as a GND line) via a constant current source ISN2. A common source terminal of the PMOS transistors MP31 and MP32 is connected to a power supply line of the power supply voltage VDD (hereinafter referred to as VDD line) via the constant current source ISP2.
A non-inverted input signal IN (+) is input to the gates of the NMOS transistor MN31 and the PMOS transistor MP31, and an inverted input signal IN (−) is input to the gates of the NMOS transistor MN32 and the PMOS transistor MP32.
The NMOS transistor MN41 is connected between the node N41 and the GND line. The NMOS transistor MN43 is connected between the node N61 and the node N41. The drain current of the PMOS transistor MP31 is input to the node N41.
The NMOS transistor MN42 is connected between the node N42 and the GND line. The NMOS transistor MN44 is connected between the node N62 and the node N42. The drain current of the PMOS transistor MP32 is input to the node N42.
The PMOS transistor MP41 is connected between the VDD line and the node N51. The PMOS transistor MP43 is connected between the node N51 and the node N61. The drain current of the NMOS transistor MN31 is input to the node N51.
The PMOS transistor MP42 is connected between the VDD line and the node N52. The PMOS transistor MP44 is connected between the node N52 and the node N62. The drain current of the NMOS transistor MN32 is input to the node N52.
A bias voltage BN2 is input to the gates of the NMOS transistors MN43 and MN44. A bias voltage BP1 is input to the gates of the PMOS transistors MP41 and MP42. A bias voltage BP2 is input to the gates of the PMOS transistors MP43 and MP44.
The gates of the NMOS transistors MN41 and MN42 are connected to the node N61.

In the differential amplifier circuit 151 shown in FIG. 16, NMOS transistors MN31 and MN32 are N-channel side differential input transistors, and PMOS transistors MP31 and MP32 are P-channel side differential input transistors.
The NMOS transistors MN41 and MN42 are resistance load circuits on the GND side of the cascode stage, and the NMOS transistors MN43 and MN44 are cascode transistors on the N channel side.
The PMOS transistors MP41 and MP42 are resistive load circuits on the VDD side of the cascode stage, and the PMOS transistors MP43 and MP44 are cascode transistors on the P channel side.
An inverted output signal of the cascode stage is generated at the node N61, and a non-inverted output signal O (+) of the cascode stage is generated at the node N62.
By supplying the voltage of the node N61 to the gates of the NMOS transistors MN41 and MN42 as a bias voltage, a wide-range cascode circuit is configured. In this cascode circuit, the voltage of the node N61 is set so that the current flowing through the PMOS transistor MP43 and the current flowing through the NMOS transistor MN43 are substantially equal, and operates as a current mirror circuit.
The differential signals (IN (+), IN (−)) input to the differential input transistor are amplified in the cascode stage, and the amplification result is output from the node N61 as the output signal O (+).

  The input voltage range of the differential amplifier circuit 151 shown in FIG. 16 is a range from the ground potential GND to the power supply voltage VDD, and the output voltage range is also a range from the ground potential GND to the power supply voltage VDD. For this reason, a normal inverter or an inverter whose input / output is short-circuited by a resistor can be used for the next-stage circuit that receives a signal output from the differential amplifier circuit.

In the differential amplifier circuit 151 shown in FIG. 16, the delay time at the rise of the output is different from the delay time at the fall, as shown in a simulation result (FIG. 6) to be described later. And the pulse width of the output signal are different. Therefore, as pointed out in Patent Document 7, it is not suitable for high-speed operation.
However, if each bias voltage (BN1, BP1, BP2) is optimally designed by using the reference current, it is possible to operate at a lower power supply voltage than a system in which the bias voltage is reduced to one type in a low frequency region. It is. Further, by using the reference current source, it is possible to reduce the frequency characteristic variation and the power supply voltage dependency of the current consumption.

FIG. 17 is a diagram illustrating a second example of a general folded cascode differential amplifier circuit that operates on rail-to-rail (registered trademark).
The difference between the differential amplifier circuit 152 shown in FIG. 17 and the differential amplifier circuit 151 shown in FIG. 16 is that the NMOS transistor MN43 is such that the average voltage of the nodes N61 and N62 in the cascode stage is around 'VDD / 2'. And the bias voltage input to the gates of the MN 44 is controlled by the common feedback circuit 51.
Feedback control with such a delay is not a problem in analog applications where the frequency band is about several MHz, but does not work well in applications of several hundred MHz such as LVDS.

FIG. 18 shows a self-bias type differential amplifier circuit disclosed in US Pat. No. 4,958,133.
The differential amplifier circuit 153 shown in FIG. 18 includes NMOS transistors MN31 to MN33, MN41 to MN44, and PMOS transistors MP31 to MP33, MP41 to MP44.

The common source terminal of the NMOS transistors MN31 and MN32 is connected to the GND line via the NMOS transistor MN33. The common source terminal of the PMOS transistors MP31 and MP32 is connected to the VDD line via the PMOS transistor MP33.
A non-inverted input signal IN (+) is input to the gates of the NMOS transistor MN31 and the PMOS transistor MP31, and an inverted input signal IN (−) is input to the gates of the NMOS transistor MN32 and the PMOS transistor MP32.
The NMOS transistor MN41 is connected between the node N41 and the GND line. The NMOS transistor MN43 is connected between the node N61 and the node N41. The drain current of the PMOS transistor MP31 is input to the node N41.
The NMOS transistor MN42 is connected between the node N42 and the GND line. The NMOS transistor MN44 is connected between the node N62 and the node N42. The drain current of the PMOS transistor MP32 is input to the node N42.
The PMOS transistor MP41 is connected between the VDD line and the node N51. The PMOS transistor MP43 is connected between the node N51 and the node N61. The drain current of the NMOS transistor MN31 is input to the node N51.
The PMOS transistor MP42 is connected between the VDD line and the node N52. The PMOS transistor MP44 is connected between the node N52 and the node N62. The drain current of the NMOS transistor MN32 is input to the node N52.
The gates of the NMOS transistors MN41 to MN44 and MN33 and the gates of the PMOS transistors MP41 to MP44 and MP33 are commonly connected to the node N61.

In the differential amplifier circuit 153 shown in FIG. 18, NMOS transistors MN31 and MN32 are N-channel side differential input transistors, and PMOS transistors MP31 and MP32 are P-channel side differential input transistors.
The NMOS transistors MN41 and MN42 are resistance load circuits on the GND side of the cascode stage, and the NMOS transistors MN43 and MN44 are cascode transistors on the N channel side.
The PMOS transistors MP41 and MP42 are resistive load circuits on the VDD side of the cascode stage, and the PMOS transistors MP43 and MP44 are cascode transistors on the P channel side.
An inverted output signal of the cascode stage is generated at the node N61, and a non-inverted output signal O (+) of the cascode stage is generated at the node N62.
The voltage of the node N61 is set so that the current flowing through the PMOS transistor MP43 and the current flowing through the NMOS transistor MN43 are substantially equal.
The differential signals (IN (+), IN (−)) input to the differential input transistor are amplified in the cascode stage, and the amplification result is output from the node N61 as the output signal O (+).

FIG. 19 is a diagram illustrating an example of a simulation result of each signal waveform in the self-bias type differential amplifier circuit 153 illustrated in FIG. FIG. 20 shows a part of the voltage waveform shown in FIG. In the examples of FIGS. 19 and 20, the power supply voltage VDD, the common mode voltage Vcom of the input differential signal, the voltage amplitude Vin of the input differential signal, and the frequency f of the input differential signal are respectively set as follows. The simulation is done.
VDD = 2.5 [V];
Vcom = 0.0 to 2.5 [V];
Vin = Vcom ± 50 [mV];
f = 200 [MHz];

In FIGS. 19A and 20A, solid lines “IN (+)” and “IN (−)” indicate voltage waveforms of complementary input signals.
In FIG. 19B and FIG. 20B, the dotted line “O (+) _ o” indicates the voltage waveform of the output signal of the differential amplifier circuit 153.
In FIG. 19C and FIG. 20C, a dotted line “INV_O (+) _ o” indicates a voltage waveform as a result of amplifying the output signal of the differential amplifier circuit 153 by the inverter.
In FIG. 19D and FIG. 20D, the dotted line “BS_o” indicates the voltage waveform of the inverted output (node N61) of the cascode stage.

  The voltage waveform of the dotted line 'BS_o' in FIGS. 19D and 20D represents the waveform of the bias voltage supplied to the gates of the NMOS transistors MN41 to MN44 and MN33 and the PMOS transistors MP41 to MP44 and MP33. . According to this simulation waveform, the bias voltage input to the gate of each transistor depends on whether the common mode voltage of the input differential signal (IN (+), IN (−)) is on the GND side or the VDD side. And about 30 mV to 60 mV depending on whether the polarity of the differential input signal is positive or negative.

In the differential amplifier circuit 153 shown in FIG. 18, when the input signal changes, the inverted output (node N62) of the cascode stage changes by about 30 mV to 60 mV. Feedback and then the output voltage is determined. Therefore, a slight loss occurs in the operation speed.
The input voltage range is the range from the ground potential GND to the power supply voltage VDD, but the output voltage range is a range of '± Vth' that is centered on the bias voltage (≈VDD / 2). Do not swing. For this reason, the next-stage circuit must also be a differential circuit based on a bias voltage similar to that of the differential amplifier circuit 153, or an inverter having a logic threshold voltage set near the bias voltage. When an inverter is connected to the next stage, if the logic threshold voltage deviates from the bias voltage, the pulse widths of the input signal and the output signal are different.

FIG. 21 is a diagram showing a configuration of a folded cascode differential amplifier circuit proposed by the inventor of Patent Document 7. In FIG.
A differential amplifier circuit 154 shown in FIG. 21 includes an amplifier AMP11 of the main body and a pseudo circuit PSAMP12 for generating a bias voltage. Similar to the differential amplifier circuit 153, the differential amplifier AMP11 includes NMOS transistors MN31 to MN33, MN41 to MN44, and PMOS transistors MP31 to MP33, MP41 to MP44. The pseudo circuit PSAMP12 includes NMOS transistors MN31b to MN33b, MN41b to MN44b, and PMOS transistors MP31b to MP33b, MP41b to MP44b.

  Each component of the main amplifier unit AMP11 has the same connection relationship as the component of the same reference sign in the differential amplifier circuit 153 shown in FIG. However, the gates of the NMOS transistors MN41 to MN44 and MN33 and the gates of the PMOS transistors MP41 to MP44 and MP33 are commonly connected to the nodes N61b and N62b of the pseudo circuit PSAMP12. Further, an inverted output signal O (+) is generated at the node N61, and a non-inverted output signal O (−) is generated at the node N62. These two signals correspond to the input differential signals (IN (+), IN (−)). Output differential signal.

Each component of the pseudo circuit PSAMP12 is connected as follows.
A common source terminal of the NMOS transistors MN31b and MN32b is connected to the GND line via the NMOS transistor MN33b. A common source terminal of the PMOS transistors MP31b and MP32b is connected to the VDD line via the PMOS transistor MP33b.
A non-inverted input signal IN (+) is input to the gates of the NMOS transistor MN31b and the PMOS transistor MP31b, and an inverted input signal IN (−) is input to the gates of the NMOS transistor MN32b and the PMOS transistor MP32b.
The NMOS transistor MN41b is connected between the node N41b and the GND line. The NMOS transistor MN43b is connected between the node N61b and the node N41b. The drain current of the PMOS transistor MP31b is input to the node N41b.
The NMOS transistor MN42b is connected between the node N42b and the GND line. The NMOS transistor MN44b is connected between the node N62b and the node N42b. The drain current of the PMOS transistor MP32b is input to the node N42b.
The PMOS transistor MP41b is connected between the VDD line and the node N51b. The PMOS transistor MP43b is connected between the node N51b and the node N61b. The drain current of the NMOS transistor MN31b is input to the node N51b.
The PMOS transistor MP42b is connected between the VDD line and the node N52b. The PMOS transistor MP44b is connected between the node N52b and the node N62b. The drain current of the NMOS transistor MN32b is input to the node N52b.
Node N61b and node N62b are connected to each other.
The gates of the NMOS transistors MN41b to MN44b and MN33b and the gates of the PMOS transistors MP41b to MP44b and MP33b are commonly connected to the nodes N61b and N62b.

In the pseudo circuit PSAMP12, the NMOS transistors MN31b and MN32b are N-channel side differential input transistors, and the PMOS transistors MP31b and MP32b are P-channel side differential input transistors.
The NMOS transistors MN41b and MN42b are resistance load circuits on the GND side of the cascode stage, and the NMOS transistors MN43b and MN44b are cascode transistors on the N channel side.
The PMOS transistors MP41b and MP42b are resistance load circuits on the VDD side of the cascode stage, and the PMOS transistors MP43b and MP44b are cascode transistors on the P channel side.
The node N61b is an inverted output of the cascode stage, the node N62b is a non-inverted output of the cascode stage, and these complementary outputs are connected to each other in the pseudo circuit PSAMP12. The voltage generated at this connection point (nodes N61b and N62b) is set so that the current flowing through the PMOS transistors MP43 and MP44 is substantially equal to the current flowing through the NMOS transistors MN43 and MN44.

  The differential amplifier circuit 154 shown in FIG. 21 has a bias voltage simplified to one, and unlike the self-bias type differential amplifier circuit 153 shown in FIG. Operates at high speed. Therefore, this circuit is applied to, for example, a synchronous SRAM. As shown in FIG. 21, a method of generating a bias voltage for the amplification unit of the main body using a pseudo circuit is hereinafter referred to as a pseudo circuit bias type.

19 and FIG. 20, the waveform indicated by the solid line shows an example of the simulation result of each signal waveform in the pseudo-circuit bias type differential amplifier circuit 154 shown in FIG. The simulation conditions are the same as those of the self-bias type differential amplifier circuit 153 shown in FIG.
In FIGS. 19A and 20A, solid lines “IN (+)” and “IN (−)” indicate voltage waveforms of complementary input signals.
In FIG. 19B and FIG. 20B, the solid line “O (+)” indicates the voltage waveform of the output signal of the differential amplifier circuit 154.
In FIG. 19C and FIG. 20C, a solid line “INV_O (+)” indicates a voltage waveform as a result of amplifying the output signal of the differential amplifier circuit 154 by an inverter.
In FIG. 19D and FIG. 20D, a solid line “BS” indicates a voltage waveform generated at the nodes N61b and N62b of the pseudo circuit PSAMP12.

  The voltage waveform of the solid line 'BS' in FIGS. 19D and 20D is the waveform of the bias voltage supplied to the gate of each transistor (MN41 to MN44, MN33, MP41 to MP44, MP33) of the amplifier AMP11. Represents. According to this simulation waveform, the bias voltage supplied to the amplifying unit AMP11 depends on whether the common mode voltage of the input differential signals (IN (+), IN (−)) is on the GND side or the VDD side. Although it fluctuates by about 60 mV, unlike the self-bias type dotted waveform 'BS_o', there is almost no fluctuation according to the polarity of the differential input signal.

  In the pseudo-circuit bias type differential amplifier circuit 154 shown in FIG. 21, the input voltage range is a range from the ground potential GND to the power supply voltage VDD, but the output voltage range is centered around the bias voltage (≈VDD / 2). In the range of “± Vth” and does not fully swing in the power supply voltage range. Therefore, similarly to the self-bias type differential amplifier circuit 153 shown in FIG. 18, if the logic threshold voltage of the inverter connected to the next stage is deviated from the vicinity of the bias voltage, the pulse widths of the input signal and the output signal are different. End up.

  In the simulation results of FIG. 20, the overall delay time from the crossing of the complementary differential input signals to the change of the inverter output is 0.6 ns to 1 ns, whereas the self-bias method and the pseudo circuit The difference in bias method is not so large as about 0.1 ns. This is because, in the self-bias method, the voltage on the inverting output side of the cascode stage also changes due to the change in the polarity of the differential input signal, but the amount of change is as small as about 30 mV to 60 mV, or the non-inverting output O ( When comparing only with (+), it is conceivable that the pseudo-circuit bias method has a smaller amplitude than the self-bias method. For this reason, in the pseudo circuit bias system, it is considered that the merit is increased when the complementary output of the differential amplifier circuit 10 is further received by the differential circuit.

  In the differential amplifier circuit 153 shown in FIG. 18 and the differential amplifier circuit 154 shown in FIG. 21 described above, the diode connection circuit of the PMOS transistor and the NMOS transistor are connected between the VDD line and the GND line in the cascode stage. The diode connection circuit is connected in series. For this reason, when the power supply voltage VDD is smaller than “2 × Vth”, the consumption current stops flowing at all, and when the power supply voltage VDD is higher than that, a consumption current proportional to ‘(VDD / 2−Vth) ^ 2’ flows. As a result, the frequency characteristics and power consumption greatly vary under the influence of power supply voltage and process variations. Therefore, the differential amplifier circuit 153 shown in FIG. 18 and the differential amplifier circuit 154 shown in FIG. 21 are not very suitable for an input / output circuit that must satisfy general-purpose standards such as LVDS.

  On the other hand, Japanese Patent Laid-Open No. 2000-31810 (Patent Document 8) discloses a resistance load type differential amplifier circuit for single input complementary output conversion for controlling an output transistor of an LVDS driver. Japanese Patent No. 3202196 (Patent Document 9) discloses a current mirror load type differential amplifier circuit for single input complementary output conversion for controlling an output transistor of an LVDS driver. As described above, a differential amplifier circuit that operates at high speed with a low power supply voltage is required not only on the receiver side of the LVDS but also on the driver side.

Japanese Unexamined Patent Publication No. Hei 9-74340 Japanese Patent No. 3269898 Specification Patent No. 3202196 JP 2000-138573 A JP 2002-319854 A JP 2004-112424 A JP 2003-249829 A JP 2000-31810 A Japanese Patent No. 3202196

  By the way, the folded cascode differential amplifier circuit 151 shown in FIG. 16 is suitable for high-speed operation of several hundred MHz because the delay time at the output rise time and the delay time at the fall time are different as described below. There is a disadvantage of not.

  When the non-inverted input signal IN (+) is at low level and the inverted input signal IN (−) is at high level, the signal generated at the inverted output (node N61) of the cascode stage is generated at the high level and non-inverted output (node N62). The signal O (+) to be turned to the low level. At this time, the currents of the NMOS transistors MN41 and MN42 to which the high level voltage of the node N61 is input to the gate increase. Further, the current flowing through the NMOS transistors MN43 and MN44 and the PMOS transistors MP43 and MP44 also increases. In this state, since the current flowing through each transistor increases, the speed of changing to the next state increases.

When the non-inverted input signal IN (+) changes from low level to high level and the inverted input signal IN (−) changes from high level to low level, the N-channel differential input NMOS transistor MN31 changes from off to on, and NMOS The transistor MN32 changes from on to off. Further, the P-channel side differential input PMOS transistor MP31 changes from on to off, and the PMOS transistor MP32 changes from off to on.
At this time, when the NMOS transistor MN31 is turned on, the current flowing from the node N51 to the NMOS transistor MN31 increases, and the current flowing to the PMOS transistor MP43 decreases. Further, when the PMOS transistor MP31 is turned off, the current flowing from the PMOS transistor MP31 to the node N41 is decreased, and the current flowing to the NMOS transistor MN43 is increased. That is, the current of the PMOS transistor MP43 decreases and the current of the NMOS transistor MN43 increases. As a result, the charges accumulated in the gate capacitances of the NMOS transistors MN41 and MN42 are discharged, and the voltage at the node N61 changes from the high level to the low level. When the node NN61 changes to the low level, the current flowing through the NMOS transistors MN41 and MN42 decreases.
On the other hand, when the PMOS transistor MP32 is turned on, the current flowing from the PMOS transistor MP32 to the node N42 increases. At this time, the current flowing to the NMOS transistor MN42 decreases, so that the voltage at the node N42 increases and the NMOS transistor The voltage between the gate and source of MN42 decreases, and the current of NMOS transistor MN44 decreases. Further, when the NMOS transistor MN32 is turned off, the current flowing from the node N52 to the NMOS transistor MN32 decreases, and the current flowing to the PMOS transistor MP44 increases. That is, the current of the NMOS transistor MN44 decreases and the current of the PMOS transistor MP44 increases. Therefore, a charging current flows from the node N62 to the output load capacitance, and the non-inverted output signal O (+) rises from the low level to the high level.

  When the non-inverted input signal IN (+) is at a high level and the inverted input signal IN (−) is at a low level, a signal generated at the inverted output (node N61) of the cascode stage is generated at a low level and a non-inverted output (node N62). The signal O (+) becomes high level. At this time, the current of the NMOS transistors MN41 and MN42 to which the low level voltage of the node N61 is input to the gate becomes small. Further, the current flowing through the NMOS transistors MN43 and MN44 and the PMOS transistors MP43 and MP44 is also reduced. In this state, since the current flowing through each transistor is small, the speed of changing to the next state is slow.

When the non-inverted input signal IN (+) changes from high level to low level and the inverted input signal IN (−) changes from low level to high level, the N-channel differential input NMOS transistor MN31 changes from on to off. The transistor MN32 changes from off to on. Further, the P-channel side differential input PMOS transistor MP31 changes from off to on, and the PMOS transistor MP32 changes from on to off.
At this time, when the NMOS transistor MN31 is turned off, the current flowing from the node N51 to the NMOS transistor MN31 decreases, and the current flowing to the PMOS transistor MP43 increases. Further, when the PMOS transistor MP31 is turned on, the current flowing from the PMOS transistor MP31 to the node N41 increases, and the current flowing to the NMOS transistor MN43 decreases. That is, the current of the PMOS transistor MP43 increases and the current of the NMOS transistor MN43 decreases. Therefore, charges are accumulated in the gate capacitances of the NMOS transistors MN41 and MN42, and the voltage at the node N61 changes from the low level to the high level. When the node NN61 changes to the high level, the current flowing through the NMOS transistors MN41 and MN42 increases.
On the other hand, when the PMOS transistor MP32 is turned off, the current flowing from the PMOS transistor MP32 to the node N42 decreases. At this time, the current flowing to the NMOS transistor MN42 increases, so that the voltage at the node N42 decreases, and the NMOS transistor The voltage between the gate and source of MN42 increases, and the current of NMOS transistor MN44 increases. Further, when the NMOS transistor MN32 is turned on, the current flowing from the node N52 to the NMOS transistor MN32 increases, and the current flowing to the PMOS transistor MP44 decreases. That is, the current of the NMOS transistor MN44 increases and the current of the PMOS transistor MP44 decreases. Therefore, a discharge current flows from the output load capacitance to the node N62, and the non-inverted output signal O (+) falls from the high level to the low level.

The current flowing through the NMOS transistor MN42 does not increase unless the gate capacitances of the NMOS transistors MN41 and MN42 are charged. Accordingly, the delay time becomes longer in the period for charging the gate capacitance, that is, the period in which the non-inverted output signal O (+) falls to the low level.
For this reason, in the folded cascode differential amplifier circuit 151 shown in FIG. 16, the delay time at the fall of the non-inverted output O (+) is longer than the delay time at the rise, and the pulse width of the input signal The pulse width of the output signal will be different. When the pulse width of the output signal is different, the duty ratio of the output signal is deviated from a desired value (for example, 50%), so that the operation margin is reduced and high-speed operation becomes difficult.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a differential amplifier circuit capable of reducing the difference between the delay time at the rise time and the delay time at the fall time, and by using the differential amplifier circuit. An object of the present invention is to provide a receiver circuit, an oscillation circuit, and a driver circuit that can operate at high speed.

  A differential amplifier circuit according to a first aspect of the present invention includes a first amplifying unit and a second amplifying unit for inputting a common differential signal. Each of the first amplifying unit and the second amplifying unit generates a first differential current that flows in a direction to be discharged from the first power supply line toward the second power supply line in response to the input differential signal. And a second differential current generator that generates a second differential current that flows in a direction of drawing from the first power supply line toward the second power supply line in response to the differential signal of the input. Part, a first cascode part that inputs one current of the first differential current and one current of the second differential current that are in a relationship of decreasing one when one increases, and the other when one increases And a second cascode portion for inputting the other one current of the first differential current and the other one current of the second differential current. Each of the first cascode section and the second cascode section includes a first node that inputs one current of the first differential current, and a second node that inputs one current of the second differential current; , A third node, a first conductivity type first transistor for controlling the current flowing from the first node to the second power supply line to be constant, and a current flowing from the first power supply line to the second node A second transistor of a second conductivity type that is controlled to keep constant, and an impedance that controls the impedance between the first node and the third node so that the voltage of the first node is kept constant. A third transistor of the first conductivity type, and a fourth transistor of the second conductivity type that controls an impedance between the second node and the third node so that the voltage of the second node is kept constant. Including. The third node of the first cascode section or the second cascode section in the first amplification section and the third node of the first cascode section or the second cascode section in the second amplification section are connected in common. The two third nodes connected in common have a relation that when one voltage rises when the two third nodes are separated from each other, the other voltage falls, and the above-mentioned third node included in the first amplification unit One of the first transistor and the second transistor increases or decreases the current in common according to the voltage of the third node connected in common, and the first transistor included in the second amplifying unit And any one of the second transistors increases or decreases the current in common according to the voltage of the third node connected in common, and From the other two of the third node that is not the common connected in serial the second amplifying unit, and outputs the amplified result of the differential signal of the input.

  A differential amplifier circuit according to a second aspect of the present invention includes a first amplifying unit and a second amplifying unit for inputting a common differential signal. Each of the first amplifying unit and the second amplifying unit generates a first differential current that flows in a direction to be discharged from the first power supply line toward the second power supply line in response to the input differential signal. And a second differential current generator that generates a second differential current that flows in a direction of drawing from the first power supply line toward the second power supply line in response to the differential signal of the input. Part. The first amplifying unit includes a first cascode unit that inputs one current of the first differential current and one current of the second differential current that have a relationship in which one decreases when the other increases. And a second cascode section for inputting the other one current of the first differential current and the other one current of the second differential current which are in a relationship of decreasing the other when the voltage increases. The second amplifying unit further includes a third cascode unit that inputs a current of the first differential current and a current of the second differential current that have a relationship in which one increases and the other decreases. . Each of the first cascode unit, the second cascode unit, and the third cascode unit receives a first node that inputs one of the first differential currents and a current of the second differential current. The second node to be input, the third node, the first transistor of the first conductivity type that controls the current flowing from the first node to the second power supply line to be constant, and the first power supply line to the above-mentioned A second conductivity type second transistor that controls the current flowing to the second node to be constant, and between the first node and the third node so that the voltage of the first node is kept constant. The second transistor for controlling the impedance between the second node and the third node so that the voltage of the second node and the second transistor of the first conductivity type for controlling the impedance of the second node are kept constant. Conductive type 4th tiger And a register. The third node of the first cascode part or the second cascode part and the third node of the third cascode part are connected in common, and the two third nodes connected in common are separated from each other. In this case, when one voltage increases, the other voltage decreases, and either one of the first transistor and the second transistor included in the first amplifying unit is connected in common. The current is commonly increased or decreased according to the voltage of the third node, and one of the first transistor and the second transistor included in the second amplifying unit is connected to the commonly connected third node. The current is increased or decreased in common according to the voltage of, and the amplification result of the input differential signal is output from the third node not connected in common.

  According to the differential amplifier circuit according to the first and second aspects, when the drive is performed so that one of the two commonly connected third nodes is increased, the other voltage is decreased. The reverse drive works like that. Therefore, even if the input differential signal changes, the voltage change of the two third nodes is suppressed.

  A differential amplifier circuit according to a third aspect of the present invention includes a first amplifying unit and a second amplifying unit for inputting a common differential signal. Each of the first amplifying unit and the second amplifying unit generates a first differential current that flows in a direction to be discharged from the first power supply line toward the second power supply line in response to the input differential signal. And a second differential current generator that generates a second differential current that flows in a direction of drawing from the first power supply line toward the second power supply line in response to the differential signal of the input. Part, a first cascode part that inputs one current of the first differential current and one current of the second differential current that are in a relationship of decreasing one when one increases, and the other when one increases And a second cascode portion for inputting the other one current of the first differential current and the other one current of the second differential current. Each of the first cascode section and the second cascode section includes a first node that inputs one current of the first differential current, and a second node that inputs one current of the second differential current; , A third node, a first conductivity type first transistor for controlling the current flowing from the first node to the second power supply line to be constant, and a current flowing from the first power supply line to the second node A second transistor of a second conductivity type that is controlled to keep constant, and an impedance that controls the impedance between the first node and the third node so that the voltage of the first node is kept constant. A third transistor of the first conductivity type, and a fourth transistor of the second conductivity type that controls an impedance between the second node and the third node so that the voltage of the second node is kept constant. Including. The third node of the first cascode part and the second cascode part in the second amplifying part is connected in common, and either one of the first transistor or the second transistor in the second amplifying part is Depending on the voltage of the third node connected in common, the current is increased or decreased in common, and one of the first transistor and the second transistor in the first amplifier is connected in common. In accordance with the voltage of the third node, the current is increased or decreased in common, and the differential signal of the input is amplified from the third node of the first cascode unit and the second cascode unit in the first amplifier unit. Output the result.

  According to the differential amplifier circuit of the third aspect, one of the first differential currents is applied to the first node of the first cascode unit and the first node of the second cascode unit in the second amplifier unit. Since each current is input, a current having a relationship in which when one increases, the other decreases. In addition, since each of the second differential currents is input to the second node of the first cascode unit and the second node of the second cascode unit in the second amplification unit, The node also receives a current having a relationship in which one increases and the other decreases. Therefore, in the two third nodes connected in common to the second amplifying unit, when driving is performed so that one voltage is increased, reverse driving is performed so that the other voltage is decreased. Therefore, even if the input differential signal changes, the voltage change of the two third nodes is suppressed.

  In the differential amplifier circuit according to the first aspect, the first transistor, the second transistor, the third transistor, and the fourth transistor may be insulated gate transistors. The first differential current generator includes a first pair of insulated gate transistors having the second conductivity type, each source being connected in common, and outputting the first differential current from each drain. And an insulated gate fifth transistor having the second conductivity type connected between the source of the first transistor pair and the first power supply line. The second differential current generator includes a pair of insulated gate second transistors having the first conductivity type, each source being connected in common, and outputting the second differential current from each drain. A sixth transistor of an insulated gate type having the first conductivity type and connected between the source of the second transistor pair and the second power supply line may be included. The gates of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor may be connected to the commonly connected third node.

  A receiver circuit according to a fourth aspect of the present invention includes a current-voltage conversion circuit that converts a differential current transmitted through a pair of signal lines into a differential voltage, and the above-described output from the current-voltage conversion circuit. A differential amplifier circuit that amplifies the differential voltage, and any of the differential amplifier circuits according to the first to third aspects is used as the differential amplifier circuit.

  An oscillation circuit according to a fifth aspect of the present invention includes an oscillation unit having a plurality of delay stages connected in a ring shape for delaying and outputting an input differential signal, and at least one of the plurality of delay stages And at least one differential amplifier circuit for amplifying the differential signal output from the first differential amplifier circuit. Any one of the differential amplifier circuits according to the first to third aspects is used as the differential amplifier circuit.

  An oscillation circuit according to a sixth aspect of the present invention includes a differential amplifier circuit that inputs and amplifies a difference between an input signal and a reference signal as a differential signal, and a differential current corresponding to the amplification result of the differential amplifier circuit Are output to a pair of signal lines, and any one of the differential amplifier circuits according to the first to third aspects is used as the differential amplifier circuit.

  According to the present invention, the bias voltage supplied to the transistor that generates the amplification result signal is less likely to fluctuate according to the differential input signal. Therefore, the delay time caused by the fluctuation of the bias voltage is suppressed, and The difference between the delay time and the delay time at the time of falling can be reduced.

FIG. 1 is a diagram illustrating a first configuration example of a differential amplifier circuit according to an embodiment of the present invention.
Before describing FIG. 1, first, the classification of bias systems of the differential amplifier circuit according to the present embodiment will be described by taking the differential amplifier circuit having a simple configuration shown in FIGS. 2 to 4 as an example.

FIG. 2A shows an example of a current mirror load type differential amplifier circuit 155 that is generally used as a differential input stage of a differential amplifier circuit for analog use.
The differential amplifier circuit 155 shown in FIG. 2A includes NMOS transistors MN51 and MN52, PMOS transistors MP61 and MP62, and a constant current source ISN3.

The NMOS transistors MN51 and MN52 are N-channel differential input transistors, and a common source thereof is connected to the GND line via the constant current source ISN3.
The non-inverted input signal IN (+) is input to the gate of the NMOS transistor MN51, and the inverted input signal IN (−) is input to the gate of the NMOS transistor MN52.
The drain of the NMOS transistor MN52 and the drain of the PMOS transistor MP62 are connected to each other, and a non-inverted output signal O (+) is generated at the node of the connection point.
The drain of the NMOS transistor MN51 and the drain of the PMOS transistor MP61 are connected to each other, and the inverted output signal O (−) is generated at the node XPGT at the connection point.
The PMOS transistors MP61 and MP62 constitute a current mirror type load circuit. The gates of the PMOS transistors MP61 and MP62 are commonly connected to the node XPGT, and the sources thereof are commonly connected to the VDD line. In this load circuit, the PMOS transistor MP61 constitutes a diode connection circuit in which a drain and a gate are connected.

  In the differential amplifier circuit 155 shown in FIG. 2A, the inverted output signal O (−) generated at the node XPGT has a smaller amplitude than the non-inverted output signal O (+). Cannot be input directly to the inverter. When the output signal of the differential amplifier circuit 155 is taken out for use as a comparator or the like, usually, an inverter is connected only to the non-inverted output signal O (+) having a large amplitude and is taken out as a single type signal.

When the non-inverted input signal IN (+) is at a low level and the inverted input signal IN (−) is at a high level, the NMOS transistor MN51 is turned off, and the inverted output signal (−) rises to the power supply voltage VDD side, and 'VDD−Vth 'Reach. At this time, the PMOS transistor MP61 constituting the diode connection circuit is turned off, and almost no current flows through the PMOS transistors MP61 and MP62. In this state, when the non-inverting input signal IN (+) changes from the low level to the high level and the inverting input signal IN (−) changes from the high level to the low level, the NMOS transistor MN51 is turned on and accumulated in the gate capacitances of the PMOS transistors MP61 and MP62. The extracted charge is extracted, and the voltage of the node XPGT decreases. The current flowing through the PMOS transistor MP62 gradually increases as the voltage at the node XPGT decreases.
In this way, in the differential amplifier circuit 155 shown in FIG. 2A, when the non-inverted output signal O (+) is at a low level, no current flows through the current mirror type load circuit. The delay time when +) rises from the low level to the high level becomes longer than the delay time at the fall. Therefore, the pulse width of the input signal and the pulse width of the output signal are different, which causes a problem in high-speed operation.

FIG. 2B shows an example of a current mirror load type differential amplifier circuit 156 that improves the above-described problems of the differential amplifier circuit 155 and is used in a data read comparator of an SRAM.
The differential amplifier circuit 156 shown in FIG. 2B includes a current mirror load type differential amplifier AMP21 that generates a non-inverted output signal O (+) and a current mirror load that generates an inverted output signal O (−). And a differential amplifier AMP22 of the type. The node (XPGT) that outputs the inverted signal in the differential amplifier AMP21 is commonly connected to the node (PGTb) that outputs the non-inverted signal in the differential amplifier AMP22, and is shared by both current mirror loads. A bias voltage is supplied.
The differential amplifier AMP21 has the same configuration as that of the differential amplifier circuit 155 shown in FIG.
The differential amplifier AMP22 includes NMOS transistors MN51b and MN52b, PMOS transistors MP61b and MP62b, and a constant current source ISN3b.

The NMOS transistors MN51b and MN52b are N-channel differential input transistors in the differential amplifier AMP22, and a common source thereof is connected to the GND line via the constant current source ISN3b. The sources of the differential input transistors (MN51b, MN52b) in the differential amplifier AMP22 are commonly connected to the sources of the differential input transistors (MN51, MN52) in the differential amplifier AMP21.
The non-inverted input signal IN (+) is input to the gate of the NMOS transistor MN51b, and the inverted input signal IN (−) is input to the gate of the NMOS transistor MN52b.
The drain of the NMOS transistor MN52b and the drain of the PMOS transistor MP62b are connected to each other, and the node at the connection point is connected to the node XPGT of the differential amplifier AMP21.
The drain of the NMOS transistor MN51b and the drain of the PMOS transistor MP61b are connected to each other, and an inverted output signal O (−) is generated at the node of the connection point.
The PMOS transistors MP61b and MP62b constitute a current mirror type load circuit. The gates b of the PMOS transistors MP61b and MP62 are commonly connected to the node XPGT of the differential amplifier AMP21, and the sources thereof are commonly connected to the VDD line. In the load circuit, the PMOS transistor MP62b constitutes a diode connection circuit in which the drain and the gate are connected.

  In the differential amplifier circuit 156, the drain of the PMOS transistor MP61 and MP62b constituting the diode connection circuit (node XPGT) is connected to the drain of the NMOS transistor MN51 that receives the non-inverted input signal IN (+) and the inverted input signal IN (− ) Is connected in parallel to the drain of the NMOS transistor MN52b. Even if the polarity of the differential input signal is positive or negative, since the NMOS transistor MN51 or MN52b is turned on, a current always flows through the PMOS transistors MP61 and MP62b constituting the diode connection circuit. As a result, the fluctuation of the bias voltage generated at the node XPGT is reduced and the charge / discharge time is shortened. Therefore, the delay time at the rise and the delay time at the fall of the non-inverted output signal O (+) are almost equal. Will be equal. The voltage waveform of the inverted output signal O (−) approximates a waveform obtained by inverting the waveform of the non-inverted output signal O (+) with the bias voltage at the node XPGT as the center.

  If the size of the differential input transistors is sufficiently large and the current is not regulated when they are on, the current flows to one of the PMOS transistors MP62 and MP61b, whereas the current flows to the PMOS transistors MP61 and MP62b. Current flows through both. Therefore, in the differential amplifier circuit 156, the number of gates of the transistors (MP61, MP62b, MN51, MN52b) involved in the generation of the bias voltage is the same as the number of gates of the transistors (MP62, MP61b, MN52, MN51b) involved in the signal output. However, it is possible to operate in half or half. However, if it is less than half, the small-size PMOS transistor constituting the diode connection circuit drives the gate capacitance of the PMOS transistor several times larger for signal output, and the balance is lost.

FIG. 3 shows an example of a differential amplifier circuit 157 that generates a bias voltage of a current mirror type load circuit by a pseudo circuit.
The differential amplifier circuit 157 shown in FIG. 3 includes a main body differential amplifier AMP23 and a bias voltage generation pseudo circuit PSAMP23.
The differential amplifier AMP23 of the main body includes NMOS transistors MN51 and MN52, PMOS transistors MP61 and MP62, and a constant current source ISN3.
The pseudo circuit PSAMP23 includes NMOS transistors MN51b and MN52b, PMOS transistors MP61b and MP62b, and a constant current source ISN3b.

In the differential amplifier AMP23 of the main body, NMOS transistors MN51 and MN52 are N-channel differential input transistors, and a common source thereof is connected to the GND line via a constant current source ISN3.
The non-inverted input signal IN (+) is input to the gate of the NMOS transistor MN51, and the inverted input signal IN (−) is input to the gate of the NMOS transistor MN52.
The drain of the NMOS transistor MN52 and the drain of the PMOS transistor MP62 are connected to each other, and a non-inverted output signal O (+) is generated at the node of the connection point.
The drain of the NMOS transistor MN51 and the drain of the PMOS transistor MP61 are connected to each other, and an inverted output signal O (−) is generated at the node of the connection point.
The gates of the PMOS transistors MP61 and MP62 receive the bias voltage BS generated by the pseudo circuit PSAMP23, and their sources are commonly connected to the VDD line.

In the pseudo circuit PSAMP23, the NMOS transistors MN51b and MN52b are N-channel differential input transistors, and a common source thereof is connected to the GND line via the constant current source ISN3b.
The non-inverted input signal IN (+) is input to the gate of the NMOS transistor MN51b, and the inverted input signal IN (−) is input to the gate of the NMOS transistor MN52b.
The drains of the NMOS transistor MN52b and the PMOS transistor MP62b and the drains of the NMOS transistor MN51b and the PMOS transistor MP61b are connected in common, and a bias voltage BS is generated at this common connection point. The bias voltage BS is input to the gates of the PMOS transistors MP61 and MP62, and is also input to the gates of the PMOS transistors MP61 and MP62 of the differential amplifier AMP23 described above. The sources of the PMOS transistors MP61 and MP62 are commonly connected to the VDD line.

  In the differential amplifier circuit 157, the drain of the PMOS transistor MP61b and the drain of the PMOS transistor MP62b, each of which constitutes a diode connection circuit, and the drain of the NMOS transistor MN51b that inputs the non-inverted input signal IN (+) and the inverted input signal IN ( The drain of the NMOS transistor MN52b for inputting-) is connected in parallel. Even if the polarity of the differential input signal is positive or negative, since the NMOS transistor MN51b or MN52b is turned on, a current always flows through the PMOS transistors MP61b and MP62b. At this time, each of the PMOS transistors MP61b and MP62b has a current that is half the current flowing through the constant current source ISN3b, that is, substantially the same current as when the differential input signal is balanced, so that the PMOS transistors MP61b and MP62b have their gates connected to the gates. Generates a constant bias voltage BS. As a result, the fluctuation of the bias voltage BS generated at the node XPGT becomes minute and the charge / discharge time is shortened. Therefore, the delay time when the non-inverted output signal O (+) rises and the delay time when it falls Are almost equal. The voltage waveform of the inverted output signal O (−) approximates a waveform obtained by inverting the waveform of the non-inverted output signal O (+) around the bias voltage of the node XPGT. The delay at the rise and fall is almost equal.

  In the differential amplifier circuit 157 shown in FIG. 3, since the bias voltage BS is generated inside the pseudo circuit PSAMP23, the number of gates of the transistors in the pseudo circuit PSAMP23 is made half the number of gates of the transistors in the differential amplifier AMP23 of the main body. It is possible to reduce the size. However, since the bias voltage BS is generated without being fed back to the differential amplifying unit AMP23 of the main body, the balance of circuit operation tends to be lost due to the influence of transistor characteristic variations.

FIG. 4 shows an example of a differential amplifier circuit that generates a bias voltage by connecting one inverted output and the other non-inverted output in two differential amplifiers.
4 is different from a current mirror load type differential amplifier AMP21 that generates a non-inverted output signal O (+) and a current mirror load type that generates an inverted output signal O (−). Dynamic amplification part AMP22. The node (XPGT) that outputs the inverted signal in the differential amplifier AMP21 is commonly connected to the node (PGTb) that outputs the non-inverted signal in the differential amplifier AMP22, and is shared by both current mirror loads. A bias voltage is supplied.

  The differential amplifiers AMP21 and AMP22 in the differential amplifier circuit 158 shown in FIG. 4 have the same configuration as the differential amplifiers AMP21 and AMP22 in the differential amplifier circuit 156 shown in FIG. The difference between the differential amplifier circuit 158 shown in FIG. 4 and the differential amplifier circuit 156 shown in FIG. 2B is that the differential input transistors (MN51 and MN52) of the differential amplifier AMP21 are connected in common. And the differentially connected source of the differential input transistors (MN51, MN52) of the differential amplifier AMP21 are separated from each other.

  In the differential amplifier circuit 158, the inverted output of the differential amplifier unit AMP21 and the non-inverted output of the differential amplifier unit AMP22 are connected, and two complementary outputs compete with each other. The drains of the PMOS transistors MP61 and MP62b constituting the diode connection circuit (node XPGT) are the drain of the NMOS transistor MN51 that receives the non-inverted input signal IN (+) and the NMOS transistor MN52b that receives the inverted input signal IN (−). Is connected in parallel with the drain of Even if the polarity of the differential input signal is positive or negative, since the NMOS transistor MN51 or MN52b is turned on, a current always flows through the PMOS transistors MP61 and MP62b constituting the diode connection circuit. At this time, the currents flowing through the PMOS transistors MP61 and MP62b are substantially the same as when the differential input signal is balanced, that is, half the current flowing through the constant current source ISN3 or the constant current source ISN3b. A constant bias voltage is generated at the gate (node XPGT) of MP62b. As a result, the fluctuation of the bias voltage generated at the node XPGT becomes minute, and the charge / discharge time is shortened. Therefore, the delay time when the non-inverted output signal O (+) rises and the delay time when it falls Almost equal. Further, since the voltage waveform of the inverted output signal O (−) approximates a waveform obtained by inverting the waveform of the non-inverted output signal O (+) around the bias voltage of the node XPGT, the inverted output signal O (−) As for, the delay at the rise and fall is almost equal.

  In the differential amplifier circuit 157 shown in FIG. 3, the balance of operation is easily lost due to the influence of variations in transistor characteristics, whereas in the differential amplifier circuit 158 shown in FIG. 4, the transistor characteristics vary slightly. It operates stably as in the differential amplifier circuit 156 shown in FIG.

  Among these four differential amplifier circuits 155 to 158, the differential amplifier circuit 155 shown in FIG. 2A can be classified as a self-bias type, and the differential amplifier circuit 157 shown in FIG. 3 can be classified as a pseudo circuit bias type. A differential amplifier circuit 158 shown in FIG. 4 generates a bias voltage by connecting one inverted output and the other non-inverted output of two differential amplifiers and competing for complementary outputs. Therefore, here, it will be classified as “competitive bias type”. The differential amplifier circuit 156 shown in FIG. 2B is an intermediate type between the competitive bias type and the pseudo circuit bias type.

  As can be seen from the above classification, in addition to the pseudo-circuit bias type, there is competition as a circuit method that reduces the difference in the delay time between the rise time and fall time of the output signal by reducing the fluctuation of the bias voltage of the differential amplifier circuit. A bias type is conceivable. The differential amplifier circuit 101 shown in FIG. 1 corresponds to this competitive bias type.

Turning to the description of FIG.
A differential amplifier circuit 101 illustrated in FIG. 1 includes amplifiers AMP1 and AMP2.

[Amplifier AMP1]
The amplifying unit AMP1 includes differential current generating units 11 and 12 and cascode units 21 and 22.

The differential current generator 11 is a circuit that generates a differential current that flows in the direction of discharging from the VDD line toward the GND line, and includes, for example, PMOS transistors MP11 and MP12 and a constant current source ISP1 as shown in FIG. .
The PMOS transistors MP11 and MP12 have their sources connected in common and output a differential current from their drains. The constant current source ISP1 allows a constant current to flow from the VDD line to the commonly connected sources of the PMOS transistors MP11 and MP2. A non-inverted input signal IN (+) is input to the gate of the PMOS transistor MP11, and an inverted input signal IN (−) is input to the gate of the PMOS transistor MP12.

The differential current generator 12 is a circuit that generates a differential current that flows in the direction of drawing from the VDD line toward the GND line. For example, as shown in FIG. 1, the differential current generator 12 includes NMOS transistors MN11 and MN12 and a constant current source ISN1. .
The NMOS transistors MN11 and MN12 have their sources connected in common and output a differential current from their drains. The constant current source ISN1 allows a constant current to flow from the commonly connected sources of the NMOS transistors MN11 and MN2 to the GND line. The non-inverted input signal IN (+) is input to the gate of the NMOS transistor MN11, and the inverted input signal IN (−) is input to the gate of the NMOS transistor MN12.

The cascode unit 21 inputs a differential current 1 generated in the differential current generation unit 11 and a differential current 1 generated in the differential current generation unit 12, and inputs these two input currents. A cascode amplifier circuit that generates a corresponding output current is configured. The two currents input to the cascode portion 21 have a relationship in which when one increases, the other decreases.
As shown in FIG. 1, for example, the cascode section 21 includes NMOS transistors MN21 and MN23 and PMOS transistors MP21 and MP23.
The NMOS transistor MN21 controls the current flowing from the node N11 to the GND line so as to be kept constant according to the voltage of the node N31. The drain of the NMOS transistor MN21 is connected to the node N11, its source is connected to the GND line, and its gate is connected to the node N31.
The NMOS transistor MN23 controls the impedance between the node N31 and the node N11 so that the voltage of the node N11 is kept constant. The source of the NMOS transistor MN23 is connected to the node N11, the drain thereof is connected to the node N31, and a predetermined bias voltage BN2 is supplied to the gate thereof.
The PMOS transistor MP21 controls the current flowing from the VDD line to the node N21 so as to be kept constant according to a predetermined bias voltage BP1. The drain of the PMOS transistor MP21 is connected to the node N21, the source is connected to the VDD line, and the bias voltage BP1 is supplied to the gate.
The PMOS transistor MP23 controls the impedance between the node N21 and the node N31 so that the voltage of the node N21 is kept constant. The source of the PMOS transistor MP23 is connected to the node N21, the drain thereof is connected to the node N31, and a predetermined bias voltage BP2 is supplied to the gate thereof.
The node N11 receives one of the differential currents generated in the differential current generator 11 (the drain current of the PMOS transistor MP11 in the example of FIG. 1).
The node N21 receives one of the differential currents generated in the differential current generator 12 (the drain current of the NMOS transistor MN11 in the example of FIG. 1).

The cascode unit 22 includes another one of the differential currents generated in the differential current generation unit 11 (the current not input to the cascode unit 21) and the other differential currents generated in the differential current generation unit 12. The cascode amplifier circuit is configured to input one current (current not input to the cascode section 21) and generate an output current corresponding to these two input currents. The two currents input to the cascode portion 22 have a relationship in which when one increases, the other decreases.
As shown in FIG. 1, for example, the cascode unit 22 includes NMOS transistors MN22 and MN24 and PMOS transistors MP22 and MP24.
The NMOS transistor MN22 controls the current flowing from the node N12 to the GND line so as to be kept constant according to the voltage of the node N31. The drain of the NMOS transistor MN22 is connected to the node N12, its source is connected to the GND line, and its gate is connected to the node N31.
The NMOS transistor MN24 controls the impedance between the node N32 and the node N12 so that the voltage of the node N12 is kept constant. The source of the NMOS transistor MN24 is connected to the node N12, the drain thereof is connected to the node N32, and the bias voltage BN2 is supplied to the gate thereof.
The PMOS transistor MP22 controls the current flowing from the VDD line to the node N22 so as to be kept constant according to the bias voltage BP1. The drain of the PMOS transistor MP22 is connected to the node N22, the source is connected to the VDD line, and the bias voltage BP1 is supplied to the gate.
The PMOS transistor MP24 controls the impedance between the node N22 and the node N32 so that the voltage of the node N22 is kept constant. The source of the PMOS transistor MP24 is connected to the node N22, the drain thereof is connected to the node N32, and a predetermined bias voltage BP2 is supplied to the gate thereof.
The node N12 receives one of the differential currents generated in the differential current generator 11 (in the example of FIG. 1, the drain current of the PMOS transistor MP12).
One of the differential currents generated in the differential current generator 12 (the drain current of the NMOS transistor MN12 in the example of FIG. 1) is input to the node N22.

[Amplifier AMP2]
The amplifying unit AMP2 includes differential current generating units 11b and 12b and cascode units 21b and 22b.

The differential current generator 11b is a circuit that generates a differential current that flows in the direction of discharging from the VDD line toward the GND line. For example, as shown in FIG. 1, the differential current generator 11b includes PMOS transistors MP11b and MP12b and a constant current source ISP1b. .
The PMOS transistors MP11b and MP12b have their sources connected in common and output a differential current from their drains. The constant current source ISP1b allows a constant current to flow from the VDD line to the commonly connected sources of the PMOS transistors MP11b and MP12b. The non-inverted input signal IN (+) is input to the gate of the PMOS transistor MP11b, and the inverted input signal IN (−) is input to the gate of the PMOS transistor MP12b.

The differential current generator 12b is a circuit that generates a differential current that flows in the direction of drawing from the VDD line toward the GND line. For example, as shown in FIG. 1, the differential current generator 12b includes NMOS transistors MN11b and MN12b and a constant current source ISN1b. .
The NMOS transistors MN11b and MN12b have their sources connected in common and output a differential current from their drains. The constant current source ISN1b allows a constant current to flow from the commonly connected sources of the NMOS transistors MN11b and MN12b to the GND line. The non-inverted input signal IN (+) is input to the gate of the NMOS transistor MN11b, and the inverted input signal IN (−) is input to the gate of the NMOS transistor MN12b.

The cascode unit 21b inputs a differential current 1 generated in the differential current generation unit 11b and a differential current 1 generated in the differential current generation unit 12b, and inputs these two input currents. A cascode amplifier circuit that generates a corresponding output current is configured. The two currents input to the cascode portion 21b have a relationship in which when one increases, the other decreases.
For example, as shown in FIG. 1, the cascode portion 21b includes NMOS transistors MN21b and MN23b and PMOS transistors MP21b and MP23b.
The NMOS transistor MN21b controls to keep the current flowing from the node N11b to the GND line constant according to the voltage of the node N32b. The drain of the NMOS transistor MN21b is connected to the node N11b, its source is connected to the GND line, and its gate is connected to the node N32b.
The NMOS transistor MN23b controls the impedance between the node N31b and the node N11b so that the voltage of the node N11b is kept constant. The source of the NMOS transistor MN23b is connected to the node N11b, the drain thereof is connected to the node N31b, and a predetermined bias voltage BN2 is supplied to the gate thereof.
The PMOS transistor MP21b controls the current flowing from the VDD line to the node N21b so as to be kept constant according to the bias voltage BP1. The drain of the PMOS transistor MP21b is connected to the node N21b, the source is connected to the VDD line, and the bias voltage BP1 is supplied to the gate.
The PMOS transistor MP23b controls the impedance between the node N21b and the node N31b so that the voltage of the node N21b is kept constant. The source of the PMOS transistor MP23b is connected to the node N21b, the drain thereof is connected to the node N31b, and the bias voltage BP2 is supplied to the gate thereof.
The node N11b receives one of the differential currents generated in the differential current generator 11b (in the example of FIG. 1, the drain current of the PMOS transistor MP11b).
The node N21b receives one of the differential currents generated in the differential current generator 12b (in the example of FIG. 1, the drain current of the NMOS transistor MN11b).

The cascode unit 22b is configured to receive another one of the differential currents generated in the differential current generation unit 11b (the current that is not input to the cascode unit 21b) and another differential current generated in the differential current generation unit 12b. The cascode amplifier circuit is configured to input one current (current not input to the cascode portion 21b) and generate an output current corresponding to these two input currents. The two currents input to the cascode portion 22b have a relationship in which when one increases, the other decreases.
As shown in FIG. 1, for example, the cascode section 22b includes NMOS transistors MN22b and MN24b and PMOS transistors MP22b and MP24b.
The NMOS transistor MN22b controls the current flowing from the node N12b to the GND line to be kept constant according to the voltage of the node N32b. The drain of the NMOS transistor MN22b is connected to the node N12b, its source is connected to the GND line, and its gate is connected to the node N32b.
The NMOS transistor MN24b controls the impedance between the node N32b and the node N12b so that the voltage of the node N12b is kept constant. The source of the NMOS transistor MN24b is connected to the node N12b, the drain thereof is connected to the node N32b, and the bias voltage BN2 is supplied to the gate thereof.
The PMOS transistor MP22b controls to keep the current flowing from the VDD line to the node N22b constant according to the bias voltage BP1. The drain of the PMOS transistor MP22b is connected to the node N22b, the source is connected to the VDD line, and the bias voltage BP1 is supplied to the gate.
The PMOS transistor MP24b controls the impedance between the node N22b and the node N32b so that the voltage of the node N22b is kept constant. The source of the PMOS transistor MP24b is connected to the node N22b, the drain thereof is connected to the node N32b, and a predetermined bias voltage BP2 is supplied to the gate thereof.
The node N12b receives one of the differential currents generated in the differential current generator 11b (in the example of FIG. 1, the drain current of the PMOS transistor MP12b).
The node N22b receives one of the differential currents generated in the differential current generator 12b (the drain current of the NMOS transistor MN12b in the example of FIG. 1).

The node N31 of the cascode unit 21 in the amplification unit AMP1 is connected to the node N32b of the cascode unit 22b in the amplification unit AMP2.
On the other hand, the non-inverted output signal O (+) is output from the node N32 of the cascode unit 22 in the amplification unit AMP1, and the inverted output signal O (+) is output from the node N31b of the cascode unit 21b in the amplification unit AMP2. The two output signals (O (+), O (−)) are the differential signals output from the differential amplifier circuit 101 as a result of amplifying the input differential signals (IN (+), IN (−)). It is.

In the differential amplifier circuit 101 having the above-described configuration, the node N31 and the node N32b have a complementary relationship in which when one voltage is increased when the other is disconnected, the other voltage is decreased. That is, when the two amplifying units are made independent by separating the two, the node N31 is the inverting output of the amplifying unit AMP1, and the node N32 is the non-inverting output of the amplifying unit AMP2. In the differential amplifier circuit 101, the complementary outputs are connected to compete with each other to stabilize the bias voltage generated at the connection point.
For example, when the voltage difference increases in the positive polarity where the non-inverted input signal IN (+) is higher than the inverted input signal IN (−), the drain current of the PMOS transistor MP11 decreases and the drain current of the NMOS transistor MN11. Increases, the current of the PMOS transistor MP23 decreases and the current of the NMOS transistor MN23 increases. On the other hand, in this case, since the drain current of the PMOS transistor MP12b increases and the drain current of the NMOS transistor MN12b decreases, the current of the PMOS transistor MP24b increases and the current of the NMOS transistor MN24b decreases. As a result, the current decrease in the PMOS transistor MP23 and the current increase in the PMOS transistor MP24b cancel each other, and the current increase in the NMOS transistor MN23 and the current decrease in the NMOS transistor MN24b cancel each other, so that the bias voltage generated at the nodes N31 and N32b. Is kept almost constant.

  As described above, according to the differential amplifier circuit 101 shown in FIG. 1, the bias voltage generated at the nodes N31 and N32b becomes almost constant regardless of whether the polarity of the differential input signal changes between positive and negative. The current always flows through the load transistors (MN21, MN22, MN21b, MN22b) on the N channel side of the unit. As a result, the time required for charging and discharging the nodes N31 and N32b becomes very short, so that the delay time when the non-inverted output signal O (+) rises and the delay time when it falls can be made substantially equal. Further, the voltage waveform of the inverted output signal O (−) approximates a waveform obtained by inverting the waveform of the non-inverted output signal O (+) around the bias voltage generated at the nodes N31 and N32b. Also for O (−), the delay time at the time of rise and at the time of fall can be made substantially equal as in the non-inverted output signal O (+). When the delay time at the rise time and the fall time are substantially equal, the pulse width of the input signal and the pulse width of the output signal become substantially the same, and the duty ratio of the pulse of the output signal deviates from a desired value (for example, 50%). Therefore, it is possible to suppress the reduction of the operation margin due to the above, and thus it can be applied to a high-speed circuit.

  In addition, the rail-to-rail (registered trademark) type CMOS differential amplifier circuit features a wide input voltage range and power supply voltage range because the average value (common mode voltage) of complementary output voltages for bias is fed back. Will not be damaged.

  Next, a second configuration example of the differential amplifier circuit according to the embodiment of the present invention will be described with reference to FIG.

The differential amplifier circuit 102 of the second configuration example illustrated in FIG. 5 includes an amplifier unit AMP1 and PSAMP2.
The amplifying unit AMP1 is the same as the components with the same reference numerals in the differential amplifier circuit 101 shown in FIG.

The amplification unit PSAMP2 is obtained by deleting the cascode unit 21b on the inverting output side of the amplification unit AMP2 that does not contribute to the generation of the bias voltage in the differential amplification circuit 101 shown in FIG. It is.
The drains of the NMOS transistors MN11b and MP11b connected to the deleted cascode portion 21b are preferably connected to each other as shown in FIG. However, if the function of the non-inverted output side of the amplifier unit PSAMP2 is not significantly affected, the drain of the NMOS transistor MN11b is connected to the VDD line, the drain of the PMOS transistor MP11b is connected to the GND line, and both drains are connected. An open state (that is, a state in which the cascode portion 21b is deleted) may be used.

  Also in the differential amplifier circuit 102 of the second configuration example described above, as in the differential amplifier circuit 101 of the first configuration example, the bias voltage generated at the nodes N31 and N32b changes the polarity of the differential input signal. Regardless, it becomes almost constant, and a current always flows through the load transistors (MN21, MN22, MN22b) on the N channel side of each cascode portion. As a result, the time required for charging and discharging the nodes N31 and N32b becomes very short, so that the delay time when the non-inverted output signal O (+) rises and the delay time when it falls can be made substantially equal. When the delay time at the time of rising and that at the time of falling are substantially equal, the pulse width of the input signal and the pulse width of the output signal become substantially the same, so that it can be applied to a high-speed circuit.

FIG. 6 is a diagram illustrating an example of voltage waveform simulation results in the differential amplifier circuit 102 of the second configuration example illustrated in FIG. 5 and the self-bias type differential amplifier circuit 151 illustrated in FIG. In the example of FIG. 6, the simulation is performed under the conditions in which the power supply voltage VDD, the voltage amplitude Vin of the input differential signal, and the frequency f of the input differential signal are set as follows.
VDD = 2.5 [V];
Vin = 1.25 [V] ± 50 [mV];
f = 200 [MHz];

In FIG. 6, solid lines 'IN (+)' and 'IN (-)' indicate voltage waveforms of complementary input signals.
A solid line “O (+)” indicates a non-inverted output signal of the differential amplifier circuit 102, and a dotted line “O (+) _ o” indicates a non-inverted output signal of the differential amplifier circuit 151.
A solid line 'INV_O (+)' indicates a signal obtained by receiving and outputting the non-inverted output signal of the differential amplifier circuit 102 by an inverter, and a dotted line 'INV_O (+) _ o' indicates the non-inverted output signal of the differential amplifier circuit 151 as an inverter. The signal received and output at.
A solid line 'BS' indicates a bias voltage (voltage at nodes N31 and N31b) of the differential amplifier circuit 102, and a dotted line 'BS_o' indicates a bias voltage (voltage at node N61) of the differential amplifier circuit 151.

  As shown in the simulation result of FIG. 6, in the differential amplifier circuit 151 shown in FIG. 16, the delay time at the rise of the output signal ('O (+) _ o') is different from the delay time at the fall. As a result, the pulse width of the input signal is different from the pulse width of the output signal. On the other hand, in the differential amplifier circuit 102 shown in FIG. 5, the delay times of both are substantially equal, and the pulse width of the input / output signal is kept constant. Further, the fluctuation of the bias voltage ('BS') of the differential amplifier circuit 102 shown in FIG. 5 is smaller than that of the bias voltage ('BS_o') of the differential amplifier circuit 151 shown in FIG.

FIG. 7 is a diagram illustrating an example of simulation results of current waveforms in the differential amplifier circuit 102 of the second configuration example illustrated in FIG. 5 and the self-bias type differential amplifier circuit 151 illustrated in FIG. The simulation conditions in the example of FIG. 5 are the same as those in FIG.
In FIG. 7A, solid lines “IN (+)” and “IN (−)” indicate voltage waveforms of complementary input signals.
In FIG. 7B, solid lines 'I (MN23)' and 'I (MP23)' indicate current waveforms of the NMOS transistor MN23 and the PMOS transistor MP23 in the differential amplifier circuit 102. Dotted lines 'I (MN43)' and 'I (MP43)' indicate current waveforms of the NMOS transistor MN43 and the PMOS transistor MP43 in the differential amplifier circuit 151.
In FIG. 7C, solid lines “I (MN24)” and “I (MP24)” indicate current waveforms of the NMOS transistor MN24 and the PMOS transistor MP24 in the differential amplifier circuit 102. Dotted lines 'I (MN44)' and 'I (MP44)' indicate current waveforms of the NMOS transistor MN44 and the PMOS transistor MP44 in the differential amplifier circuit 151.

As shown in the simulation result of FIG. 7, in the differential amplifier circuit 151, when the non-inverted input signal IN (+) is at the high level and the inverted input signal IN (−) is at the low level, the currents of the NMOS transistor MN43 and the PMOS transistor MP43 are Since both decrease, when the non-inverted input signal IN (+) changes from the high level to the low level and the inverted input signal IN (−) changes from the low level to the high level, the current rise of the NMOS transistor MN44 and the PMOS transistor MP44. Timing is delayed.
On the other hand, in the differential amplifier circuit 102, even when the non-inverting input signal IN (+) is high level and the inverting input signal IN (−) is low level, the current of the NMOS transistor MN23 does not decrease. When (+) changes from a high level to a low level and the inverted input signal IN (−) changes from a low level to a high level, the currents of the NMOS transistor MN24 and the PMOS transistor MP24 rise quickly following this change.

  As shown in the simulation results of FIGS. 6 and 7, the differential amplifier circuit 102 according to the present embodiment can realize a high-speed operation of several hundred MHz even with a low power supply voltage of about “2 × Vth”.

  Next, a third configuration example of the differential amplifier circuit according to the present embodiment will be described with reference to FIG.

A differential amplifier circuit 103 illustrated in FIG. 8 includes amplifiers AMP1 and AMP3.
The amplifying unit AMP1 is the same as the components with the same reference numerals in the differential amplifier circuit 101 shown in FIG.

  The amplifying unit AMP3 supplies a predetermined bias voltage BN1 to the gates of the N-channel side load transistors (MN21b, MN22b) in the cascode units 21b and 22b, and a node N32b to the gate of the P-channel side load transistors (MP21b, MP22b). The amplifying unit AMP2 is modified so as to supply the same voltage, and the other configuration is the same as that of the amplifying unit AMP2.

  In the differential amplifier circuit 103 of the third configuration example described above, as with the differential amplifier circuit 101 of the first configuration example, the bias voltage BS generated at the nodes N31 and N32b changes the polarity of the differential input signal. Regardless, it is almost constant, and the N-channel load transistors (MN21, MN22) in the cascode portions 21 and 22 of the amplifier AMP1 and the P-channel load transistors (MP21b, MP22b) in the cascode portions 21b, 22b of the amplifier AMP3. Always has a current flowing through it. As a result, the time required for charging and discharging the nodes N31 and N32b becomes very short, so that the delay time when the non-inverted output signal O (+) rises and the delay time when it falls can be made substantially equal. Further, the voltage waveform of the inverted output signal O (−) approximates a waveform obtained by inverting the waveform of the non-inverted output signal O (+) around the bias voltage generated at the nodes N31 and N32b. Also for O (−), the delay time at the time of rise and at the time of fall can be made substantially equal as in the non-inverted output signal O (+). When the delay time at the time of rising and that at the time of falling are substantially equal, the pulse width of the input signal and the pulse width of the output signal become substantially the same, so that it can be applied to a high-speed circuit.

  In the differential amplifier circuit 103 described above, the load transistor biasing methods in the amplifiers AMP1 and AMP3 are different. Therefore, in order to reduce the fluctuation of the bias voltage generated at the nodes N31 and N32b, for example, the size of the NMOS transistors MN21b and MN22b is made larger than the size of the NMOS transistors MN21 and MN22, or the size of the PMOS transistors MP21b and MP22b is increased. A method of balancing the circuit operation by making the size smaller than the size of the PMOS transistors MP21 and MP22 is effective.

  Next, a fourth configuration example of the differential amplifier circuit according to the present embodiment will be described with reference to FIG.

The differential amplifier circuit 104 illustrated in FIG. 9 includes amplifiers AMP1 and PSAMP3.
The amplifying unit AMP1 is the same as the components with the same reference numerals in the differential amplifier circuit 101 shown in FIG.

  The amplifying unit PSAMP3 supplies a predetermined bias voltage BN1 to the gate of the N-channel side load transistor (MN22b) in the cascode unit 22b, and supplies the voltage of the node N32b to the gate of the P-channel side load transistor (MP22b). The amplifier unit PSAMP2 is modified, and the other configuration is the same as that of the amplifier unit PSAMP2.

  In the differential amplifier circuit 104 of the fourth configuration example described above, as in the differential amplifier circuit 102 of the second configuration example, the bias voltage generated at the nodes N31 and N32b changes the polarity of the differential input signal. Regardless of this, the current always flows through the N-channel side load transistors (MN21, MN22) in the cascode portion 21 of the amplifier AMP1 and the P-channel side load transistor (MN22b) in the cascode portion 22b of the amplifier PSAMP3. It becomes a state. As a result, the time required for charging and discharging the nodes N31 and N32b becomes very short, so that the delay time when the non-inverted output signal O (+) rises and the delay time when it falls can be made substantially equal. When the delay time at the time of rising and the time of falling are substantially equal, the pulse width of the input signal and the pulse width of the output signal become substantially the same, so that it can be applied to a high-speed circuit.

  In the above-described differential amplifier circuit 104, the load transistor biasing methods in the amplifiers AMP1 and PSAMP3 are different. Therefore, in order to reduce the fluctuation of the bias voltage generated at the nodes N31 and N32b, for example, the size of the NMOS transistor MN22b is made larger than the sizes of the NMOS transistors MN21 and MN22, or the size of the PMOS transistor MP22b is changed to the PMOS transistor MP21. , And a method of balancing circuit operations by making the size smaller than the size of MP22 is effective.

  Next, a fifth configuration example of the differential amplifier circuit according to the present embodiment will be described with reference to FIG.

A differential amplifier circuit 105 illustrated in FIG. 10 is a pseudo-circuit bias type differential amplifier circuit, and includes an amplifier unit AMP4 and PSAMP4.
The amplifying unit AMP4 supplies the bias voltage BS generated by the amplifying unit PSAMP4 to the gates of the N-channel side load transistors (MN21, MN22) in the cascode units 21 and 22, and the inverted output signal O ( The amplifying unit AMP1 is modified to output-), and the other configuration is the same as that of the amplifying unit AMP1.
The amplifying unit PSAMP4 is obtained by modifying the amplifying unit AMP2 so that the node N31b of the cascode unit 21b and the node N32b of the cascode unit 22b are connected in common and a bias voltage BS generated at the connection point is supplied to the amplifying unit AMP4. Other configurations are the same as those of the amplification unit AMP2.

In the differential amplifier circuit 105 having the above-described configuration, the node N31b and the node N32b of the amplifying unit PSAMP4 have a complementary relationship in which when one voltage increases, the other voltage decreases when they are separated from each other. . In the differential amplifier circuit 105, the complementary outputs are connected to generate a constant bias voltage generated at the connection point.
For example, when the voltage difference increases in the positive polarity where the non-inverted input signal IN (+) is higher than the inverted input signal IN (−), the drain current of the PMOS transistor MP11b decreases and the drain current of the NMOS transistor MN11b. Increases, the current of the PMOS transistor MP23b decreases and the current of the NMOS transistor MN23b increases. On the other hand, in this case, since the drain current of the PMOS transistor MP12b increases and the drain current of the NMOS transistor MN12b decreases, the current of the PMOS transistor MP24b increases and the current of the NMOS transistor MN24b decreases. As a result, the current decrease in the PMOS transistor MP23b and the current increase in the PMOS transistor MP24b cancel each other, and the current increase in the NMOS transistor MN23b and the current decrease in the NMOS transistor MN24b cancel each other. BS is kept almost constant.

  As described above, according to the differential amplifier circuit 105 shown in FIG. 10, the bias voltage BS generated at the nodes N31b and N32b becomes substantially constant regardless of whether the polarity of the differential input signal changes to positive or negative. A current always flows through the load transistors (MN21, MN22, MN21b, MN22b) on the N channel side of the cascode portion. As a result, the time required for charging and discharging the nodes N31b and N32b becomes very short, so that the delay time when the non-inverted output signal O (+) rises and the delay time when it falls can be made substantially equal. Also, for the inverted output signal O (−), similarly to the non-inverted output signal O (+), the delay time at the rise time and the fall time can be made substantially equal. When the delay time at the time of rising and that at the time of falling are substantially equal, the pulse width of the input signal and the pulse width of the output signal become substantially the same, so that it can be applied to a high-speed circuit.

  Further, according to the differential amplifier circuit 106 shown in FIG. 10, since the bias voltage BS is generated inside the amplification unit PSAMP4, the number of gates of the transistors in the amplification unit PSAMP4 is reduced to half the number of gates of the transistors in the amplification unit AMP4. It is possible to reduce the circuit size by reducing the number of circuits.

  Next, a sixth configuration example of the differential amplifier circuit according to the present embodiment will be described with reference to FIG.

A differential amplifier circuit 106 illustrated in FIG. 11 is a self-biased differential amplifier circuit, and includes amplifiers AMP5 and AMP6.
The amplifying unit AMP5 modifies the amplifying unit AMP1 so that the constant current source ISP1 in the differential current generating unit 11 is replaced with the PMOS transistor MSP1, and the constant current source ISN1 in the differential current generating unit 12 is replaced with the NMOS transistor MSN1. It is what.
The amplifying unit AMP6 modifies the amplifying unit AMP2 so that the constant current source ISP1b in the differential current generating unit 11b is replaced with the PMOS transistor MSP1b, and the constant current source ISN1b in the differential current generating unit 12b is replaced with the NMOS transistor MSN1b. It is what.
Also, the node N31 of the amplifier AMP5 and the node N32b of the amplifier AMP6 are connected in common, and the bias voltage BS generated at this connection point is a constant current source transistor (MSN1, MSP1, MSN1b, MSP1b). And gates of cascode transistors (MN21 to MN24, MP21 to MN24, MN21b to MN24b, MP21b to MN24b), respectively.

  That is, in the differential amplifier circuit 106 shown in FIG. 11, the bias voltages BN1, BP1, and BP2 supplied to the differential amplifier circuit 101 shown in FIG. 1 are shared with the bias voltage BS generated at the nodes N31 and N32b, The bias voltage supplied to the transistors constituting the current source is also covered by the bias voltage BS generated at the nodes N31 and N32b.

  According to the above-described differential amplifier circuit 106, the bias voltage BS generated at the nodes N31 and N32b becomes substantially constant regardless of the change in the polarity of the differential input signal, and the load transistor in the cascode portion is always in a state where current flows. become. As a result, the time required for charging and discharging the nodes N31 and N32b becomes very short, so that the delay time at the rise time and the delay time at the fall time of the non-inverted output signal O (+) and the inverted output signal O (−) are reduced. Can be approximately equal. When the delay time at the time of rising and that at the time of falling are substantially equal, the pulse width of the input signal and the pulse width of the output signal become substantially the same, so that it can be applied to a high-speed circuit.

Next, an LVDS circuit to which the differential amplifier circuit according to this embodiment is applied will be described with reference to FIG.
When transferring image data generated by an image sensor mounted on a mobile device to another signal processing chip at high speed, or when transferring a large amount of image data to a thin display panel mounted on a mobile device. In order to reduce the number of digital signals that make up the system and reduce the size and weight of the system, and to significantly reduce the generation of unwanted radiation that affects image quality, differential signal technology with a small amplitude typified by LVDS Is used.

In the example of FIG. 12, the transmission side circuit includes a parallel / serial conversion circuit 201 and an LVDS driver 202.
The LVDS driver 202 includes drivers DV0 to DVn each driving a pair of signal lines, and a PLL circuit U1 that generates a clock signal CK2 synchronized with the input clock signal CK1.

  Based on the clock signal CK1 having the frequency Φ × 1, the PLL circuit U1 generates a clock signal having the frequency Φ × n obtained by multiplying the frequency by n.

  The parallel / serial conversion circuit 201 captures n-bit parallel data (image data, control signal, etc.) in synchronization with the clock signal having the frequency Φ × 1 supplied from the PLL circuit U1, and takes this as a clock having the frequency Φ × n. The data is converted into serialized data SD1 to SDn in synchronization with the signal.

  The drivers DV1 to DVn receive serial data SD1 to SDn, respectively, and drive a signal line pair for data transmission according to the input data. From the positive and negative output terminals of the drivers DV1 to DVn, a differential signal in which the direction of current flow is switched at a frequency Φ × n (bit rate of several hundred MHz) is output.

  The clock signal transmission driver DV0 drives the signal line pair for clock transmission in accordance with the synchronization clock signal CK2 (frequency Φ × n or Φ × 1) output from the PLL circuit U1. From the positive and negative output terminals of the driver DV0, the direction of current flow is switched at a frequency Φ × n or Φ × 1 (a bit rate of several hundred MHz or a 1 / n bit rate thereof) according to the frequency of the clock signal CK2. A differential signal is output.

On the other hand, in the example of FIG. 12, the circuit on the receiving side is constituted by a serial / parallel conversion circuit 203 and an LVDS receiver 204.
The LVDS receiver 204 includes termination resistors RT0 to RTn, receivers RV0 to RVn each amplifying differential signals transmitted by a pair of signal lines, and a clock signal CK4 synchronized with the clock signal CK3 received by the receiver RV0. PLL circuit U2 for generating

  The differential currents flowing in the signal pairs by driving the drivers DV0 to DV1 are converted into differential voltages having amplitudes of, for example, 100 mVp-p to 350 mVp-p in the termination resistors RT0 to RTn, and input to the receivers RV0 to RVn. Is done.

The receivers RV1 to RVn amplify the signals converted into differential voltages by the termination resistors RT1 to RTn, convert them into single-format serial data SD1 to SDn, and output them.
The receiver RV0 amplifies the signal converted into the differential voltage by the termination resistor RT0, converts the signal into a single format clock signal CK3, and outputs it.

The PLL circuit U2 generates clock signals with frequencies Φ × 1 and Φ × n based on the clock signal CK3.
The serial / parallel conversion circuit 203 takes in the serial data SD1 to SDn received in synchronization with the clock signal having the frequency Φ × n supplied from the PLL circuit U2, and the frequency Φ × 1 supplied from the PLL circuit U2. Are converted into n-bit parallel data in synchronization with the clock signal. The data parallelized by the serial / parallel conversion circuit 203 is written in, for example, an input side register of a D / A converter.

  In a system in which semiconductor integrated circuits mounted on different substrates are connected with small-amplitude differential signal wirings, such as the LVDS driver 202 and the LVDS receiver 204 shown in FIG. 12, the GND potential of the driver side substrate and the receiver side The GND potential of the substrate may vary separately or crosstalk may occur between wirings, which is an obstacle to the accurate transmission of signals. In the LVDS standard, the fluctuation range of the common mode voltage of the differential signal is stipulated, and in order to cope with this, a general-purpose receiver has a CMOS differential amplification that operates on rail-to-rail (registered trademark). Circuits are often used. In addition, with the miniaturization of semiconductor processes, the power supply voltage for analog circuits is required to be further reduced to, for example, 1.5V to 2.5V. For example, in a low power supply voltage LVDS (sub_LVDS) for a cellular phone, an operation speed of several hundred MHz is required at a low power supply voltage of about 2 × Vth.

For example, when the differential amplifier circuit 151 shown in FIG. 16 is used as the receivers RV0 to RVn, the delay time at the rise of the output and the delay time at the fall of the output are different. Therefore, the pulse width of the input signal and the pulse width of the output signal Unlike this, the operation margin is reduced by deviating from the optimum duty ratio. As a result, it becomes difficult to operate the circuit at high speed.
When the differential amplifier circuit 152 shown in FIG. 17 is used as the receivers RV0 to RVn, the control by the common feedback circuit 51 is not in time, and the bias voltage is greatly deviated from the optimum value, so that normal operation becomes difficult.
When the self-bias type differential amplifier circuit 153 shown in FIG. 18 or the differential amplifier circuit 154 shown in FIG. 21 is used as the receivers RV0 to RVn, the receivers RV0 to RVn can be operated with a low power supply voltage of about “2 × Vth”. Have difficulty.

  Therefore, as the receivers RV0 to RVn, the differential amplifier circuit 101 of the first configuration example shown in FIG. 1, the differential amplifier circuit 102 of the second configuration example shown in FIG. 5, and the third configuration example of FIG. If the differential amplifier circuit 103, the differential amplifier circuit 104 of the fourth configuration example shown in FIG. 9, and the differential amplifier circuit 105 of the fifth configuration example shown in FIG. 10 are used, the power supply is as low as about “2 × Vth”. It is possible to operate the circuit at a high speed with a frequency of several hundred MHz while being a voltage.

  Further, if the differential amplifier circuit 106 of the sixth configuration example shown in FIG. 8 is used as the receivers RV0 to RVn, the circuit can be operated at a frequency of several hundred MHz with a low power supply voltage of about “3 × Vth”. Is possible.

FIG. 13 shows a configuration example of the PLL circuit U1 on the driver side in the LVDS circuit shown in FIG.
The PLL circuit U1 shown in FIG. 13 is N-divided by a voltage-controlled oscillation circuit 303 that outputs a clock signal CLK2 having a frequency corresponding to the control voltage Vcnt, an N-frequency divider 304 that divides the clock signal CLK2 by N. A phase comparator 301 that compares the phases of the clock signal CLK ′ and the supplied clock signal CLK, and a charge pump circuit 302 that charges or discharges the capacitor according to the comparison result of the phase comparator 301. Is generated as a control voltage Vcnt and input to the voltage controlled oscillation circuit 303.
Although not shown, the PLL circuit U2 on the receiver side can also be realized with the same configuration as in FIG.

  An LVDS driver or LVDS receiver often incorporates a PLL circuit or a DLL circuit, and is required to operate with a low power supply voltage similar to that of the driver. For example, as shown in FIG. 13, the PLL circuit includes a voltage controlled oscillation circuit, an N frequency divider, a phase comparator, and a charge pump circuit. The N divider is driven by the clock output of the voltage controlled oscillation circuit, and must transiently operate to a frequency about twice as high as the frequency Φ × n.

FIG. 14 is a diagram illustrating an example of the configuration of the voltage controlled oscillation circuit 303.
As shown in FIG. 14, for example, the voltage controlled oscillation circuit 303 includes delay stages 403, 404,..., 408 connected in a ring shape for delaying and outputting differential signals. The value of the current flowing through the current source changes according to the control voltage Vcnt supplied to the current source of each delay stage, and the operating speed of the delay stage changes accordingly, whereby the oscillation frequency is controlled. When the differential input transistor and the current source transistor of each delay stage are composed of NMOS transistors, the differential output of each delay stage oscillates on the VDD side. Further, when the differential input transistor and the current source transistor of each delay stage are composed of PMOS transistors, the differential output of each delay stage oscillates on the GND side. That is, the output signal of the delay stage is not a signal that performs full swing in the power supply voltage range. Therefore, if this output signal is directly received by the inverter and converted to a full swing signal, the power supply voltage dependency or process dependency of the logic threshold voltage of the inverter is low at a low power supply voltage of about 2 × Vth. Due to the influence, the delay time at the rise and the delay time at the fall vary, and the duty of the clock signal greatly deviates from an optimum value (for example, 50%). With such a clock signal, it is difficult to stably operate the circuit at a high frequency.

  Therefore, in the voltage controlled oscillation circuit 303 shown in FIG. 14, as the differential amplifier circuits 401 and 402 for extracting complementary output signals of the respective delay stages, the differential amplifier circuits (first to fifth configuration examples) described above ( 101-105). This allows the delay stage to oscillate without sacrificing the speed of several hundred MHz while maintaining the same delay time at the rise and the delay time at the fall while maintaining a low power supply voltage of about '2 × Vth'. It is possible to convert the signal to a full swing signal.

  Further, if the differential amplifier circuit 6 of the sixth configuration example is used as the differential amplifier circuits 401 and 402, the delay time at the rise time and the delay time at the fall time are reduced at a low power supply voltage of about '3 × Vth'. While maintaining the same, it is possible to convert the oscillation signal of the delay stage into a full swing signal without impairing the speed of several hundred MHz.

FIG. 15 is a diagram illustrating an example of the configuration of drivers DV0 to DVn used in the LVDS driver 202.
The driver DVi (i represents an integer from 0 to n) includes a differential amplifier circuit 501, inverters 502 and 503, and an output circuit 504, for example, as shown in FIG.
The differential amplifier circuit 501 converts the single-format serial data SDi output from the parallel / serial conversion circuit 201 into a differential signal, and changes the signal level from a level suitable for the digital power supply voltage VDD1 to an analog signal. Conversion to a level suitable for the power supply voltage VDD2 (> VDD2). The differential amplifier circuit 501 amplifies the difference between the serial data SDi and the reference voltage Vref, and outputs the amplification result as a differential signal.
The output circuit 504 generates a differential current according to the differential signal input from the differential amplifier circuit 501 via the inverters 502 and 503, and outputs this to a pair of signal lines.

  If the differential amplifier circuit according to this embodiment described above is used as the differential amplifier circuit 501, the delay time at the time of rising and the delay time at the time of falling can be kept the same, so that the circuit operates at a high frequency of several hundred MHz. It is possible to make it.

  As mentioned above, although embodiment of this invention was described, this invention is not limited only to said form, Various modifications are included.

  In the example of FIG. 1, the bias voltage supplied to the N-channel side load transistors (MN21, MN22, MN21b, MN22b) is supplied from the nodes N31 and N32b. , MP22, MP21b, MP22b) may be supplied from the nodes N31 and N32b.

In the example of FIG. 5, the bias voltage supplied to the N-channel side load transistors (MN21, MN22, MN22b) is supplied from the nodes N31 and N32b, but conversely, the P-channel side load transistors (MP21, MP22). , MP22b) may be supplied from nodes N31 and N32b.
In the example of FIG. 5, the amplification unit PSAMP2 is configured by deleting the cascode circuit 21b from the amplification unit AMP2. However, the amplification unit PSAMP2 may be configured by deleting the cascode circuit 22b from the amplification unit AMP2. good. In this case, a bias voltage is generated by connecting and competing the non-inverted output (N32) of the amplifying unit AMP1 and the inverted output (N31b) of the amplifying unit PSAMP2, and the inverted output signal O (from the node N31 of the amplifying unit AMP1 is generated. -) May be output.

  In the example of FIG. 8, the inverting output (N31) of the amplifying unit AMP1 and the gates of the N-channel load transistors (MN21, MN22) are connected, and the non-inverting output (N32b) of the amplifying unit AMP3 and the load transistor on the P-channel side. (MP21b, MP22b) is connected to the gate, but conversely, the inverted output (N31) of the amplifier AMP1 and the gate of the load transistor (MP21, MP22) on the P channel side are connected and amplified. The non-inverting output (N32b) of the unit AMP3 and the gates of the N-channel side load transistors (MN21b, MN22b) may be connected.

In the example of FIG. 9, the inverting output (N31) of the amplifying unit AMP1 and the gates of the N-channel load transistors (MN21, MN22) are connected, and the non-inverting output (N32b) of the amplifying unit AMP3 and the P-channel side load transistor are connected. (MP22b) is connected to the gate, but conversely, the inverted output (N31) of the amplifier AMP1 and the gates of the load transistors (MP21, MP22) on the P channel side are connected to each other, and the amplifier AMP3 The non-inverted output (N32b) may be connected to the gate of the N-channel side load transistor (MN22b).
In the example of FIG. 5, the amplification unit PSAMP2 is configured by deleting the cascode circuit 21b from the amplification unit AMP2. However, the amplification unit PSAMP2 may be configured by deleting the cascode circuit 22b from the amplification unit AMP2. good. In this case, a bias voltage is generated by connecting and competing the non-inverted output (N32) of the amplifying unit AMP1 and the inverted output (N31b) of the amplifying unit PSAMP2, and the inverted output signal O (from the node N31 of the amplifying unit AMP1 is generated. -) May be output.

  In the example of FIG. 10, the bias voltage supplied to the N-channel side load transistors (MN21, MN22, MN21b, MN22b) is supplied from the nodes N31 and N32b. A bias voltage supplied to (MP21, MP22, MP21b, MP22b) may be supplied from the nodes N31 and N32b.

  FIG. 14 shows an example in which the differential amplifier circuit according to the present embodiment is applied to the voltage controlled oscillation circuit 303. However, the differential amplifier circuit according to the present embodiment can be similarly applied to a voltage controlled delay circuit. . In addition, the differential amplifier circuit according to the present embodiment can be applied to a PLL circuit as shown in FIGS. 13 and 14, and can be applied to a DLL circuit as well.

It is a figure which shows the 1st structural example of the differential amplifier circuit which concerns on embodiment of this invention. It is a 1st figure for demonstrating the classification | category of the supply method of the bias voltage in a differential amplifier circuit. It is a 2nd figure for demonstrating the classification | category of the supply method of the bias voltage in a differential amplifier circuit. It is a 3rd figure for demonstrating the classification | category of the supply method of the bias voltage in a differential amplifier circuit. It is a figure which shows the 2nd structural example of the differential amplifier circuit which concerns on embodiment of this invention. FIG. 17 is a diagram showing an example of simulation results of voltage waveforms in the differential amplifier circuit of the second configuration example shown in FIG. 5 and the self-bias type differential amplifier circuit shown in FIG. 16. FIG. 17 is a diagram showing an example of simulation results of current waveforms in the differential amplifier circuit of the second configuration example shown in FIG. 5 and the self-bias type differential amplifier circuit shown in FIG. 16. It is a figure which shows the 3rd structural example of the differential amplifier circuit which concerns on embodiment of this invention. It is a figure which shows the 4th structural example of the differential amplifier circuit which concerns on embodiment of this invention. It is a figure which shows the 5th structural example of the differential amplifier circuit which concerns on embodiment of this invention. It is a figure which shows the 6th structural example of the differential amplifier circuit which concerns on embodiment of this invention. It is a figure which shows an example of the LVDS circuit which applied the differential amplifier circuit which concerns on embodiment of this invention. 13 shows an example of the configuration of a PLL circuit in the LVDS circuit shown in FIG. It is a figure which shows an example of a structure of the voltage controlled oscillation circuit in the LVDS circuit shown in FIG. It is a figure which shows an example of a structure of the driver circuit used for an LVDS driver. It is a figure which shows the 1st example of a general folded cascode type | mold differential amplifier circuit. It is a figure which shows the 2nd example of a general folded cascode type | mold differential amplifier circuit. It is a figure which shows an example of a self-bias type differential amplifier circuit. It is a figure which shows an example of the simulation result of each signal waveform in the self-bias type differential amplifier circuit shown in FIG.18 and FIG.21. It is the figure which expanded and displayed a part of simulation result shown in FIG. It is a figure which shows the other example of a folded cascode type | mold differential amplifier circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11, 12, 11b, 12b ... Differential current generation part 21, 22, 21b, 22b ... Cascode part, 101-106, 401, 402, 501 ... Differential amplification circuit, 201 ... Parallel / serial conversion circuit, 202 ... LVDS driver, 203 ... serial / parallel conversion circuit, 204 ... LVDS receiver, 301 ... phase comparator, 302 ... charge pump circuit, 303 ... voltage controlled oscillation circuit, 304 ... frequency divider, 403 to 408 ... delay stage, 504 ... Output circuit, MN11, MN12, MSN1, MN21 to MN24, MN11b, MN12b, MSN1b, MN21b to MN24b ... NMOS transistor, MP11, MP12, MSP1, MP21 to MP24, MP11b, MP12b, MSP1b, MP21b to MP24b ... PMOS transistor, ISP , ISN1, ISP1b, ISN1b ... constant current source, AMP1~AMP6, PSAMP2~PSAMP4 ... amplification unit, DV0~DVn ... driver circuit, RV0~RVn ... receiver circuit, RT0~RTn ... terminating resistor

Claims (17)

A first amplifying unit and a second amplifying unit for inputting a common differential signal;
Each of the first amplification unit and the second amplification unit is
A first differential current generator that generates a first differential current that flows in a direction of discharging from the first power supply line toward the second power supply line in response to the differential signal of the input;
A second differential current generator for generating a second differential current that flows in a direction of drawing from the first power supply line toward the second power supply line in response to the input differential signal;
A first cascode section for inputting one current of the first differential current and one current of the second differential current that are in a relationship in which one increases and the other decreases;
A second cascode section for inputting the other current of the first differential current and the other current of the second differential current that are in a relationship of decreasing when the other increases.
Each of the first cascode portion and the second cascode portion is
A first node for inputting one of the first differential currents;
A second node for inputting one of the second differential currents;
A third node;
A first transistor of a first conductivity type that controls the current flowing from the first node to the second power supply line to be constant;
A second transistor of a second conductivity type that controls the current flowing from the first power supply line to the second node to be constant;
A third transistor of the first conductivity type that controls an impedance between the first node and the third node so that the voltage of the first node is kept constant;
A second transistor of the second conductivity type that controls the impedance between the second node and the third node so that the voltage of the second node is kept constant;
The third node of the first cascode section or the second cascode section in the first amplification section and the third node of the first cascode section or the second cascode section in the second amplification section are connected in common. And
The two third nodes connected in common have a relationship in which when one is increased, the other voltage is decreased when one voltage is increased.
Either one of the first transistor and the second transistor included in the first amplification unit commonly increases or decreases the current according to the voltage of the third node connected in common,
Either one of the first transistor and the second transistor included in the second amplifying unit commonly increases or decreases the current according to the voltage of the third node connected in common,
The amplification result of the differential signal of the input is output from the other two third nodes that are not commonly connected in the first amplification unit and the second amplification unit.
Differential amplifier circuit. A first amplifying unit and a second amplifying unit for inputting a common differential signal;
Each of the first amplification unit and the second amplification unit is
A first differential current generator that generates a first differential current that flows in a direction of discharging from the first power supply line toward the second power supply line in response to the differential signal of the input;
A second differential current generator for generating a second differential current that flows in a direction of drawing from the first power supply line toward the second power supply line in response to the input differential signal;
The first amplification unit includes:
A first cascode section for inputting one current of the first differential current and one current of the second differential current that are in a relationship in which one increases and the other decreases;
A second cascode section for inputting the other current of the first differential current and the other current of the second differential current that are in a relationship of decreasing when the other increases.
The second amplification unit includes:
A third cascode section for inputting one current of the first differential current and one current of the second differential current that are in a relationship in which one increases and the other decreases;
Each of the first cascode part, the second cascode part, and the third cascode part is
A first node for inputting one of the first differential currents;
A second node for inputting one of the second differential currents;
A third node;
A first transistor of a first conductivity type that controls the current flowing from the first node to the second power supply line to be constant;
A second transistor of a second conductivity type that controls the current flowing from the first power supply line to the second node to be constant;
A third transistor of the first conductivity type that controls an impedance between the first node and the third node so that the voltage of the first node is kept constant;
A second transistor of the second conductivity type that controls the impedance between the second node and the third node so that the voltage of the second node is kept constant;
The third node of the first cascode part or the second cascode part and the third node of the third cascode part are connected in common,
The two third nodes connected in common have a relationship in which when one is increased, the other voltage is decreased when one voltage is increased.
Either one of the first transistor and the second transistor included in the first amplification unit commonly increases or decreases the current according to the voltage of the third node connected in common,
Either one of the first transistor and the second transistor included in the second amplifying unit commonly increases or decreases the current according to the voltage of the third node connected in common,
The amplification result of the differential signal of the input is output from the third node that is not connected in common.
Differential amplifier circuit. A first amplifying unit and a second amplifying unit for inputting a common differential signal;
Each of the first amplification unit and the second amplification unit is
A first differential current generator that generates a first differential current that flows in a direction of discharging from the first power supply line toward the second power supply line in response to the differential signal of the input;
A second differential current generator for generating a second differential current that flows in a direction of drawing from the first power supply line toward the second power supply line in response to the input differential signal;
A first cascode section for inputting one current of the first differential current and one current of the second differential current that are in a relationship in which one increases and the other decreases;
A second cascode section for inputting the other current of the first differential current and the other current of the second differential current that are in a relationship of decreasing when the other increases.
Each of the first cascode portion and the second cascode portion is
A first node for inputting one of the first differential currents;
A second node for inputting one of the second differential currents;
A third node;
A first transistor of a first conductivity type that controls the current flowing from the first node to the second power supply line to be constant;
A second transistor of a second conductivity type that controls the current flowing from the first power supply line to the second node to be constant;
A third transistor of the first conductivity type that controls an impedance between the first node and the third node so that the voltage of the first node is kept constant;
A second transistor of the second conductivity type that controls the impedance between the second node and the third node so that the voltage of the second node is kept constant;
A third node of the first cascode section and the second cascode section in the second amplification section is connected in common;
Either one of the first transistor and the second transistor in the second amplifying unit commonly increases or decreases the current according to the voltage of the third node connected in common,
Either one of the first transistor and the second transistor in the first amplifying unit commonly increases or decreases the current according to the voltage of the third node connected in common,
From the third node of the first cascode unit and the second cascode unit in the first amplification unit, the amplification result of the differential signal of the input is output.
Differential amplifier circuit. The first transistor, the second transistor, the third transistor, and the fourth transistor are insulated gate transistors,
The first differential current generator is
A pair of insulated gate first transistors having the second conductivity type, each source being connected in common and outputting the first differential current from each drain;
An insulated gate type fifth transistor connected between the source of the first transistor pair and the first power supply line and having the second conductivity type;
The second differential current generator is
An insulated gate type second transistor pair having the first conductivity type, each source being connected in common and outputting the second differential current from each drain;
An insulated gate type sixth transistor having the first conductivity type connected between the source of the second transistor pair and the second power supply line;
The gates of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are connected to the commonly connected third node.
The differential amplifier circuit according to claim 1. The first transistor, the second transistor, the third transistor, and the fourth transistor are insulated gate transistors,
In the first differential current generator, the sources are commonly connected, a constant current is input to the commonly connected sources, and the first differential current is output from each drain. A first pair of insulated gate transistors having a conductivity type;
In the second differential current generator, the sources are connected in common, a constant current is input to the commonly connected sources, and the second differential current is output from each drain. Including an insulated gate type second transistor pair having a conductivity type;
The differential amplifier circuit according to claim 1. A current-voltage conversion circuit that converts a differential current transmitted through a pair of signal lines into a differential voltage;
A differential amplifier circuit that amplifies the differential voltage output from the current-voltage converter circuit,
The differential amplifier circuit includes a first amplifier unit and a second amplifier unit that input the differential voltage together,
Each of the first amplification unit and the second amplification unit is
A first differential current generator that generates a first differential current that flows in a direction of discharging from the first power supply line toward the second power supply line according to the differential voltage of the input;
A second differential current generator for generating a second differential current that flows in a direction of drawing from the first power supply line toward the second power supply line in accordance with the input differential voltage;
A first cascode section for inputting one current of the first differential current and one current of the second differential current that are in a relationship in which one increases and the other decreases;
A second cascode section for inputting the other current of the first differential current and the other current of the second differential current that are in a relationship of decreasing when the other increases.
Each of the first cascode portion and the second cascode portion is
A first node for inputting one of the first differential currents;
A second node for inputting one of the second differential currents;
A third node;
A first transistor of a first conductivity type that controls the current flowing from the first node to the second power supply line to be constant;
A second transistor of a second conductivity type that controls the current flowing from the first power supply line to the second node to be constant;
A third transistor of the first conductivity type that controls an impedance between the first node and the third node so that the voltage of the first node is kept constant;
A second transistor of the second conductivity type that controls the impedance between the second node and the third node so that the voltage of the second node is kept constant;
The third node of the first cascode section or the second cascode section in the first amplification section and the third node of the first cascode section or the second cascode section in the second amplification section are connected in common. And
The two third nodes connected in common have a relationship in which when one is increased, the other voltage is decreased when one voltage is increased.
Either one of the first transistor and the second transistor included in the first amplification unit commonly increases or decreases the current according to the voltage of the third node connected in common,
Either one of the first transistor and the second transistor included in the second amplifying unit commonly increases or decreases the current according to the voltage of the third node connected in common,
The amplification result of the differential voltage of the input is output from the other two third nodes that are not commonly connected in the first amplification unit and the second amplification unit.
Receiver circuit. A current-voltage conversion circuit that converts a differential current transmitted through a pair of signal lines into a differential voltage;
A differential amplifier circuit that amplifies the differential voltage output from the current-voltage converter circuit,
The differential amplifier circuit includes a first amplifier unit and a second amplifier unit that input the differential voltage together,
Each of the first amplification unit and the second amplification unit is
A first differential current generator that generates a first differential current that flows in a direction of discharging from the first power supply line toward the second power supply line according to the differential voltage of the input;
A second differential current generating unit that generates a second differential current that flows in a direction of drawing from the first power supply line toward the second power supply line in accordance with the differential voltage of the input;
The first amplification unit includes:
A first cascode section for inputting one current of the first differential current and one current of the second differential current that are in a relationship in which one increases and the other decreases;
A second cascode section for inputting the other current of the first differential current and the other current of the second differential current that are in a relationship of decreasing when the other increases.
The second amplification unit includes:
A third cascode section for inputting one current of the first differential current and one current of the second differential current that are in a relationship in which one increases and the other decreases;
Each of the first cascode part, the second cascode part, and the third cascode part is
A first node for inputting one of the first differential currents;
A second node for inputting one of the second differential currents;
A third node;
A first transistor of a first conductivity type that controls the current flowing from the first node to the second power supply line to be constant;
A second transistor of a second conductivity type that controls the current flowing from the first power supply line to the second node to be constant;
A third transistor of the first conductivity type that controls an impedance between the first node and the third node so that the voltage of the first node is kept constant;
A second transistor of the second conductivity type that controls the impedance between the second node and the third node so that the voltage of the second node is kept constant;
The third node of the first cascode part or the second cascode part and the third node of the third cascode part are connected in common,
The two third nodes connected in common have a relationship in which when one is increased, the other voltage is decreased when one voltage is increased.
Either one of the first transistor and the second transistor included in the first amplification unit commonly increases or decreases the current according to the voltage of the third node connected in common,
Either one of the first transistor and the second transistor included in the second amplifying unit commonly increases or decreases the current according to the voltage of the third node connected in common,
The amplification result of the differential voltage of the input is output from the third node not connected in common.
Receiver circuit. A current-voltage conversion circuit that converts a differential current transmitted through a pair of signal lines into a differential voltage;
A differential amplifier circuit that amplifies the differential voltage output from the current-voltage converter circuit,
The differential amplifier circuit includes a first amplifier unit and a second amplifier unit that input the differential voltage together,
Each of the first amplification unit and the second amplification unit is
A first differential current generator that generates a first differential current that flows in a direction of discharging from the first power supply line toward the second power supply line according to the differential voltage of the input;
A second differential current generator for generating a second differential current that flows in a direction of drawing from the first power supply line toward the second power supply line in accordance with the input differential voltage;
A first cascode section for inputting one current of the first differential current and one current of the second differential current that are in a relationship in which one increases and the other decreases;
A second cascode section for inputting the other current of the first differential current and the other current of the second differential current that are in a relationship of decreasing when the other increases.
Each of the first cascode portion and the second cascode portion is
A first node for inputting one of the first differential currents;
A second node for inputting one of the second differential currents;
A third node;
A first transistor of a first conductivity type that controls the current flowing from the first node to the second power supply line to be constant;
A second transistor of a second conductivity type that controls the current flowing from the first power supply line to the second node to be constant;
A third transistor of the first conductivity type that controls an impedance between the first node and the third node so that the voltage of the first node is kept constant;
A second transistor of the second conductivity type that controls the impedance between the second node and the third node so that the voltage of the second node is kept constant;
A third node of the first cascode section and the second cascode section in the second amplification section is connected in common;
Either one of the first transistor and the second transistor in the second amplifying unit commonly increases or decreases the current according to the voltage of the third node connected in common,
Either one of the first transistor and the second transistor in the first amplifying unit commonly increases or decreases the current according to the voltage of the third node connected in common,
The amplification result of the differential voltage of the input is output from the third node of the first cascode unit and the second cascode unit in the first amplification unit.
Receiver circuit. The first transistor, the second transistor, the third transistor, and the fourth transistor are insulated gate transistors,
The first differential current generator is
A pair of insulated gate first transistors having the second conductivity type, each source being connected in common and outputting the first differential current from each drain;
An insulated gate type fifth transistor connected between the source of the first transistor pair and the first power supply line and having the second conductivity type;
The second differential current generator is
An insulated gate type second transistor pair having the first conductivity type, each source being connected in common and outputting the second differential current from each drain;
An insulated gate type sixth transistor having the first conductivity type connected between the source of the second transistor pair and the second power supply line;
The gates of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are connected to the commonly connected third node.
The receiver circuit according to claim 6. An oscillating unit having a plurality of ring-shaped delay stages for outputting an input differential signal with a delay, and
At least one differential amplifier circuit for amplifying a differential signal output from at least one of the plurality of delay stages;
Each of the plurality of delay stages changes in delay according to an input control signal,
The differential amplifier circuit is
A first amplifying unit and a second amplifying unit for commonly inputting a differential signal from the delay stage;
Each of the first amplification unit and the second amplification unit is
A first differential current generator that generates a first differential current that flows in a direction of discharging from the first power supply line toward the second power supply line in response to the differential signal of the input;
A second differential current generator for generating a second differential current that flows in a direction of drawing from the first power supply line toward the second power supply line in response to the input differential signal;
A first cascode section for inputting one current of the first differential current and one current of the second differential current that are in a relationship in which one increases and the other decreases;
A second cascode section for inputting the other current of the first differential current and the other current of the second differential current that are in a relationship of decreasing when the other increases.
Each of the first cascode portion and the second cascode portion is
A first node for inputting one of the first differential currents;
A second node for inputting one of the second differential currents;
A third node;
A first transistor of a first conductivity type that controls the current flowing from the first node to the second power supply line to be constant;
A second transistor of a second conductivity type that controls the current flowing from the first power supply line to the second node to be constant;
A third transistor of the first conductivity type that controls an impedance between the first node and the third node so that the voltage of the first node is kept constant;
A second transistor of the second conductivity type that controls the impedance between the second node and the third node so that the voltage of the second node is kept constant;
The third node of the first cascode section or the second cascode section in the first amplification section and the third node of the first cascode section or the second cascode section in the second amplification section are connected in common. And
The two third nodes connected in common have a relationship in which when one is increased, the other voltage is decreased when one voltage is increased.
Either one of the first transistor and the second transistor included in the first amplification unit commonly increases or decreases the current according to the voltage of the third node connected in common,
Either one of the first transistor and the second transistor included in the second amplifying unit commonly increases or decreases the current according to the voltage of the third node connected in common,
The amplification result of the differential signal of the input is output from the other two third nodes that are not commonly connected in the first amplification unit and the second amplification unit.
Oscillator circuit. An oscillating unit having a plurality of ring-shaped delay stages for outputting an input differential signal with a delay, and
At least one differential amplifier circuit for amplifying a differential signal output from at least one of the plurality of delay stages;
Each of the plurality of delay stages changes in delay according to an input control signal,
The differential amplifier circuit is
A first amplifying unit and a second amplifying unit for commonly inputting a differential signal from the delay stage;
Each of the first amplification unit and the second amplification unit is
A first differential current generator that generates a first differential current that flows in a direction of discharging from the first power supply line toward the second power supply line in response to the differential signal of the input;
A second differential current generator for generating a second differential current that flows in a direction of drawing from the first power supply line toward the second power supply line in response to the input differential signal;
The first amplification unit includes:
A first cascode section for inputting one current of the first differential current and one current of the second differential current that are in a relationship in which one increases and the other decreases;
A second cascode section for inputting the other current of the first differential current and the other current of the second differential current that are in a relationship of decreasing when the other increases.
The second amplification unit includes:
A third cascode section for inputting one current of the first differential current and one current of the second differential current that are in a relationship in which one increases and the other decreases;
Each of the first cascode part, the second cascode part, and the third cascode part is
A first node for inputting one of the first differential currents;
A second node for inputting one of the second differential currents;
A third node;
A first transistor of a first conductivity type that controls the current flowing from the first node to the second power supply line to be constant;
A second transistor of a second conductivity type that controls the current flowing from the first power supply line to the second node to be constant;
A third transistor of the first conductivity type that controls an impedance between the first node and the third node so that the voltage of the first node is kept constant;
A second transistor of the second conductivity type that controls the impedance between the second node and the third node so that the voltage of the second node is kept constant;
The third node of the first cascode part or the second cascode part and the third node of the third cascode part are connected in common,
The two third nodes connected in common have a relationship in which when one is increased, the other voltage is decreased when one voltage is increased.
Either one of the first transistor and the second transistor included in the first amplification unit commonly increases or decreases the current according to the voltage of the third node connected in common,
Either one of the first transistor and the second transistor included in the second amplifying unit commonly increases or decreases the current according to the voltage of the third node connected in common,
The amplification result of the differential signal of the input is output from the third node that is not connected in common.
Oscillator circuit. An oscillating unit having a plurality of ring-shaped delay stages for outputting an input differential signal with a delay, and
At least one differential amplifier circuit for amplifying a differential signal output from at least one of the plurality of delay stages;
Each of the plurality of delay stages changes in delay according to an input control signal,
The differential amplifier circuit is
A first amplifying unit and a second amplifying unit for commonly inputting a differential signal from the delay stage;
Each of the first amplification unit and the second amplification unit is
A first differential current generator that generates a first differential current that flows in a direction of discharging from the first power supply line toward the second power supply line in response to the differential signal of the input;
A second differential current generator for generating a second differential current that flows in a direction of drawing from the first power supply line toward the second power supply line in response to the input differential signal;
A first cascode section for inputting one current of the first differential current and one current of the second differential current that are in a relationship in which one increases and the other decreases;
A second cascode section for inputting the other current of the first differential current and the other current of the second differential current that are in a relationship of decreasing when the other increases.
Each of the first cascode portion and the second cascode portion is
A first node for inputting one of the first differential currents;
A second node for inputting one of the second differential currents;
A third node;
A first transistor of a first conductivity type that controls the current flowing from the first node to the second power supply line to be constant;
A second transistor of a second conductivity type that controls the current flowing from the first power supply line to the second node to be constant;
A third transistor of the first conductivity type that controls an impedance between the first node and the third node so that the voltage of the first node is kept constant;
A second transistor of the second conductivity type that controls the impedance between the second node and the third node so that the voltage of the second node is kept constant;
A third node of the first cascode section and the second cascode section in the second amplification section is connected in common;
Either one of the first transistor and the second transistor in the second amplifying unit commonly increases or decreases the current according to the voltage of the third node connected in common,
Either one of the first transistor and the second transistor in the first amplifying unit commonly increases or decreases the current according to the voltage of the third node connected in common,
From the third node of the first cascode unit and the second cascode unit in the first amplification unit, the amplification result of the differential signal of the input is output.
Oscillator circuit. The first transistor, the second transistor, the third transistor, and the fourth transistor are insulated gate transistors,
The first differential current generator is
A pair of insulated gate first transistors having the second conductivity type, each source being connected in common and outputting the first differential current from each drain;
An insulated gate type fifth transistor connected between the source of the first transistor pair and the first power supply line and having the second conductivity type;
The second differential current generator is
An insulated gate type second transistor pair having the first conductivity type, each source being connected in common and outputting the second differential current from each drain;
An insulated gate type sixth transistor having the first conductivity type connected between the source of the second transistor pair and the second power supply line;
The gates of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are connected to the commonly connected third node.
The oscillation circuit according to claim 10. A differential amplifier circuit that inputs and amplifies the difference between the input signal and the reference signal as a differential signal;
An output circuit that outputs a differential current corresponding to the amplification result of the differential amplifier circuit to a pair of signal lines;
The differential amplifier circuit includes a first amplifying unit and a second amplifying unit for inputting the differential signals together,
Each of the first amplification unit and the second amplification unit is
A first differential current generator that generates a first differential current that flows in a direction of discharging from the first power supply line toward the second power supply line in response to the differential signal of the input;
A second differential current generator for generating a second differential current that flows in a direction of drawing from the first power supply line toward the second power supply line in response to the input differential signal;
A first cascode section for inputting one current of the first differential current and one current of the second differential current that are in a relationship in which one increases and the other decreases;
A second cascode section for inputting the other current of the first differential current and the other current of the second differential current that are in a relationship of decreasing when the other increases.
Each of the first cascode portion and the second cascode portion is
A first node for inputting one of the first differential currents;
A second node for inputting one of the second differential currents;
A third node;
A first transistor of a first conductivity type that controls the current flowing from the first node to the second power supply line to be constant;
A second transistor of a second conductivity type that controls the current flowing from the first power supply line to the second node to be constant;
A third transistor of the first conductivity type that controls an impedance between the first node and the third node so that the voltage of the first node is kept constant;
A second transistor of the second conductivity type that controls the impedance between the second node and the third node so that the voltage of the second node is kept constant;
The third node of the first cascode section or the second cascode section in the first amplification section and the third node of the first cascode section or the second cascode section in the second amplification section are connected in common. And
The two third nodes connected in common have a relationship in which when one is increased, the other voltage is decreased when one voltage is increased.
Either one of the first transistor and the second transistor included in the first amplification unit commonly increases or decreases the current according to the voltage of the third node connected in common,
Either one of the first transistor and the second transistor included in the second amplifying unit commonly increases or decreases the current according to the voltage of the third node connected in common,
The amplification result of the differential signal of the input is output from the other two third nodes that are not commonly connected in the first amplification unit and the second amplification unit.
Driver circuit. A differential amplifier circuit that inputs and amplifies the difference between the input signal and the reference signal as a differential signal;
An output circuit that outputs a differential current corresponding to the amplification result of the differential amplifier circuit to a pair of signal lines;
The differential amplifier circuit includes a first amplifying unit and a second amplifying unit for inputting the differential signals together,
Each of the first amplification unit and the second amplification unit is
A first differential current generator that generates a first differential current that flows in a direction of discharging from the first power supply line toward the second power supply line in response to the differential signal of the input;
A second differential current generator for generating a second differential current that flows in a direction of drawing from the first power supply line toward the second power supply line in response to the input differential signal;
The first amplification unit includes:
A first cascode section for inputting one current of the first differential current and one current of the second differential current that are in a relationship in which one increases and the other decreases;
A second cascode section for inputting the other current of the first differential current and the other current of the second differential current that are in a relationship of decreasing when the other increases.
The second amplification unit includes:
A third cascode section for inputting one current of the first differential current and one current of the second differential current that are in a relationship in which one increases and the other decreases;
Each of the first cascode part, the second cascode part, and the third cascode part is
A first node for inputting one of the first differential currents;
A second node for inputting one of the second differential currents;
A third node;
A first transistor of a first conductivity type that controls the current flowing from the first node to the second power supply line to be constant;
A second transistor of a second conductivity type that controls the current flowing from the first power supply line to the second node to be constant;
A third transistor of the first conductivity type that controls an impedance between the first node and the third node so that the voltage of the first node is kept constant;
A second transistor of the second conductivity type that controls the impedance between the second node and the third node so that the voltage of the second node is kept constant;
The third node of the first cascode part or the second cascode part and the third node of the third cascode part are connected in common,
The two third nodes connected in common have a relationship in which when one is increased, the other voltage is decreased when one voltage is increased.
Either one of the first transistor and the second transistor included in the first amplification unit commonly increases or decreases the current according to the voltage of the third node connected in common,
Either one of the first transistor and the second transistor included in the second amplifying unit commonly increases or decreases the current according to the voltage of the third node connected in common,
The amplification result of the differential signal of the input is output from the third node that is not connected in common.
Driver circuit. A differential amplifier circuit that inputs and amplifies the difference between the input signal and the reference signal as a differential signal;
An output circuit that outputs a differential current corresponding to the amplification result of the differential amplifier circuit to a pair of signal lines;
The differential amplifier circuit includes a first amplifying unit and a second amplifying unit for inputting the differential signals together,
Each of the first amplification unit and the second amplification unit is
A first differential current generator that generates a first differential current that flows in a direction of discharging from the first power supply line toward the second power supply line in response to the differential signal of the input;
A second differential current generator for generating a second differential current that flows in a direction of drawing from the first power supply line toward the second power supply line in response to the input differential signal;
A first cascode section for inputting one current of the first differential current and one current of the second differential current that are in a relationship in which one increases and the other decreases;
A second cascode section for inputting the other current of the first differential current and the other current of the second differential current that are in a relationship of decreasing when the other increases.
Each of the first cascode portion and the second cascode portion is
A first node for inputting one of the first differential currents;
A second node for inputting one of the second differential currents;
A third node;
A first transistor of a first conductivity type that controls the current flowing from the first node to the second power supply line to be constant;
A second transistor of a second conductivity type that controls the current flowing from the first power supply line to the second node to be constant;
A third transistor of the first conductivity type that controls an impedance between the first node and the third node so that the voltage of the first node is kept constant;
A second transistor of the second conductivity type that controls the impedance between the second node and the third node so that the voltage of the second node is kept constant;
A third node of the first cascode section and the second cascode section in the second amplification section is connected in common;
Either one of the first transistor and the second transistor in the second amplifying unit commonly increases or decreases the current according to the voltage of the third node connected in common,
Either one of the first transistor and the second transistor in the first amplifying unit commonly increases or decreases the current according to the voltage of the third node connected in common,
From the third node of the first cascode unit and the second cascode unit in the first amplification unit, the amplification result of the differential signal of the input is output.
Driver circuit. The first transistor, the second transistor, the third transistor, and the fourth transistor are insulated gate transistors,
The first differential current generator is
A pair of insulated gate first transistors having the second conductivity type, each source being connected in common and outputting the first differential current from each drain;
An insulated gate type fifth transistor connected between the source of the first transistor pair and the first power supply line and having the second conductivity type;
The second differential current generator is
An insulated gate type second transistor pair having the first conductivity type, each source being connected in common and outputting the second differential current from each drain;
An insulated gate type sixth transistor having the first conductivity type connected between the source of the second transistor pair and the second power supply line;
The gates of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are connected to the commonly connected third node.
The driver circuit according to claim 14.

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