JP2007072550A - Memory card - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory card which can be reduced in manufacturing cost while reducing influence of adhesiveness and bonding nature on mounting of a semiconductor memory chip. <P>SOLUTION: This memory card is equipped with: a power supply terminal 1; a board 3 on which a ground terminal 2 is formed; a NAND memory chip 6 connected electrically to the power supply terminal 1 and the ground terminal 2 while being connected with a pad 4 set up on this board by wire bonding; and a wiring capacitor 7 formed on the board 3 so as to be connected with a NAND memory chip 6 in parallel between the power supply terminal 1 and the ground terminal 2 for supplying power to the NAND memory chip 6. The wiring capacitor 7 has a power supply side wiring 10 formed on the board 3, a ground side wiring 11, and a solder resist 12 set up between the power supply side wiring 10 and the ground side wiring 11. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory card having a semiconductor memory chip for storing information.

  In recent years, memory cards equipped with semiconductor memory chips have been widely used as data storage media for digital devices such as digital video cameras, mobile phones, and portable music players.

  A conventional memory card includes a NAND memory chip and a chip capacitor on a substrate, and a power / ground terminal of the memory card is connected to a power (Vcc) and a ground (GND) of the NAND memory, and a chip capacitor is parallel to this. It is connected. The chip capacitor prevents a memory card from malfunctioning by reducing voltage fluctuation due to power source noise or the like by charging and discharging the capacitor.

  For mounting the chip capacitor, solder paste printing is performed, the chip capacitor is mounted on the substrate and the solder paste is melted by a reflow device, and the Cu surface of the foot pattern of the substrate and the electrode of the chip capacitor are formed and connected. Is implemented.

  For NAND memory cards, there is a strong demand for product cost reduction, and in order to reduce the cost of parts used, NAND memories and controllers are manufactured in a single chip state rather than a package assembly. The connection between the NAND and the controller and the substrate wiring is not the solder connection by the package external terminal but the bonding pad of the chip and the substrate wiring by wire bonding using a gold wire or the like.

  However, in the above-described prior art, in the case of mounting the bare memory chip of the NAND memory and the controller described above, the board is warped by the thermal effect of reflow when the chip capacitor is mounted, which causes the board to be mounted by mounting the NAND memory and the controller chip. Since it is warped, there is a problem that the adhesion of the mount is lowered and the bonding property is further affected.

  Further, as a technique for forming a capacitor on a substrate in order to reduce manufacturing costs, there is an IC card including a resonance circuit that communicates with an IC card reader by electromagnetic induction or radio waves. The resonant circuit of this IC card is an LC resonant circuit with a combination of inductance and capacitance. (For example, refer to Patent Document 1).

However, in the above prior art, the resonance circuit that constitutes the capacitor for communication with the IC card has an antenna effect and does not supply power, so it can be simply applied to the power supply capacitor of the memory card. The manufacturing cost of the memory card could not be reduced.
Japanese Patent Laid-Open No. 11-167612 (page 3-5, FIG. 1)

  The present invention solves the above-mentioned problems, and prevents the warp of the substrate of the memory card in the mounting process of the semiconductor memory chip, which is inexpensive to manufacture, and adversely affects the adhesion and bonding properties of the semiconductor memory chip mount. An object of the present invention is to provide a memory card that can reduce the manufacturing cost while reducing the cost.

A memory card according to the present invention includes a substrate on which a first terminal to which a first voltage is applied, a second terminal to which a second voltage is applied, and
A semiconductor memory chip connected to the pads provided on the substrate by wire bonding and electrically connected to the first terminal and the second terminal;
A wiring capacitor formed on the substrate so as to be connected in parallel with the semiconductor memory chip between the first terminal and the second terminal, and for supplying power to the semiconductor memory chip; Prepared,
The wiring capacitor includes a first wiring formed on the substrate and connected to the first terminal, a second wiring formed on the substrate and connected to the second terminal, and the first wiring And an insulator provided between the second wiring and the second wiring.

  According to the memory card of one embodiment of the present invention, it is possible to reduce the manufacturing cost while reducing the influence on the mount adhesion and bonding property of the semiconductor memory chip.

  In the present invention, for example, a semiconductor memory chip whose manufacturing cost is low is adopted, and a wiring capacitor is formed on the substrate in advance to prevent warping of the substrate of the memory card in the mounting process of the semiconductor memory chip. This is to reduce the manufacturing cost of the memory card while reducing the influence on the adhesion and bonding properties of the memory chip mount.

  In the following embodiments, the power supply voltage (Vcc) is the first voltage, the power supply terminal is the first terminal, the ground voltage (GND) is the second voltage, and the ground terminal is the second terminal. However, the first voltage may be the ground voltage (GND), the first terminal may be the ground terminal, the second voltage may be the power supply voltage (Vcc), and the second terminal may be the power supply terminal.

  Embodiments to which the present invention is applied will be described below with reference to the drawings.

  FIG. 1 is a plan view showing a configuration of a main part of a memory card according to Embodiment 1 of the present invention. 2 and 3 are plan views showing an example of the configuration of the main part of the wiring capacitor according to the first embodiment of the present invention.

  As shown in FIG. 1, the memory card 100 includes a first terminal (power supply terminal) 1 to which a first voltage (power supply voltage Vcc) is applied, and a second voltage (ground voltage GND) to which a second voltage (ground voltage GND) is applied. The substrate 3 on which the terminal (ground terminal) 2 is formed and the pad 4 provided on the substrate 3 are connected to the power supply terminal 1 and the ground terminal 2 while being connected to the pad 4 by wire bonding. Formed on the substrate 3 so as to be connected in parallel with the NAND memory chip 6 between the power supply terminal 1 and the ground terminal 2. The wiring capacitor 7 to be supplied is connected to the pad 4 on the substrate 1 by the bonding wire 5 by wire bonding, and the wiring capacitor 7 Luo power source is connected in parallel with the wiring capacitor 7 between the power supply terminal 1 and ground terminal 2 to be supplied, and a controller chip 8 for controlling the NAND memory chip 6.

  The power supply terminal 1 and the ground terminal 2 are connected to a wiring made of a conductor such as copper connected to the pad 4 and other elements, and the surface thereof is plated with two layers of nickel and gold. When the memory card 100 is connected to a connector portion of an external device (not shown), predetermined power is supplied to the NAND memory chip 6, the wiring capacitor 7, and the controller chip 8 through the power supply terminal 1 and the ground terminal 2. Is done.

  The substrate 3 is made of an insulating prepreg (glass epoxy resin), and a solder resist that is an insulator is formed on the surface thereof. It should be noted that the solder resist is removed from the portion where the element such as the pad 4 is connected.

  The wiring on the element mounting side such as the NAND memory chip 6 of the substrate 3 is connected to the wiring on the opposite side by a through hole (not shown) penetrating the substrate 3.

  The wiring capacitor 7 is charged / discharged when the voltage fluctuates due to noise of the power supply and the desired power supply from the power supply terminal 1 and the ground terminal 2 is not performed, and the wiring capacitor 7 is supplied to the NAND memory chip 6 and the controller chip 8. The stable power supply is maintained and malfunction of the memory card 100 is prevented.

  Here, as shown in FIG. 2, the wiring capacitor 7 is formed on the substrate 3 and connected to the power supply terminal 1. The power supply side wiring 10 is connected to the power supply terminal 1, and the ground capacitor 2 is formed on the substrate 3. It has a ground-side wiring 11 that is the second wiring connected, and a solder resist 12 that is an insulator provided between the power-side wiring 10 and the ground-side wiring 11. As described above, the wiring capacitor 7 has a function as a capacitor by using the electric capacitance generated between the opposing power supply side wiring 10 and the ground side wiring 11. Further, the power supply side wiring 10 and the ground side wiring 11 are formed in a comb-teeth shape so that a larger capacity can be obtained with a small wiring area.

  In addition, as shown in FIG. 3, the wiring capacitor may be formed into a pattern like the wiring capacitor 7a by forming two patterns of the wiring capacitor 7 of FIG. 2 as one block pattern. As a result, the wiring area of the wiring capacitor 7 can be increased without increasing the wiring length of the power supply side wiring 10 and the ground side wiring 11, so that the capacitance of the wiring capacitor can be reduced while suppressing the antenna effect that can affect the power supply. Can be increased.

  Here, FIG. 4 is a cross-sectional view of the main part of the memory card 100 along the line AA in which the wiring capacitor of FIG. 2 is formed only on one side of the substrate.

  As shown in FIG. 4, the power supply side wiring 10 and the ground side wiring 11 are alternately formed on the substrate 3 via the solder resist 12. In addition, a signal wiring 9 for transmitting a predetermined signal is formed on the opposite side of the substrate 3.

  On the other hand, FIG. 5 is a cross-sectional view of the main part of the memory card 100 taken along line AA when the wiring capacitor of FIG. 2 is formed on both surfaces of the substrate.

  As shown in FIG. 5, a ground-side wiring 11 is formed on the opposite side of the substrate 3 on which the power-side wiring 10 is formed. As a result, a capacitor is formed by the power supply side wiring 10 on the upper surface side and the ground side wiring 11 on the lower surface side of the insulating substrate 3, and the capacitance of the wiring capacitor 7a is further increased. The signal wiring 9 shown in FIG. 4 is not shown in FIG. 5 because it is formed in another region of the substrate 3.

  6 is an external view showing a state in which the cover case of the memory card of FIG. 1 is mounted. As shown in FIG. 6, in the memory card 100, after the NAND memory chip 6, the wiring capacitor 7 and the controller chip 8 are mounted on the substrate 3, the cover case 13 is mounted.

  As described above, the NAND memory chip 6 and the controller chip 8 are connected to the pad 4 by wire bonding, and the wiring capacitor 7 for supplying power is formed on the substrate 3 together with other wirings. Therefore, it is not necessary to reflow in order to mount a capacitor for supplying electric power, and it is possible to prevent warping of the substrate 3 and to reduce the adhesion of the mount and the influence on the bonding property. Furthermore, since the wiring capacitor 7 is formed together with other wirings on the substrate 3, it is not necessary to separately mount a chip capacitor, resulting in a reduction in manufacturing cost.

Here, the capacity of the wiring capacitor of the memory card as described above will be considered. Here, for the sake of simplicity, a parallel plate model is adopted as a model for examination. This model is defined by the area S where the conductor A and the conductor B are in contact and the distance L between the conductors, and the capacitance C of the wiring capacitor is C = S / L × ε × ε0. Here, ε is a relative dielectric constant between conductors, and ε0 is a dielectric constant in vacuum (8.854 × 10 ⁻¹² F / m).

  The area S corresponding to the model is a product of the thickness of each wiring and the length of the wiring. The distance L between the conductors is the distance between the power supply side wiring and the ground side wiring. The relative dielectric constant ε is a physical property value of the solder resist.

In the model in which the wiring capacitor is formed only on one side of the substrate, for example, the distance L between conductors is 25 μm, the wiring thickness is 25 μm, the wiring length is 10 mm, and the relative dielectric constant ε is 5. The capacitance C of the capacitor is obtained as follows. That is, the capacity C = 10 mm × 25 μm / 25 μm × 5 × 8.854 × 10 ⁻¹² F / m = 442.7 × 10 ⁻¹² F = 44.2 pF.

  On the other hand, in the case of a double-sided board wiring capacitor, if a pattern area equivalent to that on the front surface side is obtained, the capacitance on the back surface side is added, and the capacitance at the portion where the wiring on the front surface side and the wiring on the back surface side are further added. It will be.

  Next, the time when the voltage drop of the power supplied to the NAND memory can be suppressed by the capacitor will be exemplarily examined using the above model.

  Generally, the capacitor C is obtained by dividing the charge Q by the applied voltage V, and the charge Q is obtained by the product of the current I (constant here) and the time t during which the current I flows. It is done. That is, the relationship of capacitor C = Q ÷ V = (I × t) ÷ V is established. From this, for the time t, the relationship t = (C × V) ÷ I is derived.

  Here, it is assumed that the power supply voltage of the memory card fluctuates from 3v to 2.9v (0.1V drop), and the current I at the time of fluctuation is 10 mA. Further, 44.2 pF obtained by the above calculation is used as the capacitance C of the capacitor built in the card. In this case, the time t is obtained as follows. That is, time t = (C × V) ÷ I = (44.2 pF × 0.1 v) ÷ 10 mA = 4.42 nS.

  Therefore, in the case of this model, the voltage drop of the power supplied to the NAND memory can be suppressed for 4.42 nS.

  As described above, according to the memory card of this embodiment, the warp of the memory card substrate in the mounting process of the NAND memory chip and the controller chip can be prevented, and the adhesion and bonding of the NAND memory chip and the controller chip can be bonded. The manufacturing cost of the memory card can be reduced while reducing the influence on the performance.

  In the first embodiment, the configuration in which the wiring capacitor of the memory card is formed in a comb shape is described, but in this embodiment, the configuration in which the wiring capacitor of the memory card is formed in a spiral shape is described.

  FIG. 7 is a plan view showing an example of a wiring capacitor of a memory card according to Embodiment 2 of the present invention. FIG. 8 is a plan view showing another example of the wiring capacitor of the memory card according to the second embodiment of the present invention. In the figure, the same reference numerals as those in the first embodiment indicate the same configurations as those in the first embodiment.

  As shown in FIG. 7, the wiring capacitor 7b includes a power supply side wiring 10b formed in a spiral shape on the substrate and connected to the power supply terminal, a ground side wiring 11b formed on the substrate and connected to the ground terminal, And a solder resist 12 which is an insulator provided between the side wiring 10b and the ground side wiring 11b.

  In this way, the wiring capacitor 7b has a function as a capacitor by using the electric capacitance generated between the opposing power supply side wiring 10b and the ground side wiring 11b. Since the power supply side wiring 10b and the ground side wiring 11b are formed in a spiral shape, a larger capacity can be obtained with a smaller wiring area.

  In addition, as shown in FIG. 8, the wiring capacitor may be patterned as a wiring capacitor 7c by forming two wiring capacitors 7b in FIG. 7 as one block pattern. As a result, the wiring area of the wiring capacitor 7b can be increased without increasing the wiring length of the power supply side wiring 10b and the ground side wiring 11b, so that the capacitance of the wiring capacitor can be reduced while suppressing the antenna effect that can affect the power supply. Can be increased.

  As described above, according to the memory card of this embodiment, the warp of the memory card substrate in the mounting process of the NAND memory chip and the controller chip can be prevented, and the adhesion and bonding of the NAND memory chip and the controller chip can be bonded. The manufacturing cost of the memory card can be reduced while reducing the influence on the performance.

  In the foregoing first and second embodiments, the configuration in which the wiring capacitor of the memory card has only one end connected to the power supply terminal and the ground terminal has been described. However, in this embodiment, the antenna effect of the wiring capacitor is reduced. Therefore, a configuration in which the other end portion of the wiring capacitor is connected to the power supply terminal and the ground terminal will be described.

  FIG. 9 is a plan view showing an example of a wiring capacitor of a memory card according to Embodiment 3 of the present invention. FIG. 10 is a plan view showing another example of the wiring capacitor of the memory card according to the second embodiment of the present invention. In the figure, the same reference numerals as those in the first embodiment indicate the same configurations as those in the first and second embodiments.

  As shown in FIG. 9, the wiring capacitor 7d has the same wiring structure as the comb-shaped wiring capacitor 7a shown in FIG. 3, but the branching portion 14 and the other end portion 15b of the power supply side wiring 10 are The power supply terminal 1 is electrically connected to the opposite side of the substrate 3 and through-holes 16 formed in the substrate 3 through through-holes. That is, the power supply side wiring 10 is connected to the power supply terminal 1 at one end portion 15a of the power supply side wiring 10 from one end portion 15a to the other end portion 15b. It is what.

  Similarly, in the wiring capacitor 7d, the branching portion 17 and the other end portion 18b of the ground side wiring 11 are connected to the ground terminal 2 via a through hole formed in the substrate 3 at the opposite side of the substrate 3 and the through hole connecting portion 19. Being electrically. That is, the ground-side wiring 11 is connected to the ground terminal 2 at one end 18a of the ground-side wiring 11 at one end 18a to the other end 18b. It is what.

  Here, the frequency of noise input to the wiring capacitor is proportional to the length of the wiring of the wiring capacitor. Also, the high frequency noise input to the wiring capacitor due to the antenna effect is less than the low frequency noise.

  Therefore, by connecting to the power supply terminal or the ground terminal at two or more places as described above, the length of the portion of the wiring (power supply side wiring, ground side wiring) serving as an antenna is shortened, thereby reducing the low frequency in the wiring capacitor. Therefore, the NAND memory chip and the controller chip can stably supply power.

  Further, for example, a wiring structure similar to the spiral wiring capacitor 7c shown in FIG. 8 may be through-hole connected like the wiring capacitor 7e shown in FIG. 10 to reduce the antenna effect.

  In this embodiment, the case where the wiring capacitor is wired through the through hole has been described. However, the wiring capacitor, the power supply terminal, and the ground terminal may be wired in the same plane of the substrate.

  In the present embodiment, the case where the power supply side wiring and the ground side wiring are connected to the power supply terminal and the ground terminal at the other end, etc. has been described, but only one of the power supply side wiring or the ground side wiring is the other. You may make it connect with a power supply terminal and a ground terminal by an edge part.

  As described above, according to the memory card of the present embodiment, the influence of noise on the power supplied from the wiring capacitor can be reduced, and the power can be supplied stably by the NAND memory chip and the controller chip.

It is a top view which shows the structure of the principal part of the memory card based on Example 1 which is 1 aspect of this invention. It is a top view which shows an example of a structure of the principal part of the wiring capacitor which concerns on Example 1 which is 1 aspect of this invention. It is a top view which shows the other example of a structure of the principal part of the wiring capacitor which concerns on Example 1 which is 1 aspect of this invention. It is sectional drawing of the principal part of the memory card 100 along the AA line in which the wiring capacitor of FIG. 2 was formed only in the single side | surface side of a board | substrate. It is sectional drawing of the principal part along the AA of a memory card when the wiring capacitor of FIG. 2 is formed in both surfaces of a board | substrate. It is an external view which shows the state which mounted | wore with the cover case of the memory card of FIG. It is a top view which shows an example of the wiring capacitor of the memory card based on Example 2 which is 1 aspect of this invention. It is a top view which shows the other example of the wiring capacitor of the memory card based on Example 2 of this invention which is 1 aspect of this invention. It is a top view which shows an example of the wiring capacitor of the memory card based on Example 3 which is 1 aspect of this invention. It is a top view which shows the other example of the wiring capacitor of the memory card based on Example 3 which is 1 aspect of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Power supply terminal 2 Ground terminal 3 Board | substrate 4 Pad 5 Bonding wire 6 NAND memory chip 7, 7a, 7b, 7c, 7d, 7e Wiring capacitor 8 Controller chip 9 Signal wiring 10 Power supply side wiring 11 Ground side wiring 12 Solder resist 13 Cover case 14 Branch portion 15a One end portion 15b of the power supply side wiring 16 Other end portion 16 of the power supply side wiring 16 Through-hole connection portion 17 Branch portion 18a One end portion 18b of the ground side wiring 19 Other end portion of the ground side wiring 19 Through hole connection portion 100 Memory card

Claims (5)

A substrate on which a first terminal to which a first voltage is applied, a second terminal to which a second voltage is applied, is formed;
A semiconductor memory chip connected to the pads provided on the substrate by wire bonding and electrically connected to the first terminal and the second terminal;
A wiring capacitor formed on the substrate so as to be connected in parallel with the semiconductor memory chip between the first terminal and the second terminal, and for supplying power to the semiconductor memory chip; Prepared,
The wiring capacitor includes a first wiring formed on the substrate and connected to the first terminal, a second wiring formed on the substrate and connected to the second terminal, and the first wiring And an insulator provided between the second wiring and the second wiring. The semiconductor memory chip is connected in parallel with the wiring capacitor between the first terminal and the second terminal so as to be connected to the pad by wire bonding and to be supplied with power from the wiring capacitor. The memory card according to claim 1, further comprising a controller chip that controls the memory card. One end of the first wiring is connected to the first terminal, and further, the first wiring is connected to the first terminal at any part from one end to the other end of the first wiring. The memory card according to claim 1 or 2, wherein:   4. The memory card according to claim 1, wherein the first and second wirings are formed in a spiral shape.   4. The memory card according to claim 1, wherein the first and second wirings are formed in a comb shape.

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